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| REJ09B0187-0100 16 M16C/80 Group Hardware Manual RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES Before using this material, please visit our website to verify that this is the most updated document available. Rev. 1.00 Revision date: Aug. 02, 2005 www.renesas.com Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. 2. 3. 4. 5. 6. 7. 8. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http:// www.renesas.com). When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/ or the country of destination is prohibited. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. How to Use This Manual 1.Introduction This hardware manual provides detailes information on the M16C/80 group microcomputers. Users are exoected to have basic knowledge of electric circuits,logical circuits and microcomputers. 2.Register Diagram The symbols,and descriptions,used for bit function in each register are shown below. XXX register b7 b6 b5 b4 b3 b2 b1 b0 *1 Symbol XXX Address XXX When reset 0016 *2 0 Bit symbol XXX0 Bit name XXX select bit b1 b0 Function 1 0 1 1 0 1 0 1 : : : : XXX XXX Inhibited XXX R W XXX1 Nothing is assigned. When write, set "0". When read, its content is indeterminate. Must always b set to "0" Reserved bit XXX 4 XXX 5 XXX 6 Function varies with each operation mode *3 *1 XXX 7 XXX flag Blank:Set to "0" or "1" according to intended use 0: Set to "0" 1: Set to "1" X: Nothing is assigned *2 R: Read O.....Possible to read X.....Impossible to read -.....Nothing is assigned Write O.....Possible to write X.....Written value is invalid When write, value can be "0" or "1" -.....Nothing is assigned W: *3 Terms to use here are explained as follows. * Nothing is assigned Nothing is assigned to the bit concerned. When write, set "0" for new function in future plan. * Inhibited Not select. The operation at having selected is not guaranteed. * Reserved bit Reserved bit. Set the specified value. * Function varies with each operation mode Bit function changes according to the mode of peripheral functions. * Must be fixed to "0" in A mode Set the bit concerned to "0" in A mode. * Invalid in A mode The bit concerned has no function in A mode. Set the specified value. * Valid when bit A="0" When bit A is "1", the bit concerned has no function. When bit A is "0", the bit concerned has function. 3. M16C Family Documents The following documents were prepared for the M16C family. (1) Document Short Sheet Data Sheet Hardware Manual Contents Hardware overview Hardware overview and electrical characteristics Hardware specifications (pin assignments, memory maps, peripheral specifications, electrical characteristics, timing charts) Software Manual Detailed description of assembly instructions and microcomputer performance of each instruction Application Note * Application examples of peripheral functions * Sample programs * Introduction to the basic functions in the M16C family * Programming method with Assembly and C languages RENESAS TECHNICAL UPDATE Preliminary report about the specification of a product, a document, etc. NOTES : 1. Before using this material, please visit the our website to verify that this is the most updated document available. Table of Contents Quick Reference by Address ____________________________________ B-1 1. Overview ___________________________________________________ 1 1.1 Features ......................................................................................................................... 1 1.2 Applications .................................................................................................................. 1 1.3 Pin Configuration .......................................................................................................... 2 1.4 Block Diagram ............................................................................................................... 5 1.5 Performance Outline..................................................................................................... 6 1.6 Pin Description (1) ........................................................................................................ 9 2. Memory ___________________________________________________ 12 3. Central Processing Unit (CPU) ________________________________ 13 4. Reset _____________________________________________________ 18 5. SFR _______________________________________________________ 22 6. Processor Mode ____________________________________________ 26 7. Bus _______________________________________________________ 30 7.1 Bus Settings ................................................................................................................ 30 7.2 Bus Control ................................................................................................................. 33 8. Clock Generating Circuit _____________________________________ 43 8.1 Example of oscillator circuit ...................................................................................... 43 8.2 Clock Control .............................................................................................................. 44 8.3 Clock Output ............................................................................................................... 47 8.4 Stop Mode.................................................................................................................... 48 8.5 Wait Mode .................................................................................................................... 50 8.6 Status Transition of BCLK ......................................................................................... 51 8.7 Power Saving .............................................................................................................. 53 8.8 Protection .................................................................................................................... 55 9. Interrupt Outline ____________________________________________ 56 9.1 Types of Interrupts ...................................................................................................... 56 9.2 Software Interrupts ..................................................................................................... 57 9.3 Hardware Interrupts .................................................................................................... 58 9.4 High-speed interrupts................................................................................................. 59 9.5 Interrupts and Interrupt Vector Tables ...................................................................... 59 A-1 9.6 Interrupt control registers .......................................................................................... 62 9.7 Interrupt Enable Flag (I Flag) ..................................................................................... 64 9.8 Interrupt Request Bit .................................................................................................. 64 9.9 Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL) ... 64 9.10 Rewrite the interrupt control register ..................................................................... 65 9.11 Interrupt Sequence ................................................................................................... 66 9.12 Interrupt Response Time .......................................................................................... 66 9.13 Changes of IPL When Interrupt Request Acknowledged ...................................... 68 9.14 Saving Registers ....................................................................................................... 68 9.15 Return from Interrupt Routine ................................................................................. 69 9.16 Interrupt Priority........................................................................................................ 69 9.17 Interrupt Resolution Circuit ..................................................................................... 69 ______ 9.18 INT Interrupts ............................................................................................................ 71 ______ 9.19 NMI Interrupt.............................................................................................................. 72 9.20 Key Input Interrupt .................................................................................................... 72 9.21 Address Match Interrupt .......................................................................................... 73 9.22 Precautions for Interrupts ........................................................................................ 74 10. Watchdog Timer ___________________________________________ 78 11. DMAC ____________________________________________________ 80 12. Timer_____________________________________________________ 92 13. Timer A ___________________________________________________ 94 14. Timer B __________________________________________________ 106 15. Three-phase motor control timers' functions ____________________112 16. Serial I/O _________________________________________________ 124 17. Clock synchronous serial I/O mode __________________________ 136 18. Clock asynchronous serial I/O (UART) mode __________________ 144 19. Clock-asynchronous serial I/O mode (compliant with the SIM interface) ___ 151 20. UARTi Special Mode Register (i = 2 to 4) ______________________ 155 21. A/D Converter ____________________________________________ 166 22. D/A Converter ____________________________________________ 176 23. CRC Calculation Circuit ____________________________________ 178 24. XY Converter _____________________________________________ 180 A-2 25. DRAM Controller __________________________________________ 183 26. Programmable I/O Ports ____________________________________ 190 27. Usage Precaution _________________________________________ 208 28. Electrical characteristics ___________________________________ 225 29. Flash Memory Version _____________________________________ 271 30. CPU Rewrite Mode ________________________________________ 274 31. Parallel I/O Mode __________________________________________ 290 32. Standard serial I/O mode ___________________________________ 295 32.1 Overview of standard serial I/O mode 1 (clock synchronized) ........................... 296 32.2 Overview of standard serial I/O mode 2 (clock asynchronized) ......................... 311 Package Dimension __________________________________________ 326 Register Index _______________________________________________ 328 Revision History ______________________________________________ C-1 A-3 Quick Reference by Address Address 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 002016 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 004016 004116 004216 004316 004416 DRAMCONT 183 DRAM control register DRAM refresh interval set register REFCNT 185 002116 Emulator interrupt vector table register Register Symbol page Address 006016 006116 006216 006316 Register Symbol page PM0 PM1 CM0 CM1 WCR Address match interrupt enable register AIER PRCR Protect register External data bus width control register DS Main clock division register MCD Watchdog timer start register Watchdog timer control register WDTS WDC Processor mode register 0 Processor mode register 1 System clock control register 0 System clock control register 1 Wait control register 27 28 46 40 73 55 31 47 79 006416 006516 006616 006716 006816 DMA0 006916 Timer interrupt control register B5 interrupt control register 006A16 DMA2 interrupt control register 006B16 UART2 receive/ACK interrupt control register 006C16 Timer A0 interrupt control register 006D16 UART3 receive/ACK interrupt control register 006E16 Timer A2 interrupt control register 006F16 UART4 receive/ACK interrupt control register 007016 Timer A4 interrupt control register DM0IC TB5IC DM2IC S2RIC TA0IC S3RIC 63 TA2IC S4RIC Address match interrupt register 0 RMAD0 73 TA4IC 007116 Bus collision detection(UART3) interrupt control register BCN3IC 007216 UART0 receive interrupt control register S0RIC 007316 A/D 007416 UART1 007516 007616 Timer 007716 007816 Timer 007916 007A16 007B16 Address match interrupt register 1 RMAD1 73 conversion interrupt control register receive interrupt control register ADIC S1RIC B1 interrupt control register B3 interrupt control register TB1IC TB3IC INT5IC INT3IC INT1IC 63 63 63 63 63 Address match interrupt register 2 RMAD2 73 INT5 interrupt control register interrupt control register interrupt control register Address match interrupt register 3 RMAD3 73 007C16 INT3 007D16 007E16 INT1 007F16 * EIAD 008016 008116 008216 008316 008416 008516 008616 008716 008816 Emulator interrupt detect register * EITD Emulator protect register * EPRR DMA1 interrupt control register 008916 UART2 transmit/NACK interrupt control register 008A16 DMA3 interrupt control register 008B16 UART3 transmit/NACK interrupt control register 008C16 Timer A1 interrupt control register 008D16 UART4 transmit/NACK interrupt control register 008E16 Timer A3 interrupt control register DM1IC S2TIC DM3IC S3TIC 63 TA1IC S4TIC TA3IC ROM areaset register Debug monitor area set register Expansion area set register 0 Expansion area set register 1 Expansion area set register 2 Expansion area set register 3 * ROA * DBA * EXA0 * EXA1 * EXA2 * EXA3 008F16 Bus collision detection(UART2) interrupt control register BCN2IC 009016 UART0 transmit interrupt control register S0TIC 009116 Bus collision detection(UART4) interrupt control register BCN4IC 009216 UART1 transmit interrupt control register S1TIC 009316 009416 009516 009616 009716 009816 009916 009A16 009B16 009C16 INT2 009D16 009E16 INT0 009F16 00A016 00A116 00A216 00A316 00A416 Key input interrupt control register Timer B0 interrupt control register Timer B2 interrupt control register Timer B4 interrupt control register INT4 interrupt control register interrupt control register KUPIC TB0IC TB2IC TB4IC INT4IC INT2IC INT0IC RLVL 63 63 63 63 63 49 interrupt control register Exit priority register B-1 Blank spaces are reserved. No access is allowed. Quick Reference by Address Address 02C016 02C116 02C216 02C316 02C416 02C516 02C616 02C716 02C816 02C916 02CA16 02CB16 02CC16 02CD16 02CE16 02CF16 02D016 02D116 02D216 02D316 02D416 02D516 02D616 02D716 02D816 02D916 02DA16 02DB16 02DC16 02DD16 02DE16 02DF16 02E016 02E116 02E216 02E316 02E416 02E516 02E616 02E716 02E816 02E916 02EA16 02EB16 02EC16 02ED16 02EE16 02EF16 02F016 02F116 02F216 02F316 02F416 02F516 02F616 02F716 02F816 02F916 02FA16 02FB16 Register Symbol page Address 030016 030116 030216 030316 030416 030516 030616 030716 030816 030916 Register Symbol page X0 register ,Y0 register X1 register, Y1 register X2 register ,Y2 register X3 register,Y3 register X4 register , Y4 register X5 register , Y5 register X6 register ,Y6 register X7 register ,Y7 register X8 register , Y8 register X9 register,Y9 register X10 register,Y10 register X11 register, Y11 register X12 register, Y12 register X13 register,Y13 register X14 register,Y14 register X15 register, Y15 register XY control register X0R,Y0R X1R,Y1R X2R,Y2R X3R,Y3R X4R,Y4R X5R,Y5R X6R,Y6R X7R,Y7R X8R,Y8R X9R,Y9R X10R,Y10R X11R,Y11R X12R,Y12R X13R,Y13R X14R,Y14R X15R,Y15R XYC 181 Timer B3, 4, 5 count start flag Timer A1-1 register Timer A2-1 register Timer A4-1 register TBSR TA11 TA21 TA41 107 114 Three-phase PWM control register 0 Three-phase PWM control register 1 030A16 Thrree-phase output buffer register 0 030B16 Thrree-phase output buffer register 1 030C16 Dead time timer 030E16 030F16 031016 031116 031216 031316 031416 031516 031616 031716 031816 031916 031A16 031B16 INVC0 112 INVC1 113 IDB0 IDB1 DTT 030D16 Timer B2 interrupt occurrence frequency set counter ICTB2 Timer B3 register Timer B4 register Timer B5 register TB3 TB4 TB5 107 Timer B3 mode register B4 mode register 031D16 Timer B5 mode register 031C16 Timer 031E16 031F16 TB3MR 106 TB4MR TB5MR IFSR 71 Interrupt cause select register 180 032016 032116 032216 032316 032416 032516 032616 032716 032816 032916 032A16 032B16 UART3 special mode register 3 UART3 special mode register 2 UART3 special mode register UART3 transmit/receive mode register UART3 bit rate generator UART3 transmit buffer register U3SMR3 136 U3SMR2 135 U3SMR 134 U3MR 130 U3BRG 129 U3TB 129 132 133 129 032C16 UART3 032D16 UART3 032E16 032F16 033016 033116 033216 033316 033416 transmit/receive control register 0 U3C0 transmit/receive control register 1 U3C1 U3RB UART3 receive buffer register UART4 special mode register 3 UART4 special mode register 2 UART4 special mode register U4SMR3 U4SMR2 U4SMR UART4 transmit/receive mode register U4MR U4BRG UART4 bit rate generator UART4 transmit buffer register U4TB U4C0 U4C1 U4RB 136 135 134 130 129 UART2 special mode register 3 UART2 special mode register 2 033716 UART2 special mode register 033516 033616 033816 033916 033A16 033B16 UART2 transmit/receive mode register UART2 bit rate generator UART2 transmit buffer register U2SMR3 136 U2SMR2 135 U2SMR 134 U2MR 130 U2BRG 129 U2TB 131 133 129 02FC16 UART4 transmit/receive control register 0 02FD16 UART4 transmit/receive control register 1 02FE16 02FF16 132 133 129 033C16 UART2 033D16 UART2 033E16 033F16 transmit/receive control register 0 U2C0 transmit/receive control register 1 U2C1 U2RB UART4 receive buffer register UART2 receive buffer register Blank spaces are reserved. No access is allowed. B-2 Quick Reference by Address Address 034016 034116 034216 034316 034416 034516 034616 034716 034816 034916 034A16 034B16 034C16 034D16 034E16 034F16 035016 035116 035216 035316 035416 035516 035616 035716 Register Symbol page Address 038016 038116 038216 038316 038416 038516 038616 038716 038816 038916 038A16 038B16 038C16 038D16 038E16 038F16 039016 039116 039216 039316 039416 039516 039616 039716 039916 039A16 D/A 039B16 039C16 D/A 039D16 039E16 039F16 Register Symbol page Count start flag Clock prescaler reset flag One-shot start flag Trigger select register Up-down flag Timer A0 register Timer A1 register Timer A2 register Timer A3 register Timer A4 register Timer B0 register Timer B1 register Timer B2 register TABSR 95 CPSRF 96 ONSF TRGSR 95 UDF A/D register 0 A/D register 1 A/D register 2 A/D register 3 A/D register 4 A/D register 5 A/D register 6 A/D register 7 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 169 TA0 TA1 TA2 TA3 TA4 TB0 TB1 TB2 95 107 A/D control register 2 ADCON2 169 ADCON0 168 ADCON1 DA0 177 DA1 DACON 177 177 Timer A0 mode register Timer A1 mode register 035816 Timer A2 mode register 035916 Timer A3 mode register 035A16 Timer A4 mode register 035B16 Timer B0 mode register 035C16 Timer B1 mode register 035D16 Timer B2 mode register 035E16 035F16 036016 036116 036216 036316 036416 036516 036616 036716 036816 036916 036A16 036B16 TA0MR 94 TA1MR TA2MR TA3MR TA4MR TB0MR 106 TB1MR TB2MR A/D control register 0 A/D control register 1 039816 D/A register 0 register 1 control register UART0 transmit/receive mode register UART0 bit rate generator UART0 transmit buffer register U0MR 130 U0BRG 129 U0TB 129 131 133 129 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 03A916 03AA16 03AB16 UART0 transmit/receive control register 0 U0C0 UART0 transmit/receive control register 1 U0C1 UART0 receive buffer register UART1 transmit/receive mode register U0RB UART1 bit rate generator UART1 transmit buffer register U1MR 130 U1BRG 129 U1TB U1C0 U1C1 U1RB 131 133 129 036C16 UART1 transmit/receive control register 0 036D16 UART1 transmit/receive control register 1 036E16 036F16 037116 037216 037316 037416 037516 03AC16 03AD16 03AE16 03AF16 03B016 03B116 03B216 03B316 03B416 03B516 UART1 receive buffer register 037016 UART transmit/receive control register 2 UCON 134 Flash memory control register 1 Flash memory control register 0 037816 DMA0 request cause select register 037916 DMA1 request cause select register 037A16 DMA2 request cause select register 037B16 DMA3 request cause select register 037616 037716 037C16 037D16 037E16 037F16 FMR1 276 FMR0 DM0SL 82 DM1SL DM2SL DM3SL CRCD 178 CRCIN 03B616 03B716 03B816 03B916 03BA16 03BB16 03BC16 03BD16 03BE16 03BF16 Function select register C Function select register A0 Function select register A1 Function select register B0 Function select register B1 Function select register A2 Function select register A3 Function select register B2 Function select register B3 PSC PS0 PS1 PSL0 PSL1 PS2 PS3 PSL2 PSL3 203 200 202 201 202 203 CRC data register CRC input register Blank spaces are reserved. No access is allowed. B-3 Quick Reference by Address <100-pin version> Address 03C016 03C116 03C216 03C316 03C416 03C516 03C616 03C716 03C816 03C916 03CA16 03CB16 03CC16 03CD16 03CE16 03CF16 03D016 03D116 03D216 03D316 03D416 03D516 03D616 03D716 03D816 03D916 Register Symbol page <144-pin version> Address 03C016 Register Symbol page Port P6 Port P7 Port P6 direction register Port P7 direction register Port P8 Port P9 Port P8 direction register Port P9 direction register Port P10 Port P10 direction register P6 P7 PD6 PD7 P8 P9 PD8 PD9 P10 197 195 197 195 197 PD10 195 Port P6 03C116 Port P7 03C216 Port P6 direction register 03C316 Port P7 direction register 03C416 Port P8 03C516 Port P9 03C616 Port P8 direction register 03C716 Port P9 direction register 03C816 Port P10 03C916 Port P11 03CA16 Port P10 direction register 03CB16 Port P11 direction register 03CC16 Port P12 03CD16 Port P13 03CE16 Port P12 direction register 03CF16 Port P13 direction register 03D016 Port P14 03D116 Port P15 03D216 Port P14 direction register 03D316 Port P15 direction register 03D416 03D516 03D616 03D716 03D816 03D916 P6 P7 PD6 PD7 P8 P9 PD8 PD9 P10 P11 PD10 PD11 P12 P13 PD12 PD13 P14 P15 PD14 PD15 197 195 197 195 197 198 195 196 197 195 198 197 196 195 Pull-up control register 2 03DB16 Pull-up control register 3 03DA16 03DC16 03DD16 03DE16 03DF16 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA16 03EB16 03EC16 03ED16 03EE16 03EF16 03F016 03F116 03F216 03F316 03FC16 03FD16 03FE16 03FF16 PUR2 204 PUR3 205 Pull-up control register 2 Pull-up control register 3 03DC16 Pull-up control register 4 03DA16 03DB16 03DD16 03DE16 03DF16 PUR2 204 PUR3 205 PUR4 Port P0 Port P1 Port P0 direction register Port P1 direction register Port P2 Port P3 Port P2 direction register Port P3 direction register Port P4 Port P5 Port P4 direction register Port P5 direction register P0 P1 PD0 PD1 P2 P3 PD2 PD3 P4 P5 PD4 PD5 197 195 197 195 197 195 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA16 03EB16 03EC16 03ED16 03EE16 03EF16 Port P0 Port P1 Port P0 direction register Port P1 direction register Port P2 (P2) Port P3 (P3) Port P2 direction register Port P3 direction register Port P4 Port P5 Port P4 direction register Port P5 direction register P0 P1 PD0 PD1 P2 P3 PD2 PD3 P4 P5 PD4 PD5 197 195 197 195 197 195 Pull-up control register 0 Pull-up control register 1 PUR0 204 PUR1 03F016 03F116 03F216 03F316 03FC16 03FD16 03FE16 Pull-up control register 0 Pull-up control register 1 PUR0 204 PUR1 Port control register PCR 206 03FF16 Port control register PCR 206 Blank spaces are reserved. No access is allowed. B-4 M16C/80 Group 1. Overview 1. Overview The M16C/80 group of single-chip microcomputers are built using the high-performance silicon gate CMOS process using a M16C/80 Series CPU core and are packaged in a 100-pin and 144-pin plastic molded QFP. The peripheral functions of 100-pin and 144-pin are common. These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. With 16M bytes of address space, they are capable of executing instructions at high speed. They also feature a built-in multiplier and DMAC, making them ideal for controlling office, communications, industrial equipment, and other high-speed processing applications. 1.1 Features * Memory capacity .................................. ROM (See ROM expansion figure.) RAM 10 to 24 Kbytes * Shortest instruction execution time ...... 50ns (f(XIN)=20MHz) * Supply voltage ..................................... 4.2 to 5.5V (f(XIN)=20MHz) Mask ROM, external ROM and flash memory versions 2.7 to 5.5V (f(XIN)=10MHz) Mask ROM, external ROM and flash memory versions * Low power consumption ...................... 45mA (M30800MC-XXXFP) (f(XIN) = 20MHz without software wait,Vcc=5V) * Interrupts .............................................. 29 internal and 8 external interrupt sources, 5 software interrupt sources; 7 levels (including key input interrupt) * Multifunction 16-bit timer ...................... 5 output timers + 6 input timers * Serial I/O .............................................. 5 channels for UART or clock synchronous * DMAC .................................................. 4 channels (trigger: 31 sources) * DRAMC ................................................ Used for EDO, FP, CAS before RAS refresh, self-refresh * A/D converter ....................................... 10 bits X 8 channels (Expandable up to 10 channels) * D/A converter ....................................... 8 bits X 2 channels * CRC calculation circuit ......................... 1 circuit * XY converter ........................................ 1 circuit * Watchdog timer .................................... 1 line * Programmable I/O ............................... 87 lines:100-pin version, 123 lines:144-pin version _______ * Input port .............................................. 1 line (P85 shared with NMI pin) * Memory expansion .............................. Available (16M bytes) * Chip select output ................................ 4 lines * Clock generating circuit ....................... 2 built-in clock generation circuits (built-in feedback resistance, and external ceramic or quartz oscillator) 1.2 Applications Audio, cameras, office equipment, communications equipment, portable equipment, etc. Rev.1.00 Aug. 02, 2005 Page 1 REJ09B0187-0100 of 329 M16C/80 Group 1. Overview 1.3 Pin Configuration Figures 1.1 and 1.2 show the pin configuration (top view) for 100-pin and Figure 1.3 shows the pin configuration (top view) for 144-pin. PIN CONFIGURATION (top view) P10/D8 P11/D9 P12/D10 P13/D11 P14/D12 P15/D13/INT3 P16/D14/INT4 P17/D15/INT5 P20/A0(/D0) P21/A1(/D1) P22/A2(/D2) P23/A3(/D3) P24/A4(/D4) P25/A5(/D5) P26/A6(/D6) P27/A7(/D7) Vss P30/A8(MA0)(/D8) Vcc P31/A9(MA1)(/D9) P32/A10(MA2)(/D10) P33/A11(MA3)(/D11) P34/A12(MA4)(/D12) P35/A13(MA5)(/D13) P36/A14(MA6)(/D14) P37/A15(MA7)(/D15) P40/A16(MA8) P41/A17(MA9) P42/A18(MA10) P43/A19(MA11) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P07/D7 P06/D6 P05/D5 P04/D4 P03/D3 P02/D2 P01/D1 P00/D0 P107/AN7/KI3 P106/AN6/KI2 P105/AN5/KI1 P104/AN4/KI0 P103/AN3 P102/AN2 P101/AN1 AVSS P100/AN0 VREF AVcc P97/ADTRG/RXD4 /SCL4/STxD4 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 23 45 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 M16C/80 Group P44/CS3/A20(MA12) P45/CS2/A21 P46/CS1/A22 P47/CS0/A23 P50/WRL/WR/CASL P51/WRH/BHE/CASH P52/RD/DW P53/BCLK/ALE/CLKOUT P54/HLDA/ALE P55/HOLD P56/ALE/RAS P57/RDY P60/CTS0/RTS0 P61/CLK0 P62/RxD0 P63/TXD0 P64/CTS1/RTS1/CTS0/CLKS1 P65/CLK1 P66/RxD1 P67/TXD1 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Figure 1.1 Pin configuration for 100-pin version (top view) (1) Rev.1.00 Aug. 02, 2005 Page 2 REJ09B0187-0100 P96/ANEX1/TXD4/SDA4/SRxD4 P95/ANEX0/CLK4 P94/DA1/TB4IN/CTS4/RTS4/SS4 P93/DA0/TB3IN/CTS3/RTS3/SS3 P92/TB2IN/TXD3/SDA3/SRxD3 P91/TB1IN/RXD3/SCL3/STxD3 P90/TB0IN/CLK3 BYTE CNVss P87/XCIN P86/XCOUT RESET XOUT VSS XIN VCC P85/NMI P84/INT2 P83/INT1 P82/INT0 P81/TA4IN/U P80/TA4OUT/U P77/TA3IN P76/TA3OUT P75/TA2IN/W P74/TA2OUT/W P73/CTS2/RTS2/TA1IN/V P72/CLK2/TA1OUT/V P71/RxD2/SCL2/TA0IN/TB5IN (Note) P70/TXD2/SDA2/TA0OUT (Note) Note: This port is N-channel open drain output. Package: 100P6S-A of 329 M16C/80 Group 1. Overview PIN CONFIGURATION (top view) P13/D11 P14/D12 P15/D13/INT3 P16/D14/INT4 P17/D15/INT5 P20/A0(/D0) P21/A1(/D1) P22/A2(/D2) P23/A3(/D3) P24/A4(/D4) P25/A5(/D5) P26/A6(/D6) P27/A7(/D7) Vss P30/A8(MA0)(/D8) Vcc P31/A9(MA1)(/D9) P32/A10(MA2)(/D10) P33/A11(MA3)(/D11) P34/A12(MA4)(/D12) P35/A13(MA5)(/D13) P36/A14(MA6)(/D14) P37/A15(MA7)(/D15) P40/A16(MA8) P41/A17(MA9) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P12/D10 P11/D9 P10/D8 P07/D7 P06/D6 P05/D5 P04/D4 P03/D3 P02/D2 P01/D1 P00/D0 P107/AN7/KI3 P106/AN6/KI2 P105/AN5/KI1 P104/AN4/KI0 P103/AN3 P102/AN2 P101/AN1 AVSS P100/AN0 VREF AVcc P97/ADTRG/RXD4/SCL4/STxD4 P96/ANEX1/TXD4/SDA4/SRxD4 P95/ANEX0/CLK4 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 23 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 45 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 M16C/80 Group P42/A18(MA10) P43/A19(MA11) P44/CS3/A20(MA12) P45/CS2/A21 P46/CS1/A22 P47/CS0/A23 P50/WRL/WR/CASL P51/WRH/BHE/CASH P52/RD/DW P53/BCLK/ALE/CLKOUT P54/HLDA/ALE P55/HOLD P56/ALE/RAS P57/RDY P60/CTS0/RTS0 P61/CLK0 P62/RxD0 P63/TXD0 P64/CTS1/RTS1/CTS0/CLKS1 P65/CLK1 P66/RxD1 P67/TXD1 P70/TXD2/SDA2/TA0OUT (Note) P71/RxD2/SCL2/TA0IN/TB5IN (Note) P72/CLK2/TA1OUT/V P94/DA1/TB4IN/CTS4/RTS4/SS4 P93/DA0/TB3IN/CTS3/RTS3/SS3 P92/TB2IN/TXD3/SDA3/SRxD3 P91/TB1IN/RXD3/SCL3/STxD3 P90/TB0IN/CLK3 BYTE CNVss P87/XCIN P86/XCOUT RESET XOUT VSS XIN VCC P85/NMI P84/INT2 P83/INT1 P82/INT0 P81/TA4IN/U P80/TA4OUT/U P77/TA3IN P76/TA3OUT P75/TA2IN/W P74/TA2OUT/W P73/CTS2/RTS2/TA1IN/V Note: This port is N-channel open drain output. Package: 100P6Q-A Figure 1.2 Pin configuration for 100-pin version (top view) (2) Rev.1.00 Aug. 02, 2005 Page 3 REJ09B0187-0100 of 329 M16C/80 Group 1. Overview PIN CONFIGURATION (top view) P11/D9 P12/D10 P13/D11 P14/D12 P15/D13/INT3 P16/D14/INT4 P17/D15/INT5 P20/A0(/D0) P21/A1(/D1) P22/A2(/D2) P23/A3(/D3) P24/A4(/D4) P25/A5(/D5) P26/A6(/D6) P27/A7(/D7) VSS P30/A8(MA0)(/D8) VCC P120 P121 P122 P123 P124 P31/A9(MA1)(/D9) P32/A10(MA2)(/D10) P33/A11(MA3)(/D11) P34/A12(MA4)(/D12) P35/A13(MA5)(/D13) P36/A14(MA6)(/D14) P37/A15(MA7)(/D15) P40/A16(MA8) P41/A17(MA9) VSS P42/A18(MA10) VCC P43/A19(MA11) 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 P10/D8 P07/D7 P06/D6 P05/D5 P04/D4 P114 P113 P112 P111 P110 P03/D3 P02/D2 P01/D1 P00/D0 P157 P156 P155 P154 P153 P152 P151 VSS P150 VCC P107/AN7/KI3 P106/AN6/KI2 P105/AN5/KI1 P104/AN4/KI0 P103/AN3 P102/AN2 P101/AN1 AVSS P100/AN0 VREF AVCC P97/ADTRG/RXD4 /SCL4/STxD4 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 1 2 3 45 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 M16C/80 Group 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 P44/CS3/A20(MA12) P45/CS2/A21 P46/CS1/A22 P47/CS0/A23 P125 P126 P127 P50/WRL/WR/CASL P51/WRH/BHE/CASH P52/RD/DW P53/BCLK/ALE/CLKOUT P130 P131 VCC P132 VSS P133 P54/HLDA/ALE P55/HOLD P56/ALE/RAS P57/RDY P134 P135 P136 P137 P60/CTS0/RTS0 P61/CLK0 P62/RXD0 P63/TXD0 P64/CTS1/RTS1/CTS0/CLKS1 P65/CLK1 VSS P66/RXD1 VCC P67/TXD1 P70/TXD2/SDA2/TA0OUT Figure 1.3 Pin configuration for 144-pin version (top view) Rev.1.00 Aug. 02, 2005 Page 4 REJ09B0187-0100 of 329 P145 P144 P143 P142 P141 P140 BYTE CNVSS P87/XCIN P86/XCOUT RESET XOUT VSS XIN VCC P85/NMI P84/INT2 P83/INT1 P82/INT0 P81/TA4IN/U P80/TA4OUT/U P77/TA3IN P76/TA3OUT P75/TA2IN/W P74/TA2OUT/W P73/CTS2/RTS2/TA1IN/V P72/CLK2/TA1OUT/V (Note) P71/RXD2/SCL2/TA0IN/TB5IN (Note) P96/ANEX1/TXD4/SDA4/SRxD4 P95/ANEX0/CLK4 P94/DA1/TB4IN/CTS4/RTS4/SS4 P93/DA0/TB3IN/CTS3/RTS3/SS3 P92/TB2IN/TXD3/SDA3/SRxD3 P91/TB1IN/RXD3/SCL3/STxD3 P90/TB0IN/CLK3 P146 Note: This port is N-channel open drain output. Package: 144P6Q-A M16C/80 Group 1. Overview 1.4 Block Diagram Figure 1.4 is a block diagram of the M16C/80 group. 8 8 8 8 8 8 8 I/O ports Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Port P6 Port P7 Internal peripheral functions Timer A/D converter (10 bits X 8 channels Expandable up to 10 channels) UART /clock synchronous SI/O (8 bits X 5 channels) XY converter (16 bits X 16 bits) CRC arithmetic circuit (CCITT) 12 (Polynomial : X16+X +X 5+1) System clock generator XIN - XOUT XCIN - XCOUT 8 Timer TA0 (16 bits) Timer TA1 (16 bits) Timer TA2 (16 bits) Timer TA3 (16 bits) Timer TA4 (16 bits) Timer TB0 (16 bits) Timer TB1 (16 bits) Timer TB2 (16 bits) Timer TB3 (16 bits) Timer TB4 (16 bits) Timer TB5 (16 bits) Port P8 Memory ROM (Note 1) 7 Port P85 RAM (Note 2) M16C/80 series 16-bit CPU core Registers R0H R0H R1H R1H R2 R0L R0L R1L Watchdog timer (15 bits) D/A converter (8 bits X 2 channels) R1L R2 R3 A0 A1 FB SB FLG INTB ISP USP PC SVF SVP VCT DRAM controller DRAM controller Multiplier Port P9 Port P10 8 8 Port P15 Port P14 Port P13 Port P12 Port P11 8 Note 1: ROM size depends on MCU type. Note 2: RAM size depends on MCU type. Note 3: Ports P11 to P15 exist in 144-pin version. 7 8 8 5 (Note 3) Figure 1.4 Block diagram of the M16C/80 group Rev.1.00 Aug. 02, 2005 Page 5 REJ09B0187-0100 of 329 M16C/80 Group 1. Overview 1.5 Performance Outline Table 1.1 is a performance outline of M16C/80 group. Table 1.1 Performance outline of M16C/80 group Item Number of basic instructions Shortest instruction execution time Memory ROM capacity RAM I/O port 100-pin Input port Multifunction timer Serial I/O 144-pin P85 TA0, TA1, TA2, TA3,TA4 TB0, TB1, TB2, TB3, TB4, TB5 UART0, UART1, UART2, UART3, UART4 Performance 106 instructions 50ns(f(XIN)=20MHz) See ROM expansion figure. 10 to 24 K bytes P0 to P10 (except P85) 8-bit x 10, 7-bit x 1 P0 to P15 (except P85) 8-bit x 13, 7-bit x 2, 5-bit x 1 1 bit x 1 16 bits x 5 16 bits x 6 (UART or clock synchronous) x 5 10 bits x (8 + 2) channels 8 bits x 2 4 channels CAS before RAS refresh, self-refresh, EDO, FP CRC-CCITT 16 bits X 16 bits 15 bits x 1 (with prescaler) 29 internal and 8 external sources, 5 software sources, 7 levels 2 built-in clock generation circuits (built-in feedback resistance, and external ceramic or quartz oscillator) 4.2 to 5.5V (f(XIN)=20MHz) Mask ROM, external ROM and flash memory versions 2.7 to 5.5V (f(XIN)=10MHz) Mask ROM, external ROM and flash memory versions 45mA (f(XIN) = 20MHz without software wait,Vcc=5V) Mask ROM 128 Kbytes version 5V 5mA Available (up to 16M bytes) -40 to 85oC CMOS high performance silicon gate 100-pin and 144-pin plastic mold QFP A/D converter D/A converter DMAC DRAM controller CRC calculation circuit XY converter Watchdog timer Interrupt Clock generating circuit Supply voltage Power consumption I/O I/O withstand voltage characteristics Output current Memory expansion Operating ambient temperature Device configuration Package Rev.1.00 Aug. 02, 2005 Page 6 REJ09B0187-0100 of 329 M16C/80 Group 1. Overview Renesas plans to release the following products in the M16C/80 group: (1) Support for mask ROM version, external ROM version and flash memory version (2) ROM capacity (3) Package 100P6S-A : Plastic molded QFP (mask ROM version and flash memory version) 100P6Q-A : Plastic molded QFP (mask ROM version and flash memory version) 144P6Q-A : Plastic molded QFP (mask ROM version and flash memory version) ROM Size (Byte) M30805SGP-BL M30803SFP/GP-BL M30802SGP-BL M30800SFP/GP-BL M30805SGP M30803SFP/GP M30802SGP M30800SFP/GP M30803MG-XXXFP/GP M30805MG-XXXGP M30800MC-XXXFP/GP M30802MC-XXXGP Mask ROM version M30803FGFP/GP M30805FGGP M30800FCFP/GP M30802FCGP Flash memory version External ROM version External ROM 256K 128K Figure 1.5 ROM expansion The M16C/80 group products currently supported are listed in Table 1.2. Table 1.2 M16C/80 group Type No M30800MC-XXXFP M30800MC-XXXGP M30802MC-XXXGP M30803MG-XXXFP M30803MG-XXXGP M30805MG-XXXGP M30800FCFP M30800FCGP M30802FCGP M30803FGFP M30803FGGP M30805FGGP M30800SFP M30800SGP M30802SGP M30803SFP M30803SGP M30805SGP M30800SFP-BL M30800SGP-BL M30802SGP-BL M30803SFP-BL M30803SGP-BL M30805SGP-BL 24K bytes 10K bytes 24K bytes 10K bytes 256K bytes 20K bytes 128K bytes 10K bytes 256K bytes 20K bytes ROM capacity 128K bytes RAM capacity 10K bytes Package type 100P6S-A 100P6Q-A 144P6Q-A 100P6S-A 100P6Q-A 144P6Q-A 100P6S-A 100P6Q-A 144P6Q-A 100P6S-A 100P6Q-A 144P6Q-A 100P6S-A 100P6Q-A 144P6Q-A 100P6S-A 100P6Q-A 144P6Q-A 100P6S-A 100P6Q-A 144P6Q-A 100P6S-A 100P6Q-A 144P6Q-A External ROM version with built-in boot loader External ROM version Flash memory version Remarks Mask ROM version Rev.1.00 Aug. 02, 2005 Page 7 REJ09B0187-0100 of 329 M16C/80 Group 1. Overview Type No. M 3 0 8 0 2 M C - X X X G P - BL Boot loader Package type: FP : Package GP : Package 100P6S-A 100P6Q-A, 144P6Q-A ROM No. Omitted for blank external ROM version and flash memory version ROM capacity: C : 128K bytes G : 256K bytes Memory type: M : Mask ROM version S : External ROM version F : Flash memory version Shows RAM capacity, pin count, etc (The value itself has no specific meaning) M16C/80 Group M16C Family Figure 1.6 Product Numbering System Rev.1.00 Aug. 02, 2005 Page 8 REJ09B0187-0100 of 329 M16C/80 Group 1. Overview 1.6 Pin Description (1) Pin name VCC, VSS CNVSS Signal name Power supply input CNVSS I I/O type Function Supply 4.2 (2.7) to 5.5 V to the VCC pin. Supply 0 V to the VSS pin. This pin switches between processor modes. Connect it to the VSS when operating in single-chip or memory expansion mode after reset. Connect it to the VCC when in microprocessor mode after reset. An "L" on this input resets the microcomputer. These pins are provided for the main clock generating circuit. Connect a ceramic resonator or crystal between the XIN and the XOUT pins. To use an externally derived clock, input it to the XIN pin and leave the XOUT pin open. This pin selects the width of an data bus in the external area 3. A 16-bit width is selected when this input is "L"; an 8-bit width is selected when this input is "H". This input must be fixed to either "H" or "L". When not using the external bus, connect this pin to VSS. This pin is a power supply input for the A/D converter. Connect this pin to VCC. This pin is a power supply input for the A/D converter. Connect this pin to VSS. I I/O This pin is a reference voltage input for the A/D converter. This is an 8-bit CMOS I/O port. It has an input/output port direction register that allows the user to set each pin for input or output individually. When set for input in single chip mode, the user can specify in units of four bits via software whether or not they are tied to a pull-up resistance. In memory expansion and microprocessor mode, an built-in pull-up resistance cannot be used. However, it is possible to select pull-up resistance presence to the usable port as I/ O port by setting. When set as a separate bus, these pins input and output data (D0-D7). This is an 8-bit I/O port equivalent to P0. P15 to P17 also function as external interrupt pins as selected by software. When set as a separate bus, these pins input and output data (D8-D15). This is an 8-bit I/O port equivalent to P0. These pins output 8 low-order address bits (A0-A7). If a multiplexed bus is set, these pins input and output data (D0-D7) and output 8 low-order address bits (A0-A7) separated in time by multiplexing. This is an 8-bit I/O port equivalent to P0. These pins output 8 middle-order address bits (A8-A15). If the external bus is set as a 16-bit wide multiplexed bus, these pins input and output data (D8-D15) and output 8 middle-order address bits (A8-A15) separated in time by multiplexing. If accessing to DRAM area, these pins output row address and column address separated in time by multiplexing. RESET XIN XOUT Reset input Clock input Clock output I I O BYTE External data bus width select input I AVCC Analog power supply input Analog power supply input Reference voltage input I/O port P0 AVSS VREF P00 to P07 D0 to D7 P10 to P17 D8 to D15 P20 to P27 A0 to A7 A0/D0 to A7/D7 P30 to P37 A8 to A15 A8/D8 to A15/D15 I/O port P3 I/O port P2 I/O port P1 I/O I/O I/O I/O O I/O I/O O I/O MA0 to MA7 O Rev.1.00 Aug. 02, 2005 Page 9 REJ09B0187-0100 of 329 M16C/80 Group 1. Overview Pin Description (2) Pin name P40 to P47 A16 to A22, A23 CS0 to CS3 MA8 to MA12 P50 to P57 I/O port P5 Signal name I/O port P4 I/O type I/O O O O I/O Function This is an 8-bit I/O port equivalent to P0. These pins output 8 high-order address bits (A16-A22, A23). Highest address bit (A23) outputs inversely. These pins output CS0-CS3 signals. CS0-CS3 are chip select signals used to specify an access space. If accessing to DRAM area, these pins output row address and column address separated in time by multiplexing. This is an 8-bit I/O port equivalent to P0. P53 in this port outputs a divide-by-8 or divide-by-32 clock of XIN or a clock of the same frequency as XCIN as selected by software. Output WRL, WRH (WR and BHE), RD, BCLK, HLDA, and ALE signals. WRL and WRH, and BHE and WR can be switched using software control. WRL, WRH, and RD selected With a 16-bit external data bus, data is written to even addresses when the WRL signal is "L" and to the odd addresses when the WRH signal is "L". Data is read when RD is "L". WR, BHE, and RD selected Data is written when WR is "L". Data is read when RD is "L". Odd addresses are accessed when BHE is "L". Use this mode when using an 8-bit external data bus. While the input level at the HOLD pin is "L", the microcomputer is placed in the hold state. While in the hold state, HLDA outputs an "L" level. ALE is used to latch the address. While the input level of the RDY pin is "L", the bus of microcomputer is in the wait state. When accessing to DRAM area while DW signal is "L", write to DRAM. CASL and CASH show timing when latching to line address. When CASL accesses to even address, and CASH to odd, these two pins become "L". RAS signal shows timing when latching to row address. This is an 8-bit I/O port equivalent to P0. When set for input in single chip mode, microprocessor mode and memory expansion mode the user can specify in units of four bits via software whether or not they are tied to a pull-up resistance. Pins in this port also function as UART0 and UART1 I/O pins as selected by software. This is an 8-bit I/O port equivalent to P6 (P70 and P71 are N-channel open drain output). Pins in this port also function as timer A0-A3, timer B5 or UART2 I/O pins as selected by software. P80 to P84, P86, and P87 are I/O ports with the same functions as P6. Using software, they can be made to function as the I/O pins for timer A4 and the input pins for external interrupts. P86 and P87 can be set using software to function as the I/O pins for a sub clock generation circuit. In this case, connect a quartz oscillator between P86 (XCOUT pin) and P87 (XCIN pin). P85 is an input-only port that also functions for NMI. The NMI interrupt is generated when the input at this pin changes from "H" to "L". The NMI function cannot be canceled using software. The pull-up cannot be set for this pin. This is an 8-bit I/O port equivalent to P6. Pins in this port also function as UART3 and UART4 I/O pins, Timer B0-B4 input pins, D/A converter output pins, A/D converter extended input pins, or A/D trigger input pins as selected by software. This is an 8-bit I/O port equivalent to P6. Pins in this port also function as A/D converter input pins. Furthermore, P104-P107 also function as input pins for the key input interrupt function. WRL / WR, WRH / BHE, RD, BCLK, HLDA, HOLD, ALE, RDY O O O O O I O I DW, CASL, CASH, RAS P60 to P67 I/O port P6 O O O O I/O P70 to P77 I/O port P7 I/O P80 to P84, P86, P87, P85 I/O port P8 I/O I/O I/O I/O port P85 I P90 to P97 I/O port P9 I/O P100 to P107 I/O port P10 I/O Rev.1.00 Aug. 02, 2005 Page 10 REJ09B0187-0100 of 329 M16C/80 Group 1. Overview Pin Description (3) Pin name P110 to P114 (Note) P120 to P127 (Note) P130 to P137 (Note) P140 to P146 (Note) P150 to P157 (Note) I/O port P13 I/O port P14 II/O II/O This is an 8-bit I/O port equivalent to P6. This is an 7-bit I/O port equivalent to P6. Signal name I/O port P11 I/O type II/O Function This is an 5-bit I/O port equivalent to P6. I/O port P12 II/O This is an 8-bit I/O port equivalent to P6. I/O port P15 II/O This is an 8-bit I/O port equivalent to P6. Note : Port P11 to P15 exist in 144-pin version. Operation of Functional Blocks The M16C/80 group accommodates certain units in a single chip. These units include ROM and RAM to store instructions and data and the central processing unit (CPU) to execute arithmetic/logic operations. Also included are peripheral units such as timers, serial I/O, D/A converter, DMAC, CRC calculation circuit, A/D converter, DRAM controller and I/O ports. The following explains each unit. Rev.1.00 Aug. 02, 2005 Page 11 REJ09B0187-0100 of 329 M16C/80 Group 2. Memory 2. Memory Figure 2.1 is a memory map of the M16C/80 group. The address space extends the 16 Mbytes from address 00000016 to FFFFFF16. From FFFFFF16 down is ROM. For example, in the M30800MC-XXXFP, there is 128K bytes of internal ROM from FE000016 to FFFFFF16. The vector table for fixed interrupts such _______ as the reset and NMI are mapped to FFFFDC16 to FFFFFF16. The starting address of the interrupt routine is stored here. The address of the vector table for timer interrupts, etc., can be set as desired using the internal register (INTB). See the section on interrupts for details. From 00040016 up is RAM. For example, in the M30800MC-XXXFP, 10 Kbytes of internal RAM is mapped to the space from 00040016 to 002BFF16. In addition to storing data, the RAM also stores the stack used when calling subroutines and when interrupts are generated. The SFR area is mapped to 00000016 to 0003FF16. This area accommodates the control registers for peripheral devices such as I/O ports, A/D converter, serial I/O, and timers, etc. Figures 5.1 to 5.4 are location of peripheral unit control registers. Any part of the SFR area that is not occupied is reserved and cannot be used for other purposes. The special page vector table is mapped to FFFE0016 to FFFFDB16. If the starting addresses of subroutines or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions can be used as 2-byte instructions, reducing the number of program steps. In memory expansion mode and microprocessor mode, a part of the spaces are reserved and cannot be used. For example, in the M30800MC-XXXFP, the following spaces cannot be used. * The space between 002C0016 and 00800016 (Memory expansion and microprocessor modes) * The space between F0000016 and FDFFFF16 (Memory expansion mode) 00000016 SFR area For details, see Figures 5.1 to 5.4 FFFE0016 <100-pin version> Type No. M30800MC/FC M30803MG/FG M30800S M30803S Address XXXXXX16 002BFF16 0053FF16 Address YYYYYY16 FE000016 FC000016 00040016 Internal RAM area XXXXXX16 Internal reserved area (Note 1) Special page vector table 00800016 External area <144-pin version> Type No. M30802MC/FC M30805MG/FG M30802S M30805S Address XXXXXX16 002BFF16 0053FF16 002BFF16 0063FF16 Address YYYYYY16 FE000016 FC000016 FFFFDC16 Undefined instruction Overflow BRK instruction Address match Watchdog timer F0000016 YYYYYY16 Internal reserved area (Note 2) Internal ROM area FFFFFF16 FFFFFF16 NMI Reset Note 1: During memory expansion and microprocessor modes, can not be used. Note 2: In memory expansion mode, can not be used. Figure 2.1 Memory map Rev.1.00 Aug. 02, 2005 Page 12 REJ09B0187-0100 of 329 M16C/80 Group 3. Central Processing Unit (CPU) 3. Central Processing Unit (CPU) The CPU has a total of 28 registers shown in Figure 3.1. Eight of these registers (R0, R1, R2, R3, A0, A1, SB and FB) come in two sets; therefore, these have two register banks. General register b31 b15 b0 FLG R2 R3 R0H R1H R2 b23 Flag register R0L R1L Data register (Note) R3 A0 Address register (Note) A1 SB FB USP ISP INTB PC Static base register (Note) Frame base register (Note) User stack pointer Interrupt stack pointer Interrupt table register Program counter High-speed interrupt register b23 b15 b0 SVF SVP VCT Flag save register PC save register Vector register DMAC related register b15 b7 b0 DMD0 DMD1 DCT0 DMA transfer count register DCT1 DRC0 b23 DMA mode register DRC1 DMA0 DMA1 DSA0 DSA1 DRA0 DRA1 DMA transfer count reload register DMA memory address register DMA SFR address register DMA memory address reload register Note: These registers have two register banks. Figure 3.1 Central processing unit register Rev.1.00 Aug. 02, 2005 Page 13 REJ09B0187-0100 of 329 M16C/80 Group 3. Central Processing Unit (CPU) (1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, R3, R2R0 and R3R1) Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and arithmetic/logic operations. Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H), and low-order bits as (R0L/R1L). Registers R2 and R0, as well as R3 and R1 can use as 32-bit data registers (R2R0/R3R1). (2) Address registers (A0 and A1) Address registers (A0 and A1) are configured with 24 bits, and have functions equivalent to those of data registers. These registers can also be used for address register indirect addressing and address register relative addressing. (3) Static base register (SB) Static base register (SB) is configured with 24 bits, and is used for SB relative addressing. (4) Frame base register (FB) Frame base register (FB) is configured with 24 bits, and is used for FB relative addressing. (5) Program counter (PC) Program counter (PC) is configured with 24 bits, indicating the address of an instruction to be executed. (6) Interrupt table register (INTB) Interrupt table register (INTB) is configured with 24 bits, indicating the start address of an interrupt vector table. (7) User stack pointer (USP), interrupt stack pointer (ISP) Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each configured with 24 bits. Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag). This flag is located at the position of bit 7 in the flag register (FLG). Set USP and ISP to an even number so that execution efficiency is increased. (8) Save flag register (SVF) This register consists of 16 bits and is used to save the flag register when a high-speed interrupt is generated. Rev.1.00 Aug. 02, 2005 Page 14 REJ09B0187-0100 of 329 M16C/80 Group 3. Central Processing Unit (CPU) (9) Save PC register (SVP) This register consists of 24 bits and is used to save the program counter when a high-speed interrupt is generated. (10) Vector register (VCT) This register consists of 24 bits and is used to indicate the jump address when a high-speed interrupt is generated. (11) DMA mode registers (DMD0/DMD1) These registers consist of 8 bits and are used to set the transfer mode, etc. for DMA. (12) DMA transfer count registers (DCT0/DCT1) These registers consist of 16 bits and are used to set the number of DMA transfers performed. (13) DMA transfer count reload registers (DRC0/DRC1) These registers consist of 16 bits and are used to reload the DMA transfer count registers. (14) DMA memory address registers (DMA0/DMA1) These registers consist of 24 bits and are used to set a memory address at the source or destination of DMA transfer. (15) DMA SFR address registers (DSA0/DSA1) These registers consist of 24 bits and are used to set a fixed address at the source or destination of DMA transfer. (16) DMA memory address reload registers (DRA0/DRA1) These registers consist of 24 bits and are used to reload the DMA memory address registers. Rev.1.00 Aug. 02, 2005 Page 15 REJ09B0187-0100 of 329 M16C/80 Group 3. Central Processing Unit (CPU) (17) Flag register (FLG) Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 3.2 shows the flag register (FLG). The following explains the function of each flag: * Bit 0: Carry flag (C flag) This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. * Bit 1: Debug flag (D flag) This flag enables a single-step interrupt. When this flag is "1", a single-step interrupt is generated after instruction execution. This flag is cleared to "0" when the interrupt is acknowledged. * Bit 2: Zero flag (Z flag) This flag is set to "1" when an arithmetic operation resulted in 0; otherwise, cleared to "0". * Bit 3: Sign flag (S flag) This flag is set to "1" when an arithmetic operation resulted in a negative value; otherwise, cleared to "0". * Bit 4: Register bank select flag (B flag) This flag chooses a register bank. Register bank 0 is selected when this flag is "0" ; register bank 1 is selected when this flag is "1". * Bit 5: Overflow flag (O flag) This flag is set to "1" when an arithmetic operation resulted in overflow; otherwise, cleared to "0". * Bit 6: Interrupt enable flag (I flag) This flag enables a maskable interrupt. An interrupt is disabled when this flag is "0", and is enabled when this flag is "1". This flag is cleared to "0" when the interrupt is acknowledged. * Bit 7: Stack pointer select flag (U flag) Interrupt stack pointer (ISP) is selected when this flag is "0" ; user stack pointer (USP) is selected when this flag is "1". This flag is cleared to "0" when a hardware interrupt is acknowledged or an INT instruction of software interrupt Nos. 0 to 31 is executed. * Bits 8 to 11: Reserved area Rev.1.00 Aug. 02, 2005 Page 16 REJ09B0187-0100 of 329 M16C/80 Group 3. Central Processing Unit (CPU) * Bits 12 to 14: Processor interrupt priority level (IPL) Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt is enabled. * Bit 15: Reserved area b15 b0 IPL U I OBSZDC Flag register (FLG) Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved area Processor interrupt priority level Reserved area Figure 3.2 Flag register (FLG) Rev.1.00 Aug. 02, 2005 Page 17 REJ09B0187-0100 of 329 M16C/80 Group 4. Reset 4. Reset There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset. (See "Software Reset" for details of software resets.) This section explains on hardware resets. When the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the reset pin level "L" (0.2VCC max.) for at least 20 cycles. When the reset pin level is then returned to the "H" level while main clock is stable, the reset status is cancelled and program execution resumes from the address in the reset vector table. Figure 4.1 shows the example reset circuit. Figure 4.2 shows the reset sequence. Recommended operating voltage VCC 0V RESET VCC RESET 0V Equal to or less than 0.2VCC Equal to or less than 0.2VCC More than 20 cycles of XIN are needed. Figure 4.1 Example reset circuit XIN More than 20 cycles are needed Microprocessor mode BYTE = "H" RESET 40 to 45 BCLK cycles BCLK Content of reset vector Address FFFFFC16 FFFFFD16 FFFFFE16 FFFFFF16 RD WR CS0 Microprocessor mode BYTE = "L" Address FFFFFC16 FFFFFE16 Content of reset vector RD WR CS0 Single chip mode Address FFFFFE16 FFFFFC16 Content of reset vector Figure 4.2 Reset sequence Rev.1.00 Aug. 02, 2005 Page 18 REJ09B0187-0100 of 329 M16C/80 Group 4. Reset ____________ Table 4.1 shows the statuses of the other pins while the RESET pin level is "L". Figures 4.3 and 4.4 show the internal status of the microcomputer immediately after the reset is cancelled. ____________ Table 4.1 Pin status when RESET pin level is "L" Status Pin name P0 P1 P2, P3, P4 P50 P51 P52 P53 P54 CNVSS = VCC CNVSS = VSS BYTE = VSS Input port (floating) Input port (floating) Input port (floating) Input port (floating) Input port (floating) Input port (floating) Input port (floating) Input port (floating) Data input (floating) Data input (floating) Address output (undefined) WR output ("H" level is output) BHE output (undefined) RD output ("H" level is output) BCLK output BYTE = VCC Data input (floating) Input port (floating) Address output (undefined) WR output ("H" level is output) BHE output (undefined) RD output ("H" level is output) BCLK output HLDA output (The output value HLDA output (The output value depends on the input to the depends on the input to the HOLD pin) HOLD pin) HOLD input (floating) RAS output RDY input (floating) Input port (floating) Input port (floating) HOLD input (floating) RAS output RDY input (floating) Input port (floating) Input port (floating) P55 P56 P57 P6, P7, P80 to P84, P86, P87, P9, P10, Input port (floating) Input port (floating) Input port (floating) Input port (floating) P11, P12, P13, Input port (floating) P14, P15 (Note) Note :Port P11 to P15 exist in 144-pin vrsion. Rev.1.00 Aug. 02, 2005 Page 19 REJ09B0187-0100 of 329 M16C/80 Group 4. Reset (1) Processor mode register 0 (Note1) (2) Processor mode register 1 (3) System clock control register 0 (4) System clock control register 1 (5) Wait control register Address match interrupt (6) enable register (7) Protect register (8) External data bus width control register (Note 2) (9) Main clock divided register (10) Watchdog timer control register (11) Address match interrupt register 0 (000416)*** (000516)*** (000616)*** (000716)*** (000816)*** (000916)*** (000A16)*** (000B16)*** (000C16)*** 8016 0016 0816 2016 FF16 0000 000 ? 000 01000 (30) Timer B3 interrupt control register (31) INT5 interrupt control register (32) INT3 interrupt control register (33) INT1 interrupt control register (34) DMA1 interrupt control register (35) UART2 transmit/NACK interrupt control register (36) DMA3 interrupt control register (37) UART3 transmit/NACK interrupt control register (38) Timer A1 interrupt control register (39) UART4 receive/NACK interrupt control register (40) Timer A3 interrupt control register (41) Bus collision detection(UART2) interrupt control register (42) UART0 transmit interrupt control register Bus collision detection(UART4) (43) interrupt control register (44) UART1 transmit interrupt control register (45) Key input interrupt control register (46) Timer B0 interrupt control register (47) Timer B2 interrupt control register (48) Timer B4 interrupt control register (49) INT4 interrupt control register (50) INT2 interrupt control register (51) INT0 interrupt control register (52) Exit priority register (53) XY control register (54) UART4 special mode register 3 (55) UART4 special mode register 2 (56) UART4 special mode register (57) UART4 transmit/receive mode register (007816)*** (007A16)*** (007C16)*** (007E16)*** (008816)*** (008916)*** (008A16)*** (008B16)*** (008C16)*** (008D16)*** (008E16)*** (008F16)*** (009016)*** (009116)*** (009216)*** (009316)*** (009416)*** (009616)*** (009816)*** (009A16)*** (009C16)*** (009E16)*** (009F16)*** (02E016)*** (02F516)*** (02F616)*** (02F716)*** (02F816)*** ?000 00?000 00?000 0 0?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 00?000 00?000 00?000 0000 00 0016 0016 0016 0016 0816 0216 (000F16)*** 0 0 0 ? ? ? ? ? (001016)*** (001116)*** (001216)*** 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 ???? ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 (12) Address match interrupt register 1 (001416)*** (001516)*** (001616)*** (13) Address match interrupt register 2 (001816)*** (001916)*** (001A16)*** (14) Address match interrupt register 3 (001C16)*** (001D16)*** (001E16)*** (15) DMAM control register (16) DMA0 interrupt control register (17) Timer B5 interrupt control register (18) DMA2 interrupt control register (004016)*** ? (006816)*** (006916)*** (006A16)*** (19) UART2 receive/ACK interrupt control (006B16)*** register (20) Timer A0 interrupt control register (006C16)*** (21) UART3 receive/ACK interrupt control (006D16)*** register (22) Timer A2 interrupt control register (006E16)*** (58) UART4 transmit/receive control register 0 (02FC16)*** (59) UART4 transmit/receive control register 1 (02FD16)*** (60) Timer B3,4,5 count start flag (61) Three-phase PWM control register 0 (62) Three-phase PWM control register 1 (63) Three-phase output buffer register 0 (64) Three-phase output buffer register 1 (65) Timer B3 mode register (66) Timer B4 mode register (67) Timer B5 mode register (030016)*** 0 0 0 (030816)*** (23) UART4 receive/ACK interrupt control (006F16)*** register (24) Timer A4 interrupt control register Bus collision detection(UART3) (25) interrupt control register (26) UART0 receive interrupt control register (27) A/D conversion interrupt control register (28) UART1 receive interrupt control register (29) Timer B1 interrupt control register (007016)*** (007116)*** (007216)*** (007316)*** (007416)*** (007616)*** 0016 (030916)*** 0 0 0 0 ? 0 0 0 (030A16)*** (030B16)*** 3F16 3F16 (031B16)*** 0 0 ? ? 0 0 0 0 (031C16)*** 0 0 ? (031D16)*** 0 0 ? 0000 0000 x : Nothing is mapped to this bit ? : Undefined The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set. Note 1: When the VCC level is applied to the CNVSS pin, it is 0316 at a reset. Note 2: When the BYTE pin is "L", the third bit is "1". When the BYTE pin is "H", the third bit is "0". Figure 4.3 Device's internal status after a reset is cleared Rev.1.00 Aug. 02, 2005 Page 20 REJ09B0187-0100 of 329 M16C/80 Group 4. Reset (68) Interrupt cause select register (69) UART3 special mode register 3 (70) UART3 special mode register 2 (71) UART3 special mode register (72) UART3 transmit/receive mode register (031F16)*** (032516)*** (032616)*** (032716)*** (032816)*** 000000 0016 0016 0016 0016 0816 0216 (112) Function select register A0 (113) Function select register A1 (114) Function select register B0 (115) Function select register B1 (116) Function select register A2 (117) Function select register A3 (118) Function select register B2 (119) Function select register B3 (03B016)*** 0 (03B116)*** (03B216)*** (03B316)*** (03B416)*** (03B516)*** (03B616)*** 000 00 000000 0 0 000 0 00 0016 0 0 (73) UART3 transmit/receive control register 0 (032C16)*** (74) UART3 transmit/receive control register 1 (032D16)*** (75) UART2 special mode register 3 (76) UART2 special mode register 2 (77) UART2 special mode register (78) UART2 transmit/receive mode register (033516)*** 0 0 0 (033616)*** (033716)*** (033816)*** (03B716)*** 0 0 0 0 0 (03C216)*** (03C316)*** (03C616)*** 0 0 (03C716)*** (03CA16)*** (03CB16)*** (03CE16)*** (03CF16)*** (03D216)*** (03D316)*** (03DA16)*** (03DB16)*** (03DC16)*** (03E216)*** (03E316)*** (03E616)*** (03E716)*** (03EA16)*** (03EB16)*** (03F016)*** (03F116)*** (03FF16)*** 000016 00000016 00000016 00000016 00000016 00000016 00000016 000016 0016 ?? ?? ?? ?? ?? 0016 0016 0016 0016 0016 01000 0216 0016 (120) Port P6 direction register (121) Port P7 direction register (122) Port P8 direction register (123) Port P9 direction register (124) Port P10 direction register (125) Port P11 direction register (Note 2) (126) Port P12 direction register (Note 2) 00000 0016 0016 0000 0 0016 0016 (79) UART2 transmit/receive control register 0 (033C16)*** 0 0 (80) UART2 transmit/receive control register 1 (033D16)*** (81) Count start flag (82) Clock prescaler reset flag (83) One-shot start flag (84) Trigger select flag (85) Up-down flag (86) Timer A0 mode register (87) Timer A1 mode register (88) Timer A2 mode register (89) Timer A3 mode register (90) Timer A4 mode register (91) Timer B0 mode register (92) Timer B1 mode register (93) Timer B2 mode register (94) UART0 transmit/receive mode register (95) UART0 transmit/receive control register 0 (96) UART0 transmit/receive control register 1 (97) UART1 transmit/receive mode register (034016)*** (034116)*** 0 (034216)*** (034316)*** (034416)*** 0016 0016 0016 (127) Port P13 direction register (Note 2) (128) Port P14 direction register (Note 2) (129) Port P15 direction register (Note 2) (130) Pull-up control register 2 (131) Pull-up control register 3 (Note 2) (132) Pull-up control register 4 (Note 2) (133) Port P0 direction register (132) Port P1 direction register (135) Port P2 direction register (136) Port P3 direction register (137) Port P4 direction register (138) Port P5 direction register (139) Pull-up control register 0 (140) Pull-up control register 1 (141) Port control register (142) Data registers (R0/R1/R2/R3) (143) Address registers (A0/A1) (144) Static base register (SB) (145) Frame base register (FB) (146) Interrupt table register (INTB) (147) User stack pointer (USP) (148) Interrupt stack pointer (ISP) (149) Flag register (FLG) (150) DMA mode register (DMD0/DMD1) 0000000 0016 0016 0016 X016 0016 0016 0016 0016 0016 0016 0016 X016 0 (035616)*** 0 0 0 0 0 ? 0 0 (035716)*** 0 0 0 0 0 ? 0 0 (035816)*** 0 0 0 0 0 ? 0 0 (035916)*** 0 0 0 0 0 ? 0 0 (035A16)*** 0 0 0 0 0 ? 0 0 (035B16)*** 0 0 ? ? 0 0 0 0 (035C16)*** 0 0 ? (035D16)*** 0 0 ? (036016)*** (036416)*** (036516)*** (036816)*** 0000 0000 0016 0816 0216 0016 0816 0216 0 0000 (98) UART1 transmit/receive control register 0 (036C16)*** (99) UART1 transmit/receive control register 1 (036D16)*** (100) UART transmit/receive control register 2 (101) Flash memory control register 1 (Note 1) (102) Flash memory control register 0 (Note 1) (103) DMA0 cause select register (104) DMA1 cause select register (105) DMA2 cause select register (106) DMA3 cause select register (107) A/D control register 2 (108) A/D control register 0 (109) A/D control register 1 (110) D/A control register (111) Function select register C (037016)*** (037616)*** ? ? ? ? 0 ? ? ? (037716)*** (037816)*** 0 (037916)*** 0 (037A16)*** 0 (037B16)*** 0 000001 000000 000000 000000 000000 0 (039416)*** 0 0 0 0 (151) DMA transfer count register (DCT0/DCT1) (152) DMA transfer count reload register (DRC0/DRC1) (153) DMA memory address register (DMA0/DMA1) (154) DMA SFR address register (DSA0/DSA1) (039616)*** 0 0 0 0 0 ? ? ? (039716)*** (039C16)*** (03AF16)*** 0 0016 0016 0 (155) DMA memory address reload register (DRA0/DRA1) x : Nothing is mapped to this bit ? : Undefined The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set. Note 1:This register exists in the flash memory version. Note 2:This register exists in 144-pin version. Figure 4.4 Device's internal status after a reset is cleared Rev.1.00 Aug. 02, 2005 Page 21 REJ09B0187-0100 of 329 M16C/80 Group 5. SFR 5. SFR 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 004016 004116 004216 004316 004416 006016 006116 006216 006316 Processor mode register 0 (PM0) Processor mode register 1(PM1) System clock control register 0 (CM0) System clock control register 1 (CM1) Wait control register (WCR) Address match interrupt enable register (AIER) Protect register (PRCR) External data bus width control register (DS) Main clock division register (MCD) Watchdog timer start register (WDTS) Watchdog timer control register (WDC) Address match interrupt register 0 (RMAD0) 006416 006516 006616 006716 006816 006916 006A16 006B16 006C16 006D16 006E16 006F16 007016 007116 007216 007316 007416 DMA0 interrupt control register (DM0IC) Timer B5 interrupt control register (TB5IC) DMA2 interrupt control register (DM2IC) UART2 receive/ACK interrupt control register (S2RIC) Timer A0 interrupt control register (TA0IC) UART3 receive/ACK interrupt control register (S3RIC) Timer A2 interrupt control register (TA2IC) UART4 receive/ACK interrupt control register (S4RIC) Timer A4 interrupt control register (TA4IC) Bus collision detection(UART3) interrupt control register (BCN3IC) UART0 receive interrupt control register (S0RIC) A/D conversion interrupt control register (ADIC) UART1 receive interrupt control register (S1RIC) Address match interrupt register 1 (RMAD1) 007516 007616 007716 007816 Timer B1 interrupt control register (TB1IC) Timer B3 interrupt control register (TB3IC) INT5 interrupt control register (INT5IC) INT3 interrupt control register (INT3IC) INT1 interrupt control register (INT1IC) Address match interrupt register 2 (RMAD2) 007916 007A16 007B16 007C16 Address match interrupt register 3 (RMAD3) 007D16 007E16 007F16 008016 Emulator interrupt vector table register (EIAD) * Emulator interrupt detect register (EITD) * Emulator protect register (EPRR) * 008116 008216 008316 008416 008516 008616 008716 008816 008916 008A16 008B16 008C16 008D16 008E16 008F16 DMA1 interrupt control register (DM1IC) UART2 transmit/NACK interrupt control register (S2TIC) DMA3 interrupt control register (DM3IC) UART3 transmit/NACK interrupt control register (S3TIC) Timer A1 interrupt control register (TA1IC) UART4 transmit/NACK interrupt control register (S4TIC) Timer A3 interrupt control register (TA3IC) Bus collision detection(UART2) interrupt control register (BCN2IC) ROM areaset register (ROA) * Debug monitor area set register (DBA) * Expansion area set register 0 (EXA0) * Expansion area set register 1 (EXA1) * Expansion area set register 2 (EXA2) * Expansion area set register 3 (EXA3) * 009016 009116 009216 009316 009416 009516 009616 009716 009816 009916 009A16 009B16 009C16 009D16 009E16 009F16 UART0 transmit interrupt control register (S0TIC) Bus collision detection(UART4) interrupt control register (BCN4IC) UART1 transmit interrupt control register (S1TIC) Key input interrupt control register (KUPIC) Timer B0 interrupt control register (TB0IC) Timer B2 interrupt control register (TB2IC) Timer B4 interrupt control register (TB4IC) INT4 interrupt control register (INT4IC) INT2 interrupt control register (INT2IC) INT0 interrupt control register (INT0IC) Exit priority register (RLVL) DRAM control register (DRAMCONT) DRAM refresh interval set register (REFCNT) 00A016 00A116 00A216 00A316 00A416 * As this register is used exclusively for debugger purposes, user cannot use this. Do not access to the register. (The blank area is reserved and cannot be used by user.) Figure 5.1 Location of peripheral unit control registers (1) Rev.1.00 Aug. 02, 2005 Page 22 REJ09B0187-0100 of 329 M16C/80 Group 5. SFR 02C016 02C116 02C216 02C316 02C416 02C516 02C616 02C716 02C816 02C916 02CA16 02CB16 02CC16 02CD16 02CE16 02CF16 02D016 02D116 02D216 02D316 02D416 02D516 02D616 02D716 02D816 02D916 02DA16 02DB16 02DC16 02DD16 02DE16 02DF16 02E016 02E116 02E216 02E316 02E416 02E516 02E616 02E716 02E816 02E916 02EA16 02EB16 02EC16 02ED16 02EE16 02EF16 02F016 02F116 02F216 02F316 02F416 02F516 02F616 02F716 02F816 02F916 02FA16 02FB16 02FC16 02FD16 02FE16 02FF16 X0 register (X0R) Y0 register (Y0R) X1 register (X1R) Y1 register (Y1R) X2 register (X2R) Y2 register (Y2R) X3 register (X3R) Y3 register (Y3R) X4 register (X4R) Y4 register (Y4R) X5 register (X5R) Y5 register (Y5R) X6 register (X6R) Y6 register (Y6R) X7 register (X7R) Y7 register (Y7R) X8 register (X8R) Y8 register (Y8R) X9 register (X9R) Y9 register (Y9R) X10 register (X10R) Y10 register (Y10R) X11 register (X11R) Y11 register (Y11R) X12 register (X12R) Y12 register (Y12R) X13 register (X13R) Y13 register (Y13R) X14 register (X14R) Y14 register (Y14R) X15 register (X15R) Y15 register (Y15R) XY control register (XYC) 030016 030116 030216 030316 030416 030516 030616 030716 030816 030916 030A16 030B16 030C16 030D16 030E16 030F16 031016 031116 031216 031316 031416 031516 031616 031716 031816 031916 031A16 031B16 031C16 031D16 031E16 031F16 032016 032116 032216 032316 032416 032516 032616 032716 032816 032916 032A16 032B16 032C16 032D16 032E16 032F16 033016 033116 033216 033316 033416 Timer B3, 4, 5 count start flag (TBSR) Timer A1-1 register (TA11) Timer A2-1 register (TA21) Timer A4-1 register (TA41) Three-phase PWM control register 0(INVC0) Three-phase PWM control register 1(INVC1) Thrree-phase output buffer register 0(IDB0) Thrree-phase output buffer register 1(IDB1) Dead time timer(DTT) Timer B2 interrupt occurrence frequency set counter(ICTB2) Timer B3 register (TB3) Timer B4 register (TB4) Timer B5 register (TB5) Timer B3 mode register (TB3MR) Timer B4 mode register (TB4MR) Timer B5 mode register (TB5MR) Interrupt cause select register (IFSR) UART3 special mode register 3 (U3SMR3) UART3 special mode register 2 (U3SMR2) UART3 special mode register (U3SMR) UART3 transmit/receive mode register (U3MR) UART3 bit rate generator (U3BRG) UART3 transmit buffer register (U3TB) UART3 transmit/receive control register 0 (U3C0) UART3 transmit/receive control register 1 (U3C1) UART3 receive buffer register (U3RB) UART4 special mode register 3 (U4SMR3) UART4 special mode register 2 (U4SMR2) UART4 special mode register (U4SMR) UART4 transmit/receive mode register (U4MR) UART4 bit rate generator (U4BRG) UART4 transmit buffer register (U4TB) UART4 transmit/receive control register 0 (U4C0) UART4 transmit/receive control register 1 (U4C1) UART4 receive buffer register (U4RB) (The blank area is reserved and cannot be used by user.) 033516 033616 033716 033816 033916 033A16 033B16 033C16 033D16 033E16 033F16 UART2 special mode register 3 (U2SMR3) UART2 special mode register 2 (U2SMR2) UART2 special mode register (U2SMR) UART2 transmit/receive mode register (U2MR) UART2 bit rate generator (U2BRG) UART2 transmit buffer register (U2TB) UART2 transmit/receive control register 0 (U2C0) UART2 transmit/receive control register 1 (U2C1) UART2 receive buffer register (U2RB) Figure 5.2 Location of peripheral unit control registers (2) Rev.1.00 Aug. 02, 2005 Page 23 REJ09B0187-0100 of 329 M16C/80 Group 5. SFR 034016 034116 034216 034316 034416 034516 034616 034716 034816 034916 034A16 034B16 034C16 034D16 034E16 034F16 035016 035116 035216 035316 035416 035516 035616 035716 035816 035916 035A16 035B16 035C16 035D16 035E16 035F16 036016 036116 036216 036316 036416 036516 036616 036716 036816 036916 036A16 036B16 036C16 036D16 036E16 036F16 037016 037116 037216 037316 037416 037516 037616 037716 037816 037916 037A16 037B16 037C16 037D16 037E16 037F16 Count start flag (TABSR) Clock prescaler reset flag (CPSRF) One-shot start flag (ONSF) Trigger select register (TRGSR) Up-down flag (UDF) Timer A0 register (TA0) Timer A1 register (TA1) Timer A2 register (TA2) Timer A3 register (TA3) Timer A4 register (TA4) Timer B0 register (TB0) Timer B1 register (TB1) Timer B2 register (TB2) Timer A0 mode register (TA0MR) Timer A1 mode register (TA1MR) Timer A2 mode register (TA2MR) Timer A3 mode register (TA3MR) Timer A4 mode register (TA4MR) Timer B0 mode register (TB0MR) Timer B1 mode register (TB1MR) Timer B2 mode register (TB2MR) 038016 038116 038216 038316 038416 038516 038616 038716 038816 038916 038A16 038B16 038C16 038D16 038E16 038F16 039016 039116 039216 039316 039416 039516 039616 039716 039816 039916 039A16 039B16 039C16 039D16 039E16 039F16 A/D register 0 (AD0) A/D register 1 (AD1) A/D register 2 (AD2) A/D register 3 (AD3) A/D register 4 (AD4) A/D register 5 (AD5) A/D register 6 (AD6) A/D register 7 (AD7) A/D control register 2 (ADCON2) A/D control register 0 (ADCON0) A/D control register 1 (ADCON1) D/A register 0 (DA0) D/A register 1 (DA1) D/A control register (DACON) UART0 transmit/receive mode register (U0MR) 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 03A916 03AA16 03AB16 03AC16 03AD16 03AE16 03AF16 03B016 03B116 03B216 03B316 03B416 03B516 UART0 bit rate generator (U0BRG) UART0 transmit buffer register (U0TB) UART0 transmit/receive control register 0 (U0C0) UART0 transmit/receive control register 1 (U0C1) UART0 receive buffer register (U0RB) UART1 transmit/receive mode register (U1MR) UART1 bit rate generator (U1BRG) UART1 transmit buffer register (U1TB) UART1 transmit/receive control register 0 (U1C0) UART1 transmit/receive control register 1 (U1C1) UART1 receive buffer register (U1RB) UART transmit/receive control register 2 (UCON) Flash memory control register 1 (FMR1) (Note) Flash memory control register 0 (FMR0) (Note) DMA0 request cause select register (DM0SL) DMA1 request cause select register (DM1SL) DMA2 request cause select register (DM2SL) DMA3 request cause select register (DM3SL) CRC data register (CRCD) CRC input register (CRCIN) Note :This register exists in the flash memory version. 03B616 03B716 03B816 03B916 03BA16 03BB16 03BC16 03BD16 03BE16 03BF16 Function select register C(PSC) Function select register A0 (PS0) Function select register A1 (PS1) Function select register B0 (PSL0) Function select register B1 (PSL1) Function select register A2 (PS2) Function select register A3 (PS3) Function select register B2 (PSL2) Function select register B3 (PSL3) (The blank area is reserved and cannot be used by user.) Figure 5.3 Location of peripheral unit control registers (3) Rev.1.00 Aug. 02, 2005 Page 24 REJ09B0187-0100 of 329 M16C/80 Group 5. SFR <100-pin version> 03C016 03C116 03C216 03C316 03C416 03C516 03C616 03C716 03C816 03C916 03CA16 03CB16 03CC16 03CD16 03CE16 03CF16 03D016 03D116 03D216 03D316 03D416 03D516 03D616 03D716 03D816 03D916 03DA16 03DB16 03DC16 03DD16 03DE16 03DF16 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA16 03EB16 03EC16 03ED16 03EE16 03EF16 03F016 03F116 03F216 03F316 03FC16 03FD16 03FE16 03FF16 <144-pin version> 03C016 03C116 03C216 03C316 03C416 03C516 03C616 03C716 03C816 03C916 03CA16 03CB16 03CC16 03CD16 03CE16 03CF16 03D016 03D116 03D216 03D316 03D416 03D516 03D616 03D716 03D816 03D916 Port P6 (P6) Port P7 (P7) Port P6 direction register (PD6) Port P7 direction register (PD7) Port P8 (P8) Port P9 (P9) Port P8 direction register (PD8) Port P9 direction register (PD9) Port P10 (P10) Port P10 direction register (PD10) Port P6 (P6) Port P7 (P7) Port P6 direction register (PD6) Port P7 direction register (PD7) Port P8 (P8) Port P9 (P9) Port P8 direction register (PD8) Port P9 direction register (PD9) Port P10 (P10) Port P11 (P11) Port P10 direction register (PD10) Port P11 direction register (PD11) Port P12 (P12) Port P13 (P13) Port P12 direction register (PD12) Port P13 direction register (PD13) Port P14 (P14) Port P15 (P15) Port P14 direction register (PD14) Port P15 direction register (PD15) Pull-up control register 2 (PUR2) Pull-up control register 3 (PUR3) 03DA16 03DB16 03DC16 03DD16 03DE16 03DF16 Pull-up control register 2 (PUR2) Pull-up control register 3 (PUR3) Pull-up control register 4 (PUR4) Port P0 (P0) Port P1 (P1) Port P0 direction register (PD0) Port P1 direction register (PD1) Port P2 (P2) Port P3 (P3) Port P2 direction register (PD2) Port P3 direction register (PD3) Port P4 (P4) Port P5 (P5) Port P4 direction register (PD4) Port P5 direction register (PD5) 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA16 03EB16 03EC16 03ED16 03EE16 03EF16 Port P0 (P0) Port P1 (P1) Port P0 direction register (PD0) Port P1 direction register (PD1) Port P2 (P2) Port P3 (P3) Port P2 direction register (PD2) Port P3 direction register (PD3) Port P4 (P4) Port P5 (P5) Port P4 direction register (PD4) Port P5 direction register (PD5) Pull-up control register 0 (PUR0) Pull-up control register 1 (PUR1) 03F016 03F116 03F216 03F316 03FC16 03FD16 03FE16 Pull-up control register 0 (PUR0) Pull-up control register 1 (PUR1) Port control register (PCR) (The blank area is reserved and cannot be used by user.) Note 1: 03FF16 Port control register (PCR) Addresses 03C916, 03CB16 to 03D316 area is for future plan. Must set "FF16" to address 03CB16, 03CE16, 03CF16, 03D216, 03D316 at initial setting. Note 2: Address 03DC16 area is for future plan. Must set "0016" to address 03DC16 at initial setting. Figure 5.4 Location of peripheral unit control registers (4) Rev.1.00 Aug. 02, 2005 Page 25 REJ09B0187-0100 of 329 M16C/80 Group 6. Processor Mode Software Reset Writing "1" to bit 3 of the processor mode register 0 (address 000416) applies a (software) reset to the microcomputer. A software reset has the same effect as a hardware reset. The contents of internal RAM are preserved. Carry out a software reset after oscillation of main clock is fully stable. 6. Processor Mode (1) Types of Processor Mode One of three processor modes can be selected: single-chip mode, memory expansion mode, and microprocessor mode. The functions of some pins, the memory map, and the access space differ according to the selected processor mode. * Single-chip mode In single-chip mode, only internal memory space (SFR, internal RAM, and internal ROM) can be accessed. However, after the reset has been released and the operation of shifting from the microprocessor mode has started ("H" applied to the CNVSS pin), the internal ROM area cannot be accessed even if the CPU shifts to the single-chip mode. Ports P0 to P10 can be used as programmable I/O ports or as I/O ports for the internal peripheral functions. * Memory expansion mode In memory expansion mode, external memory can be accessed in addition to the internal memory space (SFR, internal RAM, and internal ROM). However, after the reset has been released and the operation of shifting from the microprocessor mode has started ("H" applied to the CNVSS pin), the internal ROM area cannot be accessed even if the CPU shifts to the memory expansion mode. In this mode, some of the pins function as the address bus, the data bus, and as control signals. The number of pins assigned to these functions depends on the bus and register settings. (See "Bus Settings" for details.) * Microprocessor mode In microprocessor mode, the SFR, internal RAM, and external memory space can be accessed. The internal ROM area cannot be accessed. In this mode, some of the pins function as the address bus, the data bus, and as control signals. The number of pins assigned to these functions depends on the bus and register settings. (See "Bus Settings" for details.) (2) Setting Processor Modes The processor mode is set using the CNVSS pin and the processor mode bits (bits 1 and 0 at address 000416). Do not set the processor mode bits to "102". Regardless of the level of the CNVSS pin, changing the processor mode bits selects the mode. Therefore, never change the processor mode bits when changing the contents of other bits. Do not change the processor mode bits simultaneously with other bits when changing the processor mode bits "012" or "112". Change the processor mode bits after changeing the other bits. Also do not attempt to shift to or from the microprocessor mode within the program stored in the internal ROM area. * Applying VSS to CNVSS pin The microcomputer begins operation in single-chip mode after being reset. Memory expansion mode is selected by writing "012" to the processor mode is selected bits. * Applying VCC to CNVSS pin The microcomputer starts to operate in microprocessor mode after being reset. Figures 6.1 and 6.2 show the processor mode register 0 and 1. Figure 6.3 shows the memory maps applicable for each processor modes. Rev.1.00 Aug. 02, 2005 Page 26 REJ09B0187-0100 of 329 M16C/80 Group 6. Processor Mode Processor mode register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol PM0 Bit symbol PM00 PM01 PM02 PM03 PM04 PM05 Address 000416 Bit name Processor mode bit (Note 8) When reset 8016 (Note 2) Function b1 b0 RW 0 0: Single-chip mode 0 1: Memory expansion mode 1 0: Must not be set 1 1: Microprocessor mode 0 : RD,BHE,WR 1 : RD,WRH,WRL The device is reset when this bit is set to "1". The value of this bit is "0" when read. b5 b4 R/W mode select bit (Note 7) Software reset bit Multiplexed bus space select bit (Note 3) 0 0 : Multiplexed bus is not used 0 1 : Allocated to CS2 space 1 0 : Allocated to CS1 space 1 1 : Allocated to entire space (Note4) Reserved bit PM07 Must always be set to "0" BCLK output disable bit (Note 5) 0 : BCLK is output (Note 6) 1 : Function set by bit 0,1 of system clock control register 0 Note 1: Set bit 1 of the protect register (address 000A16) to "1" when writing new values to this register. Note 2: If the VCC voltage is applied to the CNVSS, the value of this register when reset is 0316. (PM00 is set to "1" and PM07 is set to "0".) Note 3: Valid in microprocessor and memory expansion modes 1, 2 and 3. Do not use multiplex bus when mode 0 is selected. Do not set to allocated to CS2 space when mode 2 is selected. Note 4: After the reset has been released, the M16C/80 group MCU operates using the separate bus. As a result, in microprocessor mode, you cannot select the full CS space multiplex bus. When you select the full CS space multiplex bus in memory expansion mode, the address bus operates with 64 Kbytes boundaries for each chip select. Mode 0: Multiplexed bus cannot be used. Mode 1: CS0 to CS2 when you select full CS space. Mode 2: CS0 to CS1 when you select full CS space. Mode 3: CS0 to CS3 when you select full CS space. Note 5: No BCLK is output in single chip mode even when "0" is set in PM07. When stopping clock output in microprocessor or memory expansion mode, make the following settings: PM07="1", bit 0 (CM00) and bit 1 (CM01) of system clock control register 0 (address 000616) = "0". "L" is now output from P53. Note 6: When selecting BCLK, set bits 0 and 1 of system clock control register 0 (CM00, CM01) to "0". Note 7: When using 16-bit bus width in DRAM controller, set this bit to "1". Note 8: Do not set the processor mode bits and other bits simultaneously when setting the processor mode bits to "012" or "112". Set the other bits first, and then change the processor mode bits. Figure 6.1 Processor mode register 0 Rev.1.00 Aug. 02, 2005 Page 27 REJ09B0187-0100 of 329 M16C/80 Group 6. Processor Mode Processor mode register 1 (Note 1) :Mask ROM version ROMless version (144-pin version) b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol PM1 Address 000516 When reset 0016 Bit symbol PM10 Bit name External memory area mode bit (Note 3) b1 b0 Function 0 0 : Mode 0 (P44 to P47 : A20 to A23) 0 1 : Mode 1 (P44 : A20, P45 to P47 : CS2 to CS0) 1 0 : Mode 2 (P44, P45 : A20, A21, P46, P47 : CS1, CS0) 1 1 : Mode 3 (Note 2) (P44 to P47 : CS3 to CS0) 0 : No wait state 1 : Wait state inserted Must always be set to "0" RW PM11 PM12 Internal memory wait bit Reserved bit PM14 ALE pin select bit (Note 3) b5 b4 PM15 0 0 : No ALE 0 1 : P53/BCLK (Note 4) 1 0 : P56/RAS 1 1 : P54/HLDA Nothing is assinged. When read, the content is indeterminate. Note 1: Set bit 1 of the protect register (address 000A16) to "1" when writing new values to this register. Note 2: When mode 3 is selected, DRAMC is not used. Note 3: Valid in memory expansion mode or in microprocessor mode. Note 4: When selecting P53/BCLK, set bits 0 and 1 of system clock control register 0 (CM00, CM01) to "0". Processor mode register 1 (Note 1) :Flash memory version b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol PM1 Address 000516 When reset 0016 Bit symbol PM10 Bit name External memory area mode bit (Note 3) b1 b0 Function 0 0 : Mode 0 (P44 to P47 : A20 to A23) 0 1 : Mode 1 (P44 : A20, P45 to P47 : CS2 to CS0) 1 0 : Mode 2 (P44, P45 : A20, A21, P46, P47 : CS1, CS0) 1 1 : Mode 3 (Note 2) (P44 to P47 : CS3 to CS0) 0 : No wait state 1 : Wait state inserted Must always be set to "0" RW PM11 PM12 Internal memory wait bit Reserved bit PM14 ALE pin select bit (Note 3) b5 b4 PM15 0 0 : No ALE 0 1 : P53/BCLK (Note 4) 1 0 : P56/RAS 1 1 : P54/HLDA Must always be set to "1" (Note 5) Reserved bit Note 1: Set bit 1 of the protect register (address 000A16) to "1" when writing new values to this register. Note 2: When mode 3 is selected, DRAMC is not used. Note 3: Valid in memory expansion mode or in microprocessor mode. Note 4: When selecting P53/BCLK, set bits 0 and 1 of system clock control register 0 (CM00, CM01) to "0". Note 5: Rewrite this bit when the main clock is in division by 8 mode. Figure 6.2 Processor mode register 1 Rev.1.00 Aug. 02, 2005 Page 28 REJ09B0187-0100 of 329 Memory expanded mode Microprocessor mode Mode 2 Mode 3 Mode 1 SFR area Internal RAM area Internal reserved area SFR area Internal RAM area Internal reserved area SFR area Internal RAM area Internal reserved area SFR area Internal RAM area Internal reserved area SFR area Internal RAM area Internal reserved area Single chip mode Mode 1 Mode 0 Mode 2 SFR area Internal RAM area Internal reserved area SFR area Internal RAM area Internal reserved area Mode 0 Mode 3 00000016 M16C/80 Group 00040016 SFR area Internal RAM area SFR area Internal RAM area Internal reserved area 00080016 No use External area 0 CS1 2Mbytes (Note1) External area 0 CS1 4Mbytes (Note2) External area 0 No use CS1, 1Mbytes External area 0 CS2, 1Mbytes External area 1 No use Rev.1.00 Aug. 02, 2005 Page 29 REJ09B0187-0100 External area 0 CS1, 1Mbytes External area 0 CS2, 1Mbytes External area 1 External area 1 No use CS2 2Mbytes External area 1 CS1 2Mbytes (Note1) External area 0 CS2 2Mbytes External area 1 CS1 4Mbytes (Note2) External area 0 20000016 External area 1 Figure 6.3 Memory maps in each processor mode No use (Cannot use as DRAM area or external area.) No use (Cannot use as DRAM area or external area.) Connect with DRAM 0, 0.5 to 8MB (When open area is under 8MB, cannot use the rest of this area.) Connect with DRAM 0, 0.5 to 8MB (When open area is under 8MB, cannot use the rest of this area.) Connect with DRAM 0, 0.5 to 8MB (When not connect with DRAM, use as external area.) Connect with DRAM 0, 0.5 to 8MB (When open area is under 8MB, cannot use the rest of this area.) Connect with DRAM 0, 0.5 to 8MB (When open area is under 8MB, cannot use the rest of this area.) of 329 40000016 No use Connect with DRAM 0, 0.5 to 8MB (When not connect with DRAM, use as external area.) (External area 2) (External area 2) (External area 2) CS3, 1Mbytes External area 2 No use CS0 3Mbytes External area 3 Internal reserved area Internal ROM area (External area 2) (External area 2) (External area 2) CS3, 1Mbytes External area 2 No use External area 3 CS0 2Mbytes External area 3 No use C0000016 External area 3 No use Internal reserved area Internal ROM area CS0 2Mbytes External area 3 CS0, 1Mbytes External area 3 Internal reserved area Internal ROM area E0000016 CS0 4Mbytes External area 3 F0000016 FFFFFF16 Internal ROM area Internal reserved area Internal ROM area CS0, 1Mbytes External area 3 Note 1: 20000016-00800016=2016 Kbytes. 32 K less than 2 MB. Note 2: 40000016-00800016=4064 Kbytes. 32 K less than 4 MB. 6. Processor Mode Each CS0 to CS3 can set 0 to 3 WAIT. M16C/80 Group 7. Bus 7. Bus 7.1 Bus Settings The BYTE pin, bit 0 to 3 of the external data bus width control register (address 000B16), bits 4 and 5 of the processor mode register 0 (address 000416) and bit 0 and 1 of the processor mode register 1 (address 000516) are used to change the bus settings. Table 7.1 shows the factors used to change the bus settings, Figure 7.1 shows external data bus width control register and Table 7.2 shows external area 0 to 3 and external area mode. Table 7.1 Factors for switching bus settings Bus setting Switching external address bus width Switching external data bus width Switching between separate and multiplex bus Switching factor External data bus width control register BYTE pin (external area 3 only) Bits 4 and 5 of processor mode register 0 (1) Selecting external address bus width You can select the width of the address bus output externally from the 16 Mbytes address space, the number of chip select signals, and the address area of the chip select signals. (Note, however, that when ____ you select "Full CS space multiplex bus", addresses A0 to A15 are output.) The combination of bits 0 and 1 of the processor mode register 1 allow you to set the external area mode. When using DRAM controller, the DRAM area is output by multiplexing of the time splitting of the row and column addresses. (2) Selecting external data bus width You can select 8-bit or 16-bit for the width of the external data bus for external areas 0, 1, 2, and 3. When the data bus width bit of the external data bus width control register is "0", the data bus width is 8 bits; when "1", it is 16 bits. The width can be set for each of the external areas. The default bus width for external area 3 is 16 bits when the BYTE pin is "L" after a reset, or 8 bits when the BYTE pin is "H" after a reset. The bus width selection is valid only for the external bus (the internal bus width is always 16 bits). During operation, fix the level of the BYTE pin to "H" or "L". (3) Selecting separate/multiplex bus The bus format can be set to multiplex or separate bus using bits 4 and 5 of the processor mode register 0. * Separate bus In this bus configuration, input and output is performed on separate data and address buses. The data bus width can be set to 8 bits or 16 bits using the external data bus width control register. For all programmable external areas, P0 is the data bus when the external data bus is set to 8 bits, and P1 is a programmable IO port. When the external data bus width is set to 16 bits for any of the external areas, P0 and P1 (although P1 is undefined for any 8-bit bus areas) are the data bus. When accessing memory using the separate bus configuration, you can select a software wait using the wait control register. * Multiplex bus In this bus configuration, data and addresses are input and output on a time-sharing basis. For areas for which 8-bit has been selected using the external data bus width control register, the 8 bits D0 to D7 are multiplexed with the 8 bits A0 to A7. For areas for which 16-bit has been selected using the external data bus width control register, the 16 bits D0 to D15 are multiplexed with the 16 bits A0 to A15. When accessing memory using the multiplex bus configuration, two waits are inserted regardless of whether you select "No wait" or "1 wait' in the appropriate bit of the wait control register. Rev.1.00 Aug. 02, 2005 Page 30 REJ09B0187-0100 of 329 M16C/80 Group 7. Bus ____ The default after a reset is the separate bus configuration, and the full CS space multiplex bus configu____ ration cannot be selected in microprocessor mode. If you select "Full CS space multiplex bus", the 16 bits from A0 to A15 are output for the address. External data bus width control register b7 b6 b5 b4 b3 b2 b1 b0 Symbol DS Address 000B16 When reset XXXXX0002 Bit symbol DS0 DS1 DS2 DS3 Bit name External area 0 data bus width bit External area 1 data bus width bit External area 2 data bus width bit External area 3 data bus width bit (Note) Function 0 : 8 bits data bus width 1 : 16 bits data bus width 0 : 8 bits data bus width 1 : 16 bits data bus width 0 : 8 bits data bus width 1 : 16 bits data bus width 0 : 8 bits data bus width 1 : 16 bits data bus width RW Nothing is assigned. When write, set "0". When read, their contents are indeterminate. Note: The value after a reset is determined by the input via the BYTE pin. Figure 7.1 External data bus width control register Table 7.2 External area 0 to 3 and external area mode External area mode (Note 2) Mode 0 Mode 1 Mode 2 Mode 3 External area 0 Memory expansion mode, Microprocessor mode 00800016 to 1FFFFF16 External area 1 Memory expansion mode, Microprocessor mode 20000016 to 3FFFFF16 No area is selected. External area 2 Memory expansion mode, Microprocessor mode 40000016 to BFFFFF16 (Note 1) External area 3 Memory expansion mode C0000016 to EFFFFF16 C0000016 to FFFFFF16 Microprocessor mode Note 1: DRAMC area when using DRAMC. Note 2: Set the external area mode (modes 0, 1, 2, and 3) using bits 0 and 1 of the processor mode register 1 (address 000516). Rev.1.00 Aug. 02, 2005 Page 31 REJ09B0187-0100 of 329 M16C/80 Group 7. Bus Table 7.3 Each processor mode and port function Processor mode Multiplexed bus space select bit Single-chip mode Memory expansion mode/microprocessor modes "01", "10" CS1 or CS2 : multiplexed bus, and the other : separate bus All external area is 8 bits I/O port I/O port I/O port Data bus I/O port Address bus /data bus (Note 2) Memory expansion mode "11" (Note 1) All space multiplexed bus All external area is 8 bits I/O port I/O port Address bus /data bus Address bus Some external area is 16 bits I/O port I/O port Address bus /data bus Address bus /data bus I/O port "00" Separate bus Data bus width BYTE pin level Some external area is 16 bits Data bus Data bus Address bus /data bus (Note 2) All external area is 8 bits Data bus I/O port Address bus Some external area is 16 bits Data bus Data bus Address bus P00 to P07 P10 to P17 P20 to P27 P30 to P37 I/O port Address bus Address bus /data bus (Note 2) Address bus Address bus P40 to P43 P44 to P46 P47 P50 to P53 P54 P55 P56 P57 I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port Address bus Address bus Address bus Address bus I/O port CS (chip select) or address bus (A20 to A22) (For details, refer to "Bus control") (Note 5) CS (chip select) or address bus (A23) (For details, refer to "Bus control") (Note 5) Outputs RD, WRL, WRH and BCLK, or RD, BHE, WR and BCLK (For details, refer to "Bus control") (Note 3,4) HLDA(Note 3) HOLD RAS (Note 3) RDY HLDA(Note 3) HLDA(Note 3) HLDA(Note 3) HOLD RAS (Note 3) RDY HOLD RAS (Note 3) RDY HOLD RAS (Note 3) RDY HLDA(Note 3) HLDA(Note 3) HOLD RAS (Note 3) RDY HOLD RAS (Note 3) RDY Note 1:The default after a reset is the separate bus configuration, and "Full CS space multiplex bus" cannot be selected in microprocessor mode. When you select "Full CS space multiplex bus" in extended memory mode, the address bus operates with 64 Kbytes boundaries for each chip select. Note 2: Address bus in separate bus configuration. Note 3: The ALE output pin is selected using bits 4 and 5 of the processor mode register 1. Note 4: When you have selected use of the DRAM controller and you access the DRAM area, these are CASL, CASH, DW, and BCLK outputs. Note 5: The CS signal and address bus selection are set by the external area mode. Rev.1.00 Aug. 02, 2005 Page 32 REJ09B0187-0100 of 329 M16C/80 Group 7. Bus 7.2 Bus Control The following explains the signals required for accessing external devices and software waits. The signals required for accessing the external devices are valid when the processor mode is set to memory expansion mode and microprocessor mode. (1) Address bus/data bus ____ ____ There are 24 pins, A0 to A22 and A23 for the address bus for accessing the 16 Mbytes address space. A23 is an inverted output of the MSB of the address. The data bus consists of pins for data IO. The external data bus control register (address 000B16) selects the 8-bit data bus, D0 to D7 for each external area, or the 16-bit data bus, D0 to D15. After a reset, there is by default an 8-bit data bus for the external area 3 when the BYTE pin is "H", or a 16-bit data bus when the BYTE pin is "L". When shifting from single-chip mode to extended memory mode, the value on the address bus is undefined until an external area is accessed. When accessing a DRAM area with DRAM control in use, a multiplexed signal consisting of row address and column address is output to A8 to A20. (2) Chip select signals ____ The chip select signals share A0 to A22 and A23. You can use bits 0 and 1 of the processor mode register 1 (address 000516) to set the external area mode, then select the chip select area and number of address outputs. In microprocessor mode, external area mode 0 is selected after a reset. The external area can be split into a maximum of four using the chip select signals. Table 7.4 shows the external areas specified by the chip select signals. Table 7.4 External areas specified by the chip select signals Memory space expansion mode Mode 0 (A23) (A22) (A21) (A20) Processor mode CS0 Chip select signal CS1 CS2 CS3 Specified address range Memory expansion mode Mode 1 C0000016 to DFFFFF16 (2 Mbytes) E0000016 to FFFFFF16 (2 Mbytes) C0000016 to EFFFFF16 (3 Mbytes) C0000016 to FFFFFF16 (4 Mbytes) E0000016 to EFFFFF16 (1 Mbytes) F0000016 to FFFFFF16 (1 Mbytes) 00800016 to 1FFFFF16 (2016 Kbytes) 20000016 to 3FFFFF16 (2 Mbytes) (A20) Microprocessor mode Memory expansion mode Mode 2 00800016 to 3FFFFF16 (4064 Kbytes) (A21) (A20) Microprocessor mode Memory expansion mode Mode 3 Microprocessor mode 10000016 to 1FFFFF16 (1 Mbytes) 20000016 to 2FFFFF16 (1 Mbytes) C0000016 to CFFFFF16 (1 Mbytes) Rev.1.00 Aug. 02, 2005 Page 33 REJ09B0187-0100 of 329 M16C/80 Group 7. Bus The chip select signal turns "L" (active) in synchronize with the address bus. However, its turning "H" depends on the area accessed in the next cycle. Figure 7.2 shows the output examples of the address bus and chip select signals. (Example 1) After accessing the external area, the address bus and chip select signal both are changed in the next cycle. The following example shows the other chip select signal accessing area (j) in the cycle after having accessed external area (i). In this case, the address bus and chip select signal both change between the two cycles. Access to Access to external external area (j) area (i) (Example 2) After accessing the external area, only the chip select signal is changed in the next cycle. (The address bus does not change.) The following example shows the CPU accesses the internal ROM/RAM area in the cycle after having accessed external area. In this case, the chip select signal changes between the two cycles but the address bus does not. Data bus Address bus Data Data Data bus Address bus Chip select Data Address Chip select (CSi) Chip select (CSj) Address (Example 3) After accessing the external area, only the address bus is changed in the next cycle. (The chip select signal does not change.) The following example shows the same chip select signal accessing area (i) in the cycle after having accessed external area (i). In this case, the address bus changes between the two cycles, but the chip select signal does not. (Example 4) After accessing the external area, the address bus and chip select signal both are not changed in the next cycle. The following example shows CPU does not access any area in the cycle after having accessed external area (no instruction pre-fetch is occurred). In this case, the address bus and the chip select signal do not change between the two cycles. Access to Access to external external area (i) area (i) Access to external No access area Data bus Address bus Chip select (CSi) Data Data Data bus Address bus Chip select Data Address Address Note: These examples show the address bus and chip select signal for two consecutive cycles. By combining these examples, chip select signal can be extended beyond two cycles. Figure 7.2 Example of address bus and chip select signal outputs (Separate bus) Rev.1.00 Aug. 02, 2005 Page 34 REJ09B0187-0100 of 329 M16C/80 Group 7. Bus (3) Read/write signals With a 16-bit data bus, bit 2 of the processor mode register 0 (address 000416) select the combinations of _____ ________ ______ _____ ________ _________ RD, BHE, and WR signals or RD, WRL, and WRH signals. With a 8-bit full space data bus, use the _____ ______ ________ combination of RD, WR, and BHE signals as read/write signals. (Set "0" to bit 2 of the processor mode register 0 (address 000416).) When using both 8-bit and 16-bit data bus widths and you access an 8-bit _____ ______ ________ data bus area, the RD, WR and BHE signals combination is selected regardless of the value of bit 2 of the processor mode register 0 (address 000416). Tables 7.5 and 7.6 show the operation of these signals. _____ ______ ________ After a reset has been cancelled, the combination of RD, WR, and BHE signals is automatically selected. _____ _________ _________ When switching to the RD, WRL, and WRH combination, do not write to external memory until bit 2 of the processor mode register 0 (address 000416) has been set (Note). Note 1: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect register (address 000A16) to "1". _____ ________ _________ Note 2: When using 16-bit data bus width for DRAM controller, select RD, WRL, and WRH signals. _____ ________ _________ Table 7.5 Operation of RD, WRL, and WRH signals Data bus width RD WRL WRH L H H H L H 16-bit H H L H L L L (Note) H Not used 8-bit H (Note) L Not used ______ Note: It becomes WR signal. _____ ______ ________ Status of external data bus Read data Write 1 byte of data to even address Write 1 byte of data to odd address Write data to both even and odd addresses Write 1 byte of data Read 1 byte of data Table 7.6 Operation of RD, WR, and BHE signals Data bus width RD H L H L H L H L WR L H L H L H L H BHE L L H H L L Not used Not used A0 H H L L L L H/L H/L Status of external data bus Write 1 byte of data to odd address Read 1 byte of data from odd address Write 1 byte of data to even address Read 1 byte of data from even address Write data to both even and odd addresses Read data from both even and odd addresses Write 1 byte of data Read 1 byte of data 16-bit 8-bit Rev.1.00 Aug. 02, 2005 Page 35 REJ09B0187-0100 of 329 M16C/80 Group 7. Bus (4) ALE signal The ALE signal latches the address when accessing the multiplex bus space. Latch the address when the ALE signal falls. The ALE output pin is selected using bits 4 and 5 of the processor mode register 1 (address 000516). The ALE signal is occurred regardless of internal area and external area. When BYTE pin = "H" ALE D0/A0 to D7/A7 A8 to A15 Address Data (Note 1) ALE When BYTE pin = "L" D0/A0 to D15/A15 Address Data (Note 1) Address A16 to A19 Address (Note 2) A16 to A19 Address (Note 2) A20 to A22, A23 Address or CS A20 to A22, A23 Address or CS Note 1: Floating when reading. Note 2: When full space multiplexed bus is selected, these are I/O ports. Figure 7.3 ALE signal and address/data bus (5) Ready signal The ready signal facilitates access of external devices that require a long time for access. As shown in ________ Figure 7.2, inputting "L" to the RDY pin at the falling edge of BCLK causes the microcomputer to enter the ________ ready state. Inputting "H" to the RDY pin at the falling edge of BCLK cancels the ready state. Table 7.7 _____ shows the microcomputer status in the ready state. Figure 7.4 shows the example of the RD signal being ________ extended using the RDY signal. Ready is valid when accessing the external area during the bus cycle in which the software wait is ap________ plied. When no software wait is operating, the RDY signal is ignored, but even in this case, unused pins must be pulled up. Table 7.7 Microcomputer status in ready state (Note) Item Oscillation On _____ _____ _____ Status RD/WR signal, address bus, data bus, CS __________ ALE signal, HLDA, programmable I/O ports Internal peripheral circuits Maintain status when ready signal received On Note: The ready signal cannot be received immediately prior to a software wait. Rev.1.00 Aug. 02, 2005 Page 36 REJ09B0187-0100 of 329 M16C/80 Group 7. Bus Separate bus (2 wait) 1st cycle 2nd cycle 3rd cycle 4th cycle BCLK RD (Note) CSi (i=0 to 3) RDY tsu(RDY - BCLK) RDY received timing Multiplexed bus (2 wait) 1st cycle 2nd cycle 3rd cycle 4th cycle BCLK RD (Note) CSi (i=0 to 3) RDY tsu(RDY - BCLK) : Wait using RDY signal : Wait using software RDY received timing RDY signal received timing for i wait(s): i + 1 cycles (i = 1 to 3) Note: Chip select may get longer by a state of CPU such as an instruction queue buffer. _____ ________ Figure 7.4 Example of RD signal extended by RDY signal Rev.1.00 Aug. 02, 2005 Page 37 REJ09B0187-0100 of 329 M16C/80 Group 7. Bus (6) Hold signal The hold signal is used to transfer the bus privileges from the CPU to the external circuits. Inputting "L" to __________ the HOLD pin places the microcomputer in the hold state at the end of the current bus access. This status __________ __________ is maintained and "L" is output from the HLDA pin as long as "L" is input to the HOLD pin. Table 7.8 shows the microcomputer status in the hold state. The bus is used in the following descending order of priority: __________ HOLD, DMAC, CPU. __________ HOLD > DMAC > CPU _____ ________ Figure 7.5 Example of RD signal extended by RDY signal Table 7.8 Microcomputer status in hold state Item Oscillation _____ _____ _____ _______ Status ON Floating Maintains status when hold signal is received RD/WR signal, address bus, data bus, CS, BHE Programmable I/O ports P0, P1, P2, P3, P4, P5 P6, P7, P8, P9, P10 P11, P12, P13, P14, P15 (Note) __________ HLDA Internal peripheral circuits ALE signal Note: Ports P11 to P15 exist in 144-pin version. Output "L" ON (but watchdog timer stops) Undefined (7) External bus status when accessing to internal area Table 7.9 shows external bus status when accessing to internal area Table 7.9 External bus status when accessing to internal area Item Address bus Data bus When read When write _____ ______ ________ _________ SFR accessing status Internal ROM/RAM accessing status Remain address of external area accessed immediately before Floating Floating Output "H" Remain external area status accessed immediately before Output "H" ALE output RD, WR, WRL, WRH ________ BHE ____ CS ALE (8) BCLK output BCLK output can be selected by bit 7 of the processor mode register 0 (address 000416 :PM07) and bit 1 and bit 0 of the system clock select register 0 (address 000616 :CM01, CM00). Setting PM07 to "0" and CM01 and CM00 to "00" outputs the BCLK signal from P53. However, in single chip mode, BCLK signal is not output. When setting PM07 to "1", the function is as set by CM01 and CM00. Rev.1.00 Aug. 02, 2005 Page 38 REJ09B0187-0100 of 329 M16C/80 Group 7. Bus _______ __________ __________ _____ (9) DRAM controller signals (RAS, CASL, CASH, and DW) Bits 1, 2, and 3 of the DRAM control register (address 000416) select the DRAM space and enable the DRAM controller. The DRAM controller signals are then output when the DRAM area is accessed. Table 7.10 shows the operation of the respective signals. _______ __________ __________ _____ Table 7.10 Operation of RAS, CASL, CASH, and DW signals Data bus width RAS L L L L L L L L CASL L L H L L H L L CASH L L H L H L Not used Not used DW H H H L L L H L Status of external data bus Read data from both even and odd addresses Read 1 byte of data from even address Read 1 byte of data from odd address Write data to both even and odd addresses Write 1 byte of data to even address Write 1 byte of data to odd address Read 1 byte of data Write 1 byte of data 16-bit 8-bit (10) Software wait A software wait can be inserted by setting the wait control register (address 000816). Figure 7.6 shows wait control register You can use the external area I wait bits (where I = 0 to 3) of the wait control register to specify from "No wait" to "3 waits" for the external memory area. When you select "No wait", the read cycle is executed in the BCLK1 cycle. The write cycle is executed in the BCLK2 cycle (which has 1 wait). When accessing external memory using the multiplex bus, access has two waits regardless of whether you specify "No wait" or "1 wait" in the appropriate external area i wait bits in the wait control register. Software waits in the internal memory (internal RAM and internal ROM) can be set using the internal memory wait bits of the processor mode register 1 (address 000516). Setting the internal memory wait bit = "0" sets "No wait". Setting the internal memory wait bit = "1" specifies a wait. The SFR area is not affected by the setting of the internal memory wait bit and is always accessed in the BCLK2 cycle. Table 7.11 shows the software waits and bus cycles. Figures 7.7 and 7.8 show example bus timings when using software waits. Rev.1.00 Aug. 02, 2005 Page 39 REJ09B0187-0100 of 329 M16C/80 Group 7. Bus Wait control register b7 b6 b5 b4 b3 b2 b1 b0 Symbol WCR Address 000816 When reset FF16 Bit symbol WCR0 WCR1 WCR2 WCR WCR4 WCR5 WCR6 WCR7 Bit name External area 0 wait bit b1 b0 Function 0 0: Without wait 0 1: With 1 wait 1 0: With 2 wait 1 1: With 3 wait b3 b2 RW External area 1 wait bit 0 0: Without wait 0 1: With 1 wait 1 0: With 2 wait 1 1: With 3 wait b5 b4 External area 2 wait bit 0 0: Without wait 0 1: With 1 wait 1 0: With 2 wait 1 1: With 3 wait b7 b6 External area 3 wait bit 0 0: Without wait 0 1: With 1 wait 1 0: With 2 wait 1 1: With 3 wait Note 1: When using the multiplex bus configuration, there are two waits regardless of whether you have specified "No wait" or "1 wait". However, you can specify "2 wait" or "3 wait". Note 2: When using the separate bus configuration, the read bus cycle is executed in the BCLK1 cycle, and the write cycle is executed in the BCLK2 cycle (with 1 wait). Figure 7.6 Wait control register Table 7.11 Software waits and bus cycles Area SFR Internal ROM/RAM 0 1 002 Bus status Internal memory wait bit External memory area i wait bit Bus cycle 2 BCLK cycles 1 BCLK cycle 2 BCLK cycles Read :1 BCLK cycle Write : 2 BCLK cycles Separate bus External memory area 012 102 112 002 Multiplex bus 012 102 112 2 BCLK cycles 3 BCLK cycles 4 BCLK cycles 3 BCLK cycle 3 BCLK cycles 3 BCLK cycles 4 BCLK cycles Rev.1.00 Aug. 02, 2005 Page 40 REJ09B0187-0100 of 329 M16C/80 Group 7. Bus < Separate bus (no wait) > Bus cycle (Note) Bus cycle (Note) BCLK Write signal Read signal Data bus Address bus (Note 2) Chip select (Note 2,3) Output Address Input Address < Separate bus (with wait) > Bus cycle (Note) Bus cycle (Note) BCLK Write signal Read signal Output Address Address Input Data bus Address bus (Note 2) Chip select (Note 2,3) < Separate bus with 2 wait > Bus cycle (Note 1) Bus cycle (Note 1) BCLK Write signal Read signal Data bus Address bus (Note 2) Chip select (Note 2,3) Note 1: This timing example shows bus cycle length. Read cycle and write cycle may be continued after this bus cycle. Note 2: Address bus and chip select may get longer by a state of CPU such as an instruction queue buffer. Note 3: When accessing same external area (same CS area) continuously, chip select may output continuously. Data output Address Address Input Figure 7.7 Typical bus timings using software wait Rev.1.00 Aug. 02, 2005 Page 41 REJ09B0187-0100 of 329 M16C/80 Group 7. Bus < Separate bus (with 3 wait) > Bus cycle (Note) Bus cycle (Note) BCLK Write signal Read signal Data bus Address (Note 2) Chip select (Note 2,3) < Multiplexed bus (with 2 wait) > Bus cycle (Note) BCLK Write signal Read signal ALE Address Address bus/Data bus (Note 2) Chip select (Note 2,3) < Multiplexed bus (with 3 wait) > Bus cycle (Note) Address Address Data output Address Address Input Data output Address Address Input Bus cycle (Note) Bus cycle (Note) BCLK Write signal Read signal Address Address bus /Data bus (Note 2) ALE Chip select (Note 2,3) Note 1: This timing example shows bus cycle length. Read cycle and write cycle may be continued after this bus cycle. Note 2: Address bus and chip select may get longer by a state of CPU such as an instruction queue buffer. Note 3: When accessing same external area (same CS area) continuously, chip select may output continuously. Address Address Data output Address Address Input Figure 7.8 Typical bus timings using software wait Rev.1.00 Aug. 02, 2005 Page 42 REJ09B0187-0100 of 329 M16C/80 Group 8. Clock Generating Circuit 8. Clock Generating Circuit The clock generating circuit contains two oscillator circuits that supply the operating clock sources to the CPU and internal peripheral units. Table 8.1 Main clock and sub clock generating circuits Use of clock Main clock generating circuit Sub clock generating circuit * CPU's operating clock source * CPU's operating clock source * Internal peripheral units' * Timer A/B's count clock operating clock source source Ceramic or crystal oscillator Crystal oscillator XIN, XOUT XCIN, XCOUT Available Available Oscillating Stopped Externally derived clock can be input Usable oscillator Pins to connect oscillator Oscillation stop/restart function Oscillator status immediately after reset Other 8.1 Example of oscillator circuit Figure 8.1 shows some examples of the main clock circuit, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. Figure 8.2 shows some examples of sub clock circuits, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. Circuit constants in Figures 8.1 and 8.2 vary with each oscillator used. Use the values recommended by the manufacturer of your oscillator. Microcomputer (Built-in feedback resistance) Microcomputer (Built-in feedback resistance) XIN XOUT (Note) Rd XIN XOUT Open Externally derived clock CIN COUT Vcc Vss Note: Insert a damping resistance if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. When the oscillation drive capacity is set to low, check that oscillation is stable. Insert a feedback resistance between XIN and XOUT when an oscillation manufacture required. Figure 8.1 Examples of main clock Microcomputer (Built-in feedback resistance) Microcomputer (Built-in feedback resistance) XCIN XCOUT (Note) RCd XCIN XCOUT Open Externally derived clock CCIN CCOUT Vcc Vss Note: Insert a damping resistance if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. When the oscillation drive capacity is set to low, check that oscillation is stable. Insert a feedback resistance between XCIN and XCOUT when an oscillation manufacture required. Figure 8.2 Examples of sub clock Rev.1.00 Aug. 02, 2005 Page 43 REJ09B0187-0100 of 329 M16C/80 Group 8. Clock Generating Circuit 8.2 Clock Control Figure 8.3 shows the block diagram of the clock generating circuit. XCIN CM04 XCOUT 1/32 fC32 f1 f1SIO2 fC fAD f8 f32 f8SIO2 f32SIO2 Sub clock CM10 "1" Write signal SQ XIN R RESET Software reset NMI Interrupt request level judgment output WAIT instruction CM05 Main clock CM02 XOUT b a c Divider 1 e d Divider 2 CM07=0 BCLK SQ R fC CM07=1 b a 1/2 1/2 1/2 1/2 1/2 c Details of divider 1 a CM0i : Bit i at address 000616 CM1i : Bit i at address 000716 WDCi : Bit i at address 000F16 1/N divider e N is set by MCD4 to MCD0 as follow: N = 1, 2, 3, 4, 6, 8, 10, 12, 14 and 16 Details of divider 2 Figure 8.3 Clock generating circuit Rev.1.00 Aug. 02, 2005 Page 44 REJ09B0187-0100 of 329 M16C/80 Group 8. Clock Generating Circuit The following paragraphs describes the clocks generated by the clock generating circuit. (1) Main clock The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 000616). Switching to the sub clock oscillation as CPU operating clock source before stopping the clock reduces the power dissipation. When the main clock is stoped (bit 5 at address 000616 =1) or the mode is shifted to stop mode (bit 0 at address 000716 =1), the main clock division register (address 000C16) is set to the division by 8 ("0816"). After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock oscillation circuit can be reduced using the XIN-XOUT drive capacity select bit (bit 5 at address 000716). Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. This bit defaults to "1" when shifting from high-speed or middle-speed mode to stop mode and after a reset. This bit remains in low-speed and low power dissipation mode. (2) Sub clock The sub clock is generated by the sub clock oscillation circuit. No sub clock is generated after a reset. After oscillation is started using the port Xc select bit (bit 4 at address 000616), the sub clock can be selected as the BCLK by using the system clock select bit (bit 7 at address 000616). However, be sure that the sub clock oscillation has fully stabilized before switching. After the oscillation of the sub clock oscillation circuit has stabilized, the drive capacity of the sub clock oscillation circuit can be reduced using the XCIN-XCOUT drive capacity select bit (bit 3 at address 000616). Reducing the drive capacity of the sub clock oscillation circuit reduces the power dissipation. This bit changes to "1" when shifting to stop mode and at a reset. When the sub clock is used, set ports P86 and P87 to no pull-up resistance with the input port. (3) BCLK The BCLK is the clock that drives the CPU, and is either fc or is derived by dividing the main clock by 1, 2, 3, 4, 6, 8, 10, 12, 14 or 16. The BCLK is derived by dividing the main clock by 8 after a reset. This signal is output from BCLK pin using CM01, CM00 and PM07 in memory expansion mode and microprocessor mode. When main clock is stoped or shifting to stop mode, the main clock division register (address 000C16) is set to the division by 8 ("0816"). (4) Peripheral function clock * f1, f8, f32, f1SIO2, f8SIO2, f32SIO2 The clock for the peripheral devices is derived from the main clock or by dividing it by 8 or 32. The peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function clock stop bit (bit 2 at 000616) to "1" and then executing a WAIT instruction. * fAD This clock has the same frequency as the main clock and is used for A/D conversion. (5) fC32 This clock is derived by dividing the sub clock by 32. It is used for the timer A and timer B counts. (6) fC This clock has the same frequency as the sub clock. It is used for BCLK and for the watchdog timer. Figure 8.4 shows the system clock control registers 0 and 1 and Figure 8.5 shows main clock division register. Rev.1.00 Aug. 02, 2005 Page 45 REJ09B0187-0100 of 329 M16C/80 Group 8. Clock Generating Circuit System clock control register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol CM0 Bit symbol CM00 CM01 CM02 Address 000616 Bit name Clock output function select bit (Note 2) When reset 0816 Function b1 b0 RW 0 0 : I/O port P53 0 1 : fC output (Note 3) 1 0 : f8 output (Note 3) 1 1 : f32 output (Note 3) 0 : Do not stop peripheral clock in wait mode 1 : Stop peripheral clock in wait mode (Note 10) WAIT peripheral function clock stop bit CM03 CM04 CM05 CM06 CM07 XCIN-XCOUT drive capacity 0 : LOW select bit (Note 4) 1 : HIGH Port XC select bit 0 : I/O port 1 : XCIN-XCOUT generation (Note 11) Main clock (XIN-XOUT) stop bit (Note 5, 6) Watchdog timer function select bit System clock select bit (Note 9) 0 : On 1 : Off (Note 7) 0 : Watchdog timer interrupt 1 : Reset (Note 8) 0 : XIN, XOUT 1 : XCIN, XCOUT Note 1: Set bit 0 of the protect register (address 000A16) to "1" before writing to this register. Note 2: When outputting BCLK (bit 7 of processor mode register 0 is "0"), set these bits to "00". When outputting ALE to P53 (bit 5 and 4 of processor mode register 0 is "01"), set these bits to "00". The port P53 function is not selected even when you set "00" in microprocessor or memory expansion mode and bit 7 of the processor mode register 0 is "1". Note 3: When selecting fC, f8 or f32 in single chip mode, must use P57 as input port. Note 4: Changes to "1" when shifting to stop mode or reset. Note 5: When entering the power saving mode, the main clock is stopped using this bit. To stop the main clock, set system clock stop bit (CM07) to "1" while an oscillation of sub clock is stable. Then set this bit to "1". Note 6: When this bit is "1", XOUT is "H". Also, the internal feedback resistance remains ON, so XIN is pulled up to XOUT ("H" level) via the feedback resistance. Note 7: When the main clock is stopped, the main clock division register (address 000C16) is set to the division by 8 mode. Note 8: When "1" has been set once, "0" cannot be written by software. Note 9: To set CM07 "1" from "0", first set CM04 to "1", and an oscillation of sub clock is stable. Then set CM07. Also, to set CM07 "0" from "1", first set CM05 to "1", and an oscillation of main clock is stable. Then set CM07. Do not rewrite CM04 and CM05 simultaneously. Note 10: fc32 is not included. Note 11: When XcIN-XcOUT is used, set port P86 and P87 to no pull-up resistance with the input port. System clock control register 1 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 00 Symbol CM1 Bit symbol CM10 Reserved bit CM15 Reserved bit Address 000716 Bit name All clock stop control bit (Note 3) When reset 2016 Function 0 : Clock on 1 : All clocks off (stop mode) (Note 4) Always set to "0" RW XIN-XOUT drive capacity select bit (Note 2) Always set to "0" Note 1: Set bit 0 of the protect register (address 000A16) to "1" before writing to this register. Note 2: Changes to "1" when shifting from high-speed or middle-speed mode to stop mode or reset. This bit is remained in low speed or low power dissipation mode. Note 3: When this bit is "1", XOUT is "H", and the internal feedback resistance is disabled. XCIN and XCOUT are high-inpedance. Note 4: When the main clock is stopped, the main clock division register (address 000C16) is set to the division by 8 mode. Figure 8.4 System clock control registers 0 and 1 Rev.1.00 Aug. 02, 2005 Page 46 REJ09B0187-0100 of 329 M16C/80 Group 8. Clock Generating Circuit Main clock division register (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol MCD Bit symbol MCD0 MCD1 MCD2 MCD3 MCD4 Address 000C16 Bit name Main clock division select bit (Note 2) When reset XXX010002 Function b4 b3 b2 b1 b0 RW 10010 00010 00011 00100 00110 01000 01010 01100 01110 00000 : No division mode : Division by 2 mode : Division by 3 mode : Division by 4 mode : Division by 6 mode : Division by 8 mode : Division by 10 mode : Division by 12 mode : Division by 14 mode : Division by 16 mode Nothing is assigned. When write, set "0". When read, their contents are indeterminate. Note 1: Set bit 0 of the protect register (address 000A16) to "1" before writing to this register. Note 2: These bits are "010002" (8-division mode) when main clock is stopped or you shift to stop mode. Note 3: Do not attempt to set combinations of values other than those shown in this figure. Figure 8.5 Main clock division register 8.3 Clock Output In single chip mode, when the BCLK output function select bit (bit 7 at address 000416 :PM07) is "1", you can output f8, f32, or fc from the P53/BCLK/ALE/CLKOUT pins by setting the clock output function select bits (bits 1 and 0 at address 000616 :CM01, CM00).(Note) Even when you set PM07 to "0" and CM01 and CM00 to "002", no BCLK is output. In memory expansion mode or microprocessor mode, when the ALE pin select bits (bits 5 and 4 at address 000516 :PM15, PM14) are other than "012(P53/BCLK)" and PM07 is "1", you can output f8, f32, or fc from the P53/BCLK/ALE/CLKOUT pins by setting CM01 and CM00. In memory expansion mode or microprocessor mode, when PM15 and PM14 are other than "012(P53/ BCLK)" and PM07 is "0" and CM01 and CM00 to "002", BCLK is output from the P53/BCLK/ALE/CLKOUT pins. When stopping clock output in memory expansion mode or microprocessor mode, set PM07 to "1" and CM01 and CM00 to "002" (IO port P53). The P53 function is not selected. When PM15 and PM14 are "012 (P53/BCLK)" and CM01 and CM00 are "002", PM07 is ignored and the P53 pin is set for ALE output. When the WAIT peripheral function clock stop bit (bit 2 at address 000616) is set to "1", f8 or f32 clock output is stopped when a WAIT command is executed. Table 8.2 shows clock output setting (single chip mode) and Table 8.3 shows clock output setting (memory expansion/microprocessor mode). Note :When outputting the f8, f32 or fc from port P53/BCLK/ALE/CLKOUT pin in single chip mode, use port _______ P57/RDY as an input only port. Rev.1.00 Aug. 02, 2005 Page 47 REJ09B0187-0100 of 329 M16C/80 Group 8. Clock Generating Circuit Table 8.2 Clock output setting (single chip mode) BCLK output function select bit Clock output function select bit ALE pin select bit PM07 0/1 1 1 1 CM01 0 0 1 1 CM00 0 1 0 1 PM15 Ignored Ignored Ignored Ignored PM14 Ignored Ignored Ignored Ignored P53/BCLK/ALE/CLKOUT pin function P53 I/O port fc output (Note) f8 output (Note) f32 output (Note) Note :Must use P57 as input port. Table 8.3 Clock output setting (memory expansion/microprocessor mode) BCLK output function Clock output function select select bit bit ALE pin select bit PM07 0 1 1 1 1 Ignored CM01 0 0 0 1 1 0 CM00 0 0 1 0 1 0 PM15 PM14 P53/BCLK/ALE/CLKOUT pin function BCLK output 0 1 1 0 0 1 "L" output (not P53) fc output f8 output f32 output 0 1 ALE output 8.4 Stop Mode Writing "1" to the all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the microcomputer enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC remains above 2V. Because the oscillation of BCLK, f1 to f32, f1SIO2 to f32SIO2, fc, fc32, and fAD stops in stop mode, peripheral functions such as the A/D converter and watchdog timer do not function. However, timer A and timer B operate provided that the event counter mode is set to an external pulse, and UARTi(i = 0 to 2) functions provided an external clock is selected. Table 8.4 shows the status of the ports in stop mode. Stop mode is cancelled by a hardware reset or interrupt. When using an interrupt to exit stop mode, the relevant interrupt must have been enabled and set to a priority level above the level set by the interrupt priority set bits (bits 2, 1, and 0 at address 009F16) for exiting a stop/wait state. Set the interrupt priority set bits for the exit from a stop/wait state to the same level as the flag register (FLG) processor interrupt level (IPL). Figure 8.6 shows the exit priority register. The priority level of the interrupt which is not used to cancel stop mode, must have been changed to 0. When exiting stop mode using an interrupt, the relevant interrupt routine is executed. ______ If only a hardware reset or an NMI interrupt is used to cancel stop mode, change the priority level of all interrupt to 0, then shift to stop mode. When shifting to stop mode and reset, the main clock division register (000C16) is set to "0816". Rev.1.00 Aug. 02, 2005 Page 48 REJ09B0187-0100 of 329 M16C/80 Group 8. Clock Generating Circuit Table 8.4 Port status during stop mode Pin _______ _______ _______ Memory expansion mode Microprocessor mode Retains status before stop mode "H" (Note) ______ _________ Single-chip mode Address bus, data bus, CS0 to CS3, BHE _____ ______ ________ _________ RD, WR, WRL, WRH, DW, CASL, ________ CASH ________ RAS __________ "H" (Note) HLDA, BCLK "H" ALE "H" Port Retains status before stop mode Retains status before stop mode CLKOUT When fc selected "H" "H" When f8, f32 selected Retains status before stop mode Retains status before stop mode ________ ________ Note :When self-refresh is done in operating DRAM control, CAS and RAS becomes "L". Exit priority register b7 b6 b5 b4 b3 b2 b1 b0 Symbol RLVL Bit symbol RLVL0 RLVL1 Address 009F16 Bit name When reset XXXX00002 Function b2 b1 b0 RW Interrupt priority set bit for exiting Stop/Wait state (Note 1,2) RLVL2 FSIT High-speed interrupt set bit (Note 3) 0 0 0 : Level 0 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0: Interrupt priority level 7 = normal interrupt 1: Interrupt priority level 7 = high-speed interrupt Nothing is assigned. When write, set "0". When read, their contents are indeterminate. Note 1: Exits the Stop or Wait mode when the requested interrupt priority level is higher than that set in the exit priority register. Note 2: Set to the same value as the processor interrupt priority level (IPL) set in the flag register (FLG). Note 3: The high-speed interrupt can only be specified for interrupts with interrupt priority level 7. Specify interrupt priority level 7 for only one interrupt. Figure 8.6 Exit priority register Rev.1.00 Aug. 02, 2005 Page 49 REJ09B0187-0100 of 329 M16C/80 Group 8. Clock Generating Circuit 8.5 Wait Mode When a WAIT instruction is executed, the BCLK stops and the microcomputer enters the wait mode. In this mode, oscillation continues but the BCLK and watchdog timer stop. Writing "1" to the WAIT peripheral function clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal peripheral functions, allowing power dissipation to be reduced. Table 8.5 shows the status of the ports in wait mode. Wait mode is cancelled by a hardware reset or interrupt. If an interrupt is used to cancel wait mode, the microcomputer restarts using as BCLK the clock that had been selected when the WAIT instruction was executed. When using an interrupt to exit Wait mode, the relevant interrupt must have been enabled and set to a priority level above the level set by the interrupt priority set bits for exiting a stop/wait state (bits 2, 1, and 0 at address 009F16). Set the interrupt priority set bits for the exit from a stop/wait state to the same level as the flag register (FLG) processor interrupt level (IPL). The priority level of the interrupt which is not used to cancel wait mode, must have been changed to 0. When using an interrupt to exit Wait mode, the microcomputer resumes operating the clock that was operating when the WAIT command was executed as BCLK from the interrupt routine. ______ If only a hardware reset or an NMI interrupt is used to cancel stop mode, change the priority level of all interrupt to 0, then shift to wait mode. Table 8.5 Port status during wait mode Pin _______ _______ Memory expansion mode Microprocessor mode Retains status before wait mode "H" (Note) Single-chip mode Address bus, data bus, CS0 to CS3, ________ BHE _____ ______ ________ _________ ______ _________ RD, WR, WRL, WRH, DW, CASL, ________ CASH ________ RAS __________ "H" (Note) "H" "L" Retains status before wait mode Retains status before wait mode When fC selected Does not stop When f8, f32 selected Does not stop when the WAIT peripheral function clock stop bit is "0". When the WAIT peripheral function clock stop bit is "1", the status immediately prior to entering wait mode is maintained. ________ ________ Note :When self-refresh is done in operating DRAM control, CAS and RAS becomes "L". HLDA,BCLK ALE Port CLKOUT Rev.1.00 Aug. 02, 2005 Page 50 REJ09B0187-0100 of 329 M16C/80 Group 8. Clock Generating Circuit 8.6 Status Transition of BCLK Power dissipation can be reduced and low-voltage operation achieved by changing the count source for BCLK. Table 8.6 shows the operating modes corresponding to the settings of system clock control registers 0 and main clock division register. After a reset, operation defaults to division by 8 mode. When shifting to stop mode, reset or stopping main clock, the main clock division register (address 000C16) is set to "0816". (1) Division by 2 mode The main clock is divided by 2 to obtain the BCLK. (2) Division by 3 mode The main clock is divided by 3 to obtain the BCLK. (3) Division by 4 mode The main clock is divided by 4 to obtain the BCLK. (4) Division by 6 mode The main clock is divided by 6 to obtain the BCLK. (5) Division by 8 mode The main clock is divided by 8 to obtain the BCLK. After reset, this mode is executed. Note that oscillation of the main clock must have stabilized before transferring from this mode to no-division, division by 2, 6, 10, 12, 14 and 16 mode. Oscillation of the sub clock must have stabilized before transferring to low-speed and low power dissipation mode. (6) Division by 10 mode The main clock is divided by 10 to obtain the BCLK. (7) Division by 12 mode The main clock is divided by 12 to obtain the BCLK. (8) Division by 14 mode The main clock is divided by 14 to obtain the BCLK. (9) Division by 16 mode The main clock is divided by 16 to obtain the BCLK. (10) No-division mode The main clock is divided by 1 to obtain the BCLK. (11) Low-speed mode fC is used as BCLK. Note that oscillation of both the main and sub clocks must have stabilized before transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the sub clock starts. Therefore, the program must be written to wait until this clock has stabilized immediately after powering up and after stop mode is cancelled. (12) Low power dissipation mode fC is the BCLK and the main clock is stopped. When the main clock is stoped, the main clock division register (address 000C16) is set to the division by 8 mode. Rev.1.00 Aug. 02, 2005 Page 51 REJ09B0187-0100 of 329 M16C/80 Group 8. Clock Generating Circuit Note: When count source of BCLK is changed from clock A to clock B (XIN to XCIN or XCIN to XIN), clock B needs to be stable before changing. Please wait to change modes until after oscillation has stabilized. Table 8.6 Operating modes dictated by settings of system clock control register 0 and main clock division register CM07 CM05 CM04 MCD4 MCD3 MCD2 MCD1 MCD0 Operating mode of BCLK 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid 1 1 1 0 0 0 0 0 0 0 0 0 Invalid Invalid 0 0 0 0 0 1 1 1 1 0 Invalid Invalid 0 0 0 1 1 0 0 1 1 0 Invalid Invalid 1 1 1 0 1 0 1 0 1 0 Invalid Invalid 0 0 1 0 0 0 0 0 0 0 Invalid Invalid No division Division by 2 mode Division by 3 mode Division by 4 mode Division by 6 mode Division by 8 mode Division by 10 mode Division by 12 mode Division by 14 mode Division by 16 mode Low-speed mode Low power dissipation mode CM0i: Clock control register 0 (address 000616) bit i MCDi: Main clock division register (address 000C16) bit i Rev.1.00 Aug. 02, 2005 Page 52 REJ09B0187-0100 of 329 M16C/80 Group 8. Clock Generating Circuit 8.7 Power Saving In Power Save modes, the CPU and oscillator stop and the operating clock is slowed to minimize power dissipation by the CPU. The following outlines the Power Save modes. There are three power save modes. (1) Normal operating mode * High-speed mode In this mode, one main clock cycle forms BCLK. The CPU operates on the selected internal clock. The peripheral functions operate on the clocks specified for each respective function. * Medium-speed mode In this mode, the main clock is divided into 2, 3, 4, 6, 8, 10, 12, 14, or 16 to form BCLK. The CPU operates on the selected internal clock. The peripheral functions operated on the clocks specified for each respective function. * Low-speed mode In this mode, fc forms BCLK. The CPU operates on the fc clock. fc is the clock supplied by the subclock. The peripheral functions operate on the clocks specified for each respective function. * Low power-dissipation mode This mode is selected when the main clock is stopped from low-speed mode. The CPU operates on the fc clock. fc is the clock supplied by the subclock. Only the peripheral functions for which the subclock was selected as the count source continue to run. (2) Wait mode CPU operation is halted in this mode. The oscillator continues to run. (3) Stop mode All oscillators stop in this mode. The CPU and internal peripheral functions all stop. Of all 3 power saving modes, power savings are greatest in this mode. Figure 8.7 shows the clock transition between each of the three modes, (1), (2), and (3). Rev.1.00 Aug. 02, 2005 Page 53 REJ09B0187-0100 of 329 M16C/80 Group 8. Clock Generating Circuit Transition of stop mode, wait mode Reset All oscillators stopped CM10="1" WAIT instruction Medium-speed mode (Divided-by-8 mode) Interrupt CPU operation stopped Stop mode Interrupt Wait mode Note 1 Interrupt CM10="1" WAIT instruction High-speed/mediumspeed mode Interrupt CPU operation stopped Wait mode All oscillators stopped CM10="1" Note 1 Note 2 WAIT instruction Interrupt CPU operation stopped Stop mode Interrupt Low-speed/low power dissipation mode Wait mode Note 3 Note 4 Normal mode (Please see the following as transition of normal mode.) Note 1: Switch clocks after oscillation of main clock is fully stable. After stop mode or when main clock oscillation is stopped, transferred to the middle speed mode. Note 2: Switch clocks after oscillation of sub clock is fully stable. Note 3: The main ckock devision register is set to the division by 8 mode (MCD="0816"). Note 4: When shifting to low power dissipation mode, the main ckock devision register is set to the division by 8 mode (MCD="0816"). Transition of normal mode Please change according to a direction of an arrow. Main clock is oscillating Sub clock is stopped Medium-speed mode (divided-by-8 mode) BCLK :f(XIN)/8 High-speed/medium-speed mode MCD="XX16" Main clock is oscillating Sub clock is stopped High-speed mode BCLK :f(XIN) CM07="0" MCD="1216" Medium-speed mode (divided-by-2, 3, 4, 6, 10, 12, 14 and 16 mode) BCLK :f(XIN)/division rate CM07="0" MCD="XX16" CM04="1" CM07="0" MCD="0816" Note 1, 3 Main clock is oscillating Sub clock is oscillating High-speed mode BCLK :f(XIN) CM04="0" CM07="0" MCD="1216" CM04="1" MCD="XX16" Note 1, 3 Medium-speed mode (divided-by-2, 3, 4, 6, 8, 10, 12, 14 and 16 mode) BCLK :f(XIN)/division rate CM07="0" MCD="XX16" Note 4 CM07="0" MCD="XX16" CM04="1" Note 4 Note 1 Note 3 Low-speed/low power dissipation mode Main clock is stopped Sub clock is oscillating CM07="0 Note 1 MCD="XX16" Note CM07="1" 3 Note 2 Low power dissipation mode CM05="1" BCLK :f(XCIN) CM07="1" CM05="0" Main clock is oscillating Sub clock is oscillating Low-speed mode BCLK :f(XCIN) CM07="1" Note 4 Note 1: Switch clocks after oscillation of main clock is fully stable. Note 2: Switch clocks after oscillation of sub clock is fully stable. Note 3: Set the desired division to the main clock division register (MCD). Note 4: When shifting to division by 8 mode, MCD is set to "0816". Figure 8.7 Clock transition Rev.1.00 Aug. 02, 2005 Page 54 REJ09B0187-0100 of 329 M16C/80 Group 8. Clock Generating Circuit 8.8 Protection The protection function is provided so that the values in important registers cannot be changed in the event that the program runs out of control. Figure 8.8 shows the protect register. The values in the processor mode register 0 (address 000416), processor mode register 1 (address 000516), system clock control register 0 (address 000616), system clock control register 1 (address 000716), main clock division register (address 000C16), port P9 direction register (address 03C716) and function select register A3 (address 03B516) can only be changed when the respective bit in the protect register is set to "1". Therefore, important outputs can be allocated to port P9. If, after "1" (write-enabled) has been written to the PRC2 (bit 2 at address 000A16), a value is written to any address, the bit automatically reverts to "0" (write-inhibited). Change port P9 input/output and function select register A3 immediately after setting "1" to PRC2. Interrupt and DMA transfer should not be inserted between instructions. However, the PRC0 (bit 0 at address 000A16) and PRC1 (bit 1 at address 000A16) do not automatically return to "0" after a value has been written to an address. The program must therefore be written to return these bits to "0". Protect register b7 b6 b5 b4 b3 b2 b1 b0 Symbol PRCR Bit symbol PRC0 Address 000A16 Bit name When reset XXXXX0002 Function RW Enables writing to system clock control registers 0 and 1 (addresses 0 : Write-inhibited 000616 and 000716) and main clock 1 : Write-enabled division register (address 000C16) Enables writing to processor mode 0 : Write-inhibited registers 0 and 1 (addresses 000416 1 : Write-enabled and 000516) Enables writing to port P9 direction register (address 03C716) and function select register A3 (address 03B516) (Note) 0 : Write-inhibited 1 : Write-enabled PRC1 PRC2 Nothing is assigned. When write, set "0". When read, their contents are indeterminate. Note: Writing a value to an address after "1" is written to this bit returns the bit to "0". Other bits do not automatically return to "0" and they must therefore be reset by the program. Figure 8.8 Protect register Rev.1.00 Aug. 02, 2005 Page 55 REJ09B0187-0100 of 329 M16C/80 Group 9. Interrupt Outline 9. Interrupt Outline 9.1 Types of Interrupts Figure 9.1 lists the types of interrupts. Software Special Hardware Peripheral I/O*1 *1 Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system. High-speed interrupt can be used as highest priority in peripheral I/O interrupts. Figure 9.1 Classification of interrupts * Maskable interrupt * Non-maskable interrupt : An interrupt which can be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority can be changed by priority level. : An interrupt which cannot be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority cannot be changed by priority level. Rev.1.00 Aug. 02, 2005 Page 56 REJ09B0187-0100 of 329 Interrupt Undefined instruction (UND instruction) Overflow (INTO instruction) BRK instruction BRK2 instruction INT instruction _______ Reset NMI Watchdog timer Single step Address matched M16C/80 Group 9. Interrupt Outline 9.2 Software Interrupts Software interrupts are generated by some instruction that generates an interrupt request when executed. Software interrupts are nonmaskable interrupts. (1) Undefined-instruction interrupt This interrupt occurs when the UND instruction is executed. (2) Overflow interrupt This interrupt occurs if the INTO instruction is executed when the O flag is 1. The following lists the instructions that cause the O flag to change: ABS, ADC, ADCF, ADD, ADDX, CMP, CMPX, DIV, DIVU, DIVX, NEG, RMPA, SBB, SCMPU, SHA, SUB, SUBX (3) BRK interrupt This interrupt occurs when the BRK instruction is executed. (4) BRK2 interrupt This interrupt occurs when the BRK2 instruction is executed. This interrupt is used exclusively for debugger purposes. You normally do not need to use this interrupt. (5) INT instruction interrupt This interrupt occurs when the INT instruction is executed after specifying a software interrupt number from 0 to 63. Note that software interrupt numbers 0 to 43 are assigned to peripheral I/O interrupts. This means that by executing the INT instruction, you can execute the same interrupt routine as used in peripheral I/O interrupts. The stack pointer used in INT instruction interrupt varies depending on the software interrupt number. For software interrupt numbers 0 to 31, the U flag is saved when an interrupt occurs and the U flag is cleared to 0 to choose the interrupt stack pointer (ISP) before executing the interrupt sequence. The previous U flag before the interrupt occurred is restored when control returns from the interrupt routine. For software interrupt numbers 32 to 63, such stack pointer switchover does not occur. However, in peripheral I/O interrupts, the U flag is saved when an interrupt occurs and the U flag is cleared to 0 to choose ISP. Therefore movement of U flag is different by peripheral I/O interrupt or INT instruction in software interrupt number 32 to 43. Rev.1.00 Aug. 02, 2005 Page 57 REJ09B0187-0100 of 329 M16C/80 Group 9. Interrupt Outline 9.3 Hardware Interrupts There are Two types in hardware Interrupts; special interrupts and Peripheral I/O interrupts. (1) Special interrupts Special interrupts are nonmaskable interrupts. * Reset ____________ A reset occurs when the RESET pin is pulled low. ______ * NMI interrupt ______ This interrupt occurs when the NMI pin is pulled low. * Watchdog timer interrupt This interrupt is caused by the watchdog timer. * Address-match interrupt This interrupt occurs immediately before the instruction at the address indicated by the address match interrupt register is executed while the address match interrupt enable bit is set to "1". This interrupt does not occur if any address other than the start address of an instruction is set in the address match register. * Single-step interrupt This interrupt is used exclusively for debugger purposes, do not use it in other circumstances. A singlestep interrupt occurs when the D flag is set (= 1); in this case, an interrupt is generated after one instruction is executed. (2) Peripheral I/O interrupts A peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral functions are dependent on classes of products, so the interrupt factors too are dependent on classes of products. The interrupt vector table is the same as the one for software interrupt numbers 0 through 43 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts. * Bus collision detection, start/stop condition detection interrupts (UART2, UART3, UART4), fault error interrupts (UART3, 4) This is an interrupt that the serial I/O bus collision detection generates. When I2C mode is selected, _____ start, stop condition interrupt is selected. When SS pin is selected, fault error interrupt is selected. * DMA0 through DMA3 interrupts These are interrupts that DMA generates. * Key-input interrupt ___ A key-input interrupt occurs if an "L" is input to the KI pin. * A/D conversion interrupt This is an interrupt that the A/D converter generates. * UART0, UART1, UART2/NACK, UART3/NACK and UART4/NACK transmission interrupt These are interrupts that the serial I/O transmission generates. * UART0, UART1, UART2/ACK, UART3/ACK and UART4/ACK reception interrupt These are interrupts that the serial I/O reception generates. * Timer A0 interrupt through timer A4 interrupt These are interrupts that timer A generates * Timer B0 interrupt through timer B5 interrupt These are interrupts that timer B generates. _______ ________ * INT0 interrupt through INT5 interrupt _____ _____ An INT interrupt selects a edge sense or a level sense. In edge sense, an INT interrupt occurs if either _____ _____ a rising edge or a falling edge or a both edge is input to the INT pin. In level sense, an INT interrupt _____ occurs if either an "H" level or an "L" level is input to the INT pin. Rev.1.00 Aug. 02, 2005 Page 58 REJ09B0187-0100 of 329 M16C/80 Group 9. Interrupt Outline 9.4 High-speed interrupts High-speed interrupts are interrupts in which the response is executed at 5 cycles and the return is 3 cycles. When a high-speed interrupt is received, the flag register (FLG) and program counter (PC) are saved to the save flag register (SVF) and save PC register (SVP) and the program is executed from the address shown in the vector register (VCT). Execute a FREIT instruction to return from the high-speed interrupt routine. High-speed interrupts can be set by setting "1" in the high-speed interrupt specification bit allocated to bit 3 of the exit priority register. Setting "1" in the high-speed interrupt specification bit makes the interrupt set to level 7 in the interrupt control register into a high-speed interrupt. You can only set one interrupt as a high-speed interrupt. When using a high-speed interrupt, do not set multiple interrupts as level 7 interrupts. The interrupt vector for a high-speed interrupt must be set in the vector register (VCT). When using a high-speed interrupt, you can use a maximum of two DMAC channels. The execution speed is improved when register bank 1 is used with high speed interrupt register selected by not saving registers to the stack but to the switching register bank. In this case, switch register bank mode for high-speed interrupt routine. 9.5 Interrupts and Interrupt Vector Tables If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector table. Set the first address of the interrupt routine in each vector table. Figure 9.2 shows the format for specifying the address. Two types of interrupt vector tables are available -- fixed vector table in which addresses are fixed and variable vector table in which addresses can be varied by the setting. MSB LSB Low address Mid address High address 0000 0000 Vector address + 0 Vector address + 1 Vector address + 2 Vector address + 3 Figure 9.2 Format for specifying interrupt vector addresses Rev.1.00 Aug. 02, 2005 Page 59 REJ09B0187-0100 of 329 M16C/80 Group 9. Interrupt Outline * Fixed vector tables The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area extending from FFFFDC16 to FFFFFF16. One vector table comprises four bytes. Set the first address of interrupt routine in each vector table. Table 9.1 shows the interrupts assigned to the fixed vector tables and addresses of vector tables. Table 9.1 Interrupt factors (fixed interrupt vector addresses) Interrupt source Vector table addresses Remarks Address (L) to address (H) Undefined instruction FFFFDC16 to FFFFDF16 Interrupt on UND instruction Overflow FFFFE016 to FFFFE316 Interrupt on INTO instruction BRK instruction FFFFE416 to FFFFE716 If content of FFFFE716 is filled with FF16, program execution starts from the address shown by the vector in the variable vector table Address match FFFFE816 to FFFFEB16 There is an address-matching interrupt enable bit Watchdog timer FFFFF016 to FFFFF316 _______ _______ NMI FFFFF816 to FFFFFB16 External interrupt by input to NMI pin Reset FFFFFC16 to FFFFFF16 * Vector table dedicated for emulator Table 9.2 shows interrupt vector address which is vector table register dedicated for emulator (address 00002016 to 00002216). These instructions are not effected with interrupt enable flag (I flag) (non maskable interrupt). This interrupt is used exclusively for debugger purposes. You normally do not need to use this interrupt. Do not access to the interrupt vector table register dedicated for emulator (address 00002016 to 00002216). Table 9.2 Interrupt vector table register for emulator Interrupt source Vector table addresses Address (L) to address (H) BRK2 instruction Interrupt vector table register for emulator 00002016 to 00002216 Single step Interrupt vector table register for emulator 00002016 to 00002216 Remarks Interrupt for debugger Interrupt for debugger * Variable vector tables The addresses in the variable vector table can be modified, according to the user's settings. Indicate the first address using the interrupt table register (INTB). The 256-byte area subsequent to the address the INTB indicates becomes the area for the variable vector tables. One vector table comprises four bytes. Set the first address of the interrupt routine in each vector table. Table 9.3 shows the interrupts assigned to the variable vector tables and addresses of vector tables. Set an even address to the start address of vector table setting in INTB so that operating efficiency is increased. Rev.1.00 Aug. 02, 2005 Page 60 REJ09B0187-0100 of 329 M16C/80 Group 9. Interrupt Outline Table 9.3 Interrupt causes (variable interrupt vector addresses) Software interrupt number Software interrupt number 0 Vector table address Address (L) to address (H) Interrupt source BRK instruction Remarks Cannot be masked I flag +0 to +3 (Note 1) Software interrupt number 8 Software interrupt number 9 Software interrupt number 10 Software interrupt number 11 Software interrupt number 12 Software interrupt number 13 Software interrupt number 14 Software interrupt number 15 Software interrupt number 16 Software interrupt number 17 Software interrupt number 18 Software interrupt number 19 Software interrupt number 20 Software interrupt number 21 Software interrupt number 22 Software interrupt number 23 Software interrupt number 24 Software interrupt number 25 Software interrupt number 26 Software interrupt number 27 Software interrupt number 28 Software interrupt number 29 Software interrupt number 30 Software interrupt number 31 Software interrupt number 32 Software interrupt number 33 Software interrupt number 34 Software interrupt number 35 Software interrupt number 36 Software interrupt number 37 Software interrupt number 38 Software interrupt number 39 Software interrupt number 40 Software interrupt number 41 Software interrupt number 42 Software interrupt number 43 Software interrupt number 44 to Software interrupt number 63 +32 to +35 (Note 1) +36 to +39 (Note 1) +40 to +43 (Note 1) +44 to +47 (Note 1) +48 to +51 (Note 1) +52 to +55 (Note 1) +56 to +59 (Note 1) +60 to +63 (Note 1) +64 to +67 (Note 1) +68 to +71 (Note 1) +72 to +75 (Note 1) +76 to +79 (Note 1) +80 to +83 (Note 1) +84 to +87 (Note 1) +88 to +91 (Note 1) +92 to +95 (Note 1) +96 to +99 (Note 1) +100 to +103 (Note 1) +104 to +107 (Note 1) +108 to +111 (Note 1) +112 to +115 (Note 1) +116 to +119 (Note 1) +120 to +123 (Note 1) +124 to +127 (Note 1) +128 to +131 (Note 1) +132 to +135 (Note 1) +136 to +139 (Note 1) +140 to +143 (Note 1) +144 to +147 (Note 1) +148 to +151 (Note 1) +152 to +155 (Note 1) +156 to +159 (Note 1) +160 to +163 (Note 1) +164 to +167 (Note 1) +168 to +171 (Note 1) +172 to +175 (Note 1) +176 to +179 (Note 1) to +252 to +255 (Note 1) DMA0 DMA1 DMA2 DMA3 Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 UART0 transmit UART0 receive UART1 transmit UART1 receive Timer B0 Timer B1 Timer B2 Timer B3 Timer B4 INT5 INT4 INT3 INT2 INT1 INT0 Timer B5 UART2 transmit/NACK (Note 2) UART2 receive/ACK (Note 2) UART3 transmit/NACK (Note 2) UART3 receive/ACK (Note 2) UART4 transmit/NACK (Note 2) UART4 receive/ACK (Note 2) Bus collision detection, start/stop condition detection (UART2) (Note 2) Bus collision detection, start/stop condition detection, fault error (UART3) (Note 2, 3) Bus collision detection, start/stop condition detection, fault error (UART4) (Note 2, 3) A/D Key input interrupt Software interrupt Cannot be masked I flag Note 1: Address relative to address in interrupt table register (INTB). Note 2: When I 2 C mode is selected, NACK/ACK, start/stop condition detection interrupts are selected. Note 3: The fault error interrupt is selected when SS pin is selected. Rev.1.00 Aug. 02, 2005 Page 61 REJ09B0187-0100 of 329 M16C/80 Group 9. Interrupt Outline 9.6 Interrupt control registers Peripheral I/O interrupts have their own interrupt control registers. Figure 9.3 shows the interrupt control registers. When using an interrupt to exit Stop mode or Wait mode, the relevant interrupt must have been enabled and set to a priority level above the level set by the interrupt priority set bits for exit a stop/wait state (bits 2, 1, and 0 at address 009F16). Set the interrupt priority set bits for the exit from a stop/wait state to the same level as the flag register (FLG) processor interrupt level (IPL). Figure 9.4 shows the exit priority register. Rev.1.00 Aug. 02, 2005 Page 62 REJ09B0187-0100 of 329 M16C/80 Group 9. Interrupt Outline Interrupt control register Symbol Address ADIC 007316 BCNiIC(i=2 to 4) 008F16, 007116, 009116 DMiIC(i=0 to 3) 006816, 008816, 006A16, 008A16 KUPIC 009316 TAiIC(i=0 to 4) 006C16, 008C16, 006E16, 008E16, 007016 TBiIC(i=0 to 5) 009416, 007616, 009616, 007816, 009816, 006916 SiTIC(i=0 to 4) 009016, 009216, 008916, 008B16, 008D16 SiRIC(i=0 to 4) 007216, 007416, 006B16, 006D16, 006F16 When reset XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 R W b7 b6 b5 b4 b3 b2 b1 b0 Bit symbol ILVL0 Bit name Interrupt priority level select bit b2 b1 b0 Function 000: 001: 010: 011: 100: 101: 110: 111: Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 ILVL1 ILVL2 IR Interrupt request bit 0 : Interrupt not requested 1 : Interrupt requested (Note) Nothing is assigned. When write, set "0". When read, their contents are indeterminate. Note: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). b7 b6 b5 b4 b3 b2 b1 b0 Symbol INTiIC(i=0 to 5) Address When reset 009E16, 007E16, 009C16, 007C16, 009A16, 007A16 XX00X0002 Bit symbol ILVL0 Bit name Interrupt priority level select bit b2 b1 b0 Function 0 0 0 : Level 0 (interrupt disabled) (Note 2) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0: Interrupt not requested 1: Interrupt requested 0 : Selects falling edge or L level 1 : Selects rising edge or H level 0 : Edge sense 1 : Level sense R W ILVL1 ILVL2 IR Interrupt request bit (Note 1) POL Polarity select bit LVS Level sense/edge sense select bit (Note 3) Nothing is assigned. When write, set "0". When read, their contents are indeterminate. Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). Note 2: When INT3 to INT5 are used for data bus in microprocessor mode or memory expansion mode, set the interrupt disabled to INT3IC, INT4IC and INT5IC. Note 3: When level sense is selected, set related bit of interrupt cause select register ( address 031F16) to one edge. Figure 9.3 Interrupt control register Rev.1.00 Aug. 02, 2005 Page 63 REJ09B0187-0100 of 329 M16C/80 Group 9. Interrupt Outline Exit priority register b7 b6 b5 b4 b3 b2 b1 b0 Symbol RLVL Bit symbol RLVL0 RLVL1 Address 009F16 Bit name When reset XXXX00002 Function b2 b1 b0 RW Interrupt priority set bit for exiting Stop/Wait state (Note 1,2) RLVL2 FSIT High-speed interrupt set bit (Note 3) 0 0 0 : Level 0 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0: Interrupt priority level 7 = normal interrupt 1: Interrupt priority level 7 = high-speed interrupt Nothing is assigned. When write, set "0". When read, their contents are indeterminate. Note 1: Exits the Stop or Wait mode when the requested interrupt priority level is higher than that set in the exit priority register. Note 2: Set to the same value as the processor interrupt priority level (IPL) set in the flag register (FLG). Note 3: The high-speed interrupt can only be specified for interrupts with interrupt priority level 7. Specify interrupt priority level 7 for only one interrupt. Figure 9.4 Exit priority register 9.7 Interrupt Enable Flag (I Flag) The interrupt enable flag (I flag) is used to disable/enable maskable interrupts. When this flag is set (= 1), all maskable interrupts are enabled; when the flag is cleared to 0, they are disabled. This flag is automatically cleared to 0 after a reset is cleared. 9.8 Interrupt Request Bit This bit is set (= 1) by hardware when an interrupt request is generated. The bit is cleared to 0 by hardware when the interrupt request is acknowledged and jump to the interrupt vector. This bit can be cleared to 0 (but cannot be set to 1) in software. 9.9 Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL) Interrupt priority levels are set by the interrupt priority select bit in an interrupt control register. When an interrupt request is generated, the interrupt priority level of this interrupt is compared with the processor interrupt priority level (IPL). This interrupt is enabled only when its interrupt priority level is greater than the processor interrupt priority level (IPL). This means that you can disable any particular interrupt by setting its interrupt priority level to 0. Rev.1.00 Aug. 02, 2005 Page 64 REJ09B0187-0100 of 329 M16C/80 Group 9. Interrupt Outline Table 9.4 shows how interrupt priority levels are set. Table 9.5 shows interrupt enable levels in relation to the processor interrupt priority level (IPL). The following lists the conditions under which an interrupt request is acknowledged: * Interrupt enable flag (I flag) =1 * Interrupt request bit =1 * Interrupt priority level > Processor interrupt priority level (IPL) The interrupt enable flag (I flag), interrupt request bit, interrupt priority level select bit, and the processor interrupt priority level (IPL) all are independent of each other, so they do not affect any other bit. Table 9.4 Interrupt Priority Levels Interrupt priority Interrupt priority level level select bit b2 b1 b0 Table 9.5 IPL and Interrupt Enable Levels Priority order Processor interrupt priority level (IPL) IPL2 IPL1 IPL0 Enabled interrupt priority levels Interrupt levels 1 and above are enabled. Interrupt levels 2 and above are enabled. Interrupt levels 3 and above are enabled. Interrupt levels 4 and above are enabled. Interrupt levels 5 and above are enabled. Interrupt levels 6 and above are enabled. Interrupt levels 7 and above are enabled. All maskable interrupts are disabled. 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Level 0 (interrupt disabled) 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Low 0 0 0 1 1 1 High 1 9.10 Rewrite the interrupt control register When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been generated. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : AND, OR, BCLR, BSET Rev.1.00 Aug. 02, 2005 Page 65 REJ09B0187-0100 of 329 M16C/80 Group 9. Interrupt Outline 9.11 Interrupt Sequence An interrupt sequence -- what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed -- is described here. If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. If an interrupt occurs during execution of either the SCMPU, SIN, SMOVB, SMOVF, SMOVU, SSTR, SOUT or RMPA instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. In the interrupt sequence, the processor carries out the following in sequence given: (1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading address 00000016 (address 00000216 when high-speed interrupt). After this, the related interrupt request bit is "0". (2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt sequence in the temporary register (Note) within the CPU. (3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag) to "0" (the U flag, however does not change if the INT instruction, in software interrupt numbers 32 through 63, is executed) (4) Saves the content of the temporary register (Note 1) within the CPU in the stack area. Saves in the flag save register (SVF) in high-speed interrupt. (5) Saves the content of the program counter (PC) in the stack area. Saves in the PC save register (SVP) in high-speed interrupt. (6) Sets the interrupt priority level of the accepted instruction in the IPL. After the interrupt sequence is completed, the processor resumes executing instructions from the first address of the interrupt routine. Note: This register cannot be utilized by the user. 9.12 Interrupt Response Time 'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first instruction within the interrupt routine has been executed. This time comprises the period from the occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the time required for executing the interrupt sequence (b). Figure 9.5 shows the interrupt response time. Interrupt request generated Interrupt request acknowledged Time Instruction (a) Interrupt sequence (b) Instruction in interrupt routine Interrupt response time (a) The period from the occurrence of an interrupt to the completion of the instruction under execution. (b) The time required for executing the interrupt sequence. Figure 9.5 Interrupt response time Rev.1.00 Aug. 02, 2005 Page 66 REJ09B0187-0100 of 329 M16C/80 Group 9. Interrupt Outline Time (a) varies with each instruction being executed. The DIVX instruction requires a maximum time that consists of 24* cycles. Time (b) is shown in Table 9.6. * It is when the divisor is immediate or register. When the divisor is memory, the following value is added. * Normal addressing :2+X * Index addressing :3+X * Indirect addressing : 5 + X + 2Y * Indirect index addressing : 6 + X + 2Y X is number of wait of the divisor area. Y is number of wait of the indirect address stored area. When X and Y are in odd address or in 8 bits bus area, double the value of X and Y. Table 9.6 Interrupt Sequence Execution Time Interrupt Peripheral I/O INT instruction _______ Interrupt vector address Even address Odd address (Note 1) Even address Odd address (Note 1) Even address (Note 2) 16 bits data bus 14 cycles 16 cycles 12 cycles 14 cycles 13 cycles 8 bits data bus 16 cycles 16 cycles 14 cycles 14 cycles 15 cycles NMI Watchdog timer Undefined instruction Address match Overflow BRK instruction (Variable vector table) Single step BRK2 instruction BRK instruction (Fixed vector table) High-speed interrupt (Note 3) Even address (Note 2) Even address Odd address (Note 1) Even address (Note 2) 14 cycles 17 cycles 19 cycles 19 cycles 16 cycles 19 cycles 19 cycles 21 cycles Vector table is internal register 5 cycles Note 1: Allocate interrupt vector addresses in even addresses, if possible. Note 2: The vector table is fixed to even address. Note 3: The high-speed interrupt is independent of these conditions. Rev.1.00 Aug. 02, 2005 Page 67 REJ09B0187-0100 of 329 M16C/80 Group 9. Interrupt Outline 9.13 Changes of IPL When Interrupt Request Acknowledged When an interrupt request is acknowledged, the interrupt priority level of the acknowledged interrupt is set to the processor interrupt priority level (IPL). If an interrupt request is acknowledged that does not have an interrupt priority level, the value shown in Table 9.7 is set to the IPL. Table 9.7 Relationship between Interrupts without Interrupt Priority Levels and IPL Interrupt sources without interrupt priority levels _______ Value that is set to IPL 7 0 Not changed Watchdog timer, NMI Reset Other 9.14 Saving Registers In an interrupt sequence, only the contents of the flag register (FLG) and program counter (PC) are saved to the stack area. The order in which these contents are saved is as follows: First, the FLG register is saved to the stack area. Next, the 16 high-order bits and 16 low-order bits of the program counter expanded to 32-bit are saved. Figure 9.6 shows the stack status before an interrupt request is acknowledged and the stack status after an interrupt request is acknowledged. In a high-speed interrupt sequence, the contents of the flag register (FLG) is saved to the flag save register (SVF) and program counter (PC) is saved to PC save register (SVP). If there are any other registers you want to be saved, save them in software at the beginning of the interrupt routine. The PUSHM instruction allows you to save all registers except the stack pointer (SP) by a single instruction. The execution speed is improved when register bank 1 is used with high speed interrupt register selected by not saving registers to the stack but to the switching register bank. In this case, switch register bank mode for high-speed interrupt routine. Address MSB Stack area LSB Address Stack area MSB Program counter (PCL) Program counter (PC M) Program counter (PC H) 0 0 LSB m-6 m-5 m-4 m-3 m-2 m-1 m m+1 Content of previous stack Content of previous stack [SP] Stack pointer value before interrupt occurs m-6 m-5 m-4 m-3 m-2 m-1 m m+1 [SP] New stack pointer value Flag register (FLG L) Flag register (FLG H) Content of previous stack Content of previous stack Stack status before interrupt request is acknowledged Stack status after interrupt request is acknowledged Figure 9.6 Stack status before and after an interrupt request is acknowledged Rev.1.00 Aug. 02, 2005 Page 68 REJ09B0187-0100 of 329 M16C/80 Group 9. Interrupt Outline 9.15 Return from Interrupt Routine As you execute the REIT instruction at the end of the interrupt routine, the contents of the flag register (FLG) and program counter (PC) that have been saved to the stack area immediately preceding the interrupt sequence are automatically restored. In high-speed interrupt, as you execute the FREIT instruction at the end of the interrupt routine, the contents of the flag register (FLG) and program counter (PC) that have been saved to the save registers immediately preceding the interrupt sequence are automatically restored. Then control returns to the routine that was under execution before the interrupt request was acknowledged, and processing is resumed from where control left off. If there are any registers you saved via software in the interrupt routine, be sure to restore them using an instruction (e.g., POPM instruction) before executing the REIT or FREIT instruction. When switching the register bank before executing REIT and FREIT instruction, switched to the register bank immediately before the interrupt sequence. 9.16 Interrupt Priority If two or more interrupt requests are sampled active at the same time, whichever interrupt request is acknowledged that has the highest priority. Maskable interrupts (Peripheral I/O interrupts) can be assigned any desired priority by setting the interrupt priority level select bit accordingly. If some maskable interrupts are assigned the same priority level, the priority between these interrupts is resolved by the priority that is set in hardware. Certain nonmaskable interrupts such as a reset (reset is given the highest priority) and watchdog timer interrupt have their priority levels set in hardware. Figure 9.7 lists the hardware priority levels of these interrupts. Software interrupts are not subjected to interrupt priority. They always cause control to branch to an interrupt routine whenever the relevant instruction is executed. 9.17 Interrupt Resolution Circuit Interrupt resolution circuit selects the highest priority interrupt when two or more interrupt requests are sampled active at the same time. Figure 9.8 shows the interrupt resolution circuit. _______ Reset > NMI > Watchdog > Peripheral I/O > Single step > Address match Figure 9.7 Interrupt priority that is set in hardware Rev.1.00 Aug. 02, 2005 Page 69 REJ09B0187-0100 of 329 M16C/80 Group 9. Interrupt Outline High Priority level of each interrupt Level 0 (initial value) DMA0 DMA1 DMA2 DMA3 Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 UART0 transmission UART0 reception UART1 transmission UART1 reception Timer B0 Timer B1 Timer B2 Timer B3 Timer B4 INT5 INT4 INT3 Interrupt enable flag (I flag) INT2 Instruction fetch Address match Watchdog timer DBC Processor interrupt priority level (IPL) INT1 INT0 Timer B5 UART2 transmission/NACK UART2 reception/ACK UART3 transmission/NACK UART3 reception/ACK UART4 transmission/NACK UART4 reception/ACK Bus collision/start, stop condition(UART2) Bus collision/start, stop condition/fault error (UART3) Bus collision/start, stop condition/fault error (UART4) A/D conversion Key input interrupt Stop/wait return interrupt level (RLVL) Interrupt request priority detection results output (to clock generation circuit) Interrupt request accepted. To CPU Low Priority of peripheral I/O interrupts (if priority levels are same) NMI Reset Figure 9.8 Interrupt resolution circuit Rev.1.00 Aug. 02, 2005 Page 70 REJ09B0187-0100 of 329 M16C/80 Group 9. Interrupt Outline ______ 9.18 INT Interrupts ________ ________ INT0 to INT5 are external input interrupts. The level sense/edge sense switching bits of the interrupt control register select the input signal level and edge at which the interrupt can be set to occur on input signal level and input signal edge. The polarity bit selects the polarity. With the external interrupt input edge sense, the interrupt can be set to occur on both rising and falling edges by setting the INTi interrupt polarity switch bit of the interrupt request select register (address 031F16) to "1". When you select both edges, set the polarity switch bit of the corresponding interrupt control register to the falling edge ("0"). When you select level sense, the INTi interrupt polarity switch bit of the interrupt request select register (address 031F16) to "0". Figure 9.9 shows the interrupt request select register. Interrupt request cause select register b7 b6 b5 b4 b3 b2 b1 b0 Symbol IFSR Bit symbol Address 031F16 Bit name When reset XX0000002 Fumction 0 : One edge 1 : Two edges 0 : One edge 1 : Two edges 0 : One edge 1 : Two edges 0 : One edge 1 : Two edges 0 : One edge 1 : Two edges 0 : One edge 1 : Two edges RW IFSR0 IFSR1 IFSR2 IFSR3 IFSR4 IFSR5 INT0 interrupt polarity swiching bit (Note) INT1 interrupt polarity swiching bit (Note) INT2 interrupt polarity swiching bit (Note) INT3 interrupt polarity swiching bit (Note) INT4 interrupt polarity swiching bit (Note) INT5 interrupt polarity swiching bit (Note) Nothing is assigned. When write, set "0". When read, their contents are indeterminate. Note :When level sense is selected, set this bit to "0". Figure 9.9 Interrupt request cause select register Rev.1.00 Aug. 02, 2005 Page 71 REJ09B0187-0100 of 329 M16C/80 Group 9. Interrupt Outline ______ 9.19 NMI Interrupt ______ ______ ______ An NMI interrupt is generated when the input to the P85/NMI pin changes from "H" to "L". The NMI interrupt is a non-maskable external interrupt. The pin level can be checked in the port P85 register (bit 5 at address 03C416). This pin cannot be used as a normal port input. Notes: ______ ______ ______ When not intending to use the NMI function, be sure to connect the NMI pin to VCC (pulled-up). The NMI interrupt is non-maskable. Because it cannot be disabled, the pin must be pulled up. 9.20 Key Input Interrupt If the direction register of any of P104 to P107 is set for input and a falling edge is input to that port, a key input interrupt is generated. A key input interrupt can also be used as a key-on wakeup function for cancelling the wait mode or stop mode. However, if you intend to use the key input interrupt, do not use P104 to P107 as A/D input ports. Figure 9.10 shows the block diagram of the key input interrupt. Note that if an "L" level is input to any pin that has not been disabled for input, inputs to the other pins are not detected as an interrupt. Setting the key input interrupt disable bit (bit 7 at address 03AF16) to "1" disables key input interrupts from occurring regardless of the setting in the interrupt control register. When "1" is set in the key input interrupt disable register, there is no input via the port pin even when the direction register is set to input. Port P104-P107 pull-up select bit Pull-up transistor Port P107 direction register Key input interrupt control register (address 009316) key input interrupt disable bit Port P107 direction register P107/KI3 Pull-up transistor P106/KI2 Port P105 direction register Port P106 direction register Interrupt control circuit Pull-up transistor Key input interrupt request P105/KI1 Pull-up transistor P104/KI0 Port P104 direction register Figure 9.10 Block diagram of key input interrupt Rev.1.00 Aug. 02, 2005 Page 72 REJ09B0187-0100 of 329 M16C/80 Group 9. Interrupt Outline 9.21 Address Match Interrupt An address match interrupt is generated when the address match interrupt address register contents match the program counter value. Four address match interrupts can be set, each of which can be enabled and disabled by an address match interrupt enable bit. Address match interrupts are not affected by the interrupt enable flag (I flag) and processor interrupt priority level (IPL). Figure 9.11 shows the address match interrupt-related registers. Set the start address of an instruction to the address match interrupt register. Address match interrupt is not generated when address such as the middle of instruction or table data is set. Address match interrupt enable register b7 b6 b5 b4 b3 b2 b1 b0 Symbol AIER Bit symbol Address 000916 Bit name Address match interrupt 0 enable bit Address match interrupt 1 enable bit Address match interrupt 2 enable bit Address match interrupt 3 enable bit When reset XXXX00002 Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled RW AIER0 AIER1 AIER2 AIER3 Nothing is assigned. When write, set "0". When read, their contents are indeterminate. Address match interrupt register i (i = 0 ot 3) (b23) b7 (b16)(b15) b0 b7 (b8) b0 b7 b0 Symbol RMAD0 RMAD1 RMAD2 RMAD3 Address 001216 to 001016 001616 to 001416 001A16 to 001816 001E16 to 001C16 When reset 00000016 00000016 00000016 00000016 RW Function Address setting register for address match interrupt Values that can be set 00000016 to FFFFFF16 Figure 9.11 Address match interrupt-related registers Rev.1.00 Aug. 02, 2005 Page 73 REJ09B0187-0100 of 329 M16C/80 Group 9. Interrupt Outline 9.22 Precautions for Interrupts (1) Reading addresses 00000016 and 00000216 * When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence from address 00000016. When high-speed interrupt is occurred, CPU read from address 00000216. The interrupt request bit of the certain interrupt will then be set to "0". However, reading addresses 00000016 and 00000216 by software does not set request bit to "0". (2) Setting the stack pointer * The value of the stack pointer immediately after reset is initialized to 00000016. Accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in _______ the stack pointer before accepting an interrupt. When using the NMI interrupt, initialize the stack point _______ at the beginning of a program. Any interrupt including the NMI interrupt is generated immediately after executing the first instruction after reset. Set an even address to the stack pointer so that the operating efficiency of accessign memory is increased. _______ (3) The NMI interrupt _______ * As for the NMI interrupt pin, an interrupt cannot be disabled. Connect it to the Vcc pin via a resistance (pull-up) if unused. Be sure to work on it. _______ * The NMI pin also serves as P85, which is exclusively input. Reading the contents of the P8 register allows reading the pin value. Use the reading of this pin only for establishing the pin level at the time _______ when the NMI interrupt is input. ______ * Signals input to the NMI pin require "L" level and "H" level of 2 clock + 300ns or more, from the operation clock of CPU. (4) External interrupt * Edge sense Either an "L" level or an "H" level of at least 250 ns width is necessary for the signal input to pins INT0 to INT5 regardless of the CPU operation clock. * Level sense Either an "L" level or an "H" level of 1 cycle of BCLK + at least 200 ns width is necessary for the signal input to pins INT0 to INT5 regardless of the CPU operation clock. (When XIN=20MHz and no division mode, at least 250 ns width is necessary.) * When the polarity of the INT0 to INT5 pins is changed, the interrupt request bit is sometimes set to "1". After changing the polarity, set the interrupt request bit to "0". Figure 9.12 shows the procedure for ______ changing the INT interrupt generate factor. Rev.1.00 Aug. 02, 2005 Page 74 REJ09B0187-0100 of 329 M16C/80 Group 9. Interrupt Outline Set the interrupt priority level to level 0 (Disable INT interrupt) Set the polarity select bit Clear the interrupt request bit to "0" Set the interrupt priority level to level 1 to 7 (Enable the accepting of INT interrupt request) ______ Figure 9.12 Switching condition of INT interrupt request (5) Rewrite the interrupt control register * When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been generated. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : AND, OR, BCLR, BSET * When attempting to clear the interrupt request bit of an interrupt control register, the interrupt request bit is not cleared sometimes. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : MOV (6) Address match interrupt * Do not set the following addresses to the address match interrupt register. 1. The address of the starting instruction in an interrupt routine. 2. Any of the next 7 instructions addresses immediately after an instruction to clear an interrupt request bit of an interrupt control register or an instruction to rewrite an interrupt priority level to a smaller value. 3. Any of the next 3 instructions addresses immediately after an instruction to set the interrupt enable flag (I flag). 4. Any of the next 3 instructions addresses immediately after an instruction to rewrite a processor interrupt priority level (IPL) to a smaller value. Rev.1.00 Aug. 02, 2005 Page 75 REJ09B0187-0100 of 329 M16C/80 Group 9. Interrupt Outline Example 1) Interrupt_A: ; Interrupt A routine pushm R0,R1,R2,R3,A0,A1 ; <---- Do not set address match interrupt to the start address of an interrupt instruction **** ; Example 2) mov.b #0,TA0IC ;Change TA0 interrupt priority level to a smaller value nop ; 1st instruction nop ; 2nd instruction nop ; 3rd instruction Do not set address match interrupt nop ; 4th instruction during this period nop ; 5th instruction nop ; 6th instruction nop ; 7th instruction Example 3) fset I nop nop nop Example 4) ldipl #0 nop nop nop ; ; ; ; ; ; ; ; Set I flag ( interrupt enabled) 1st instruction Do not set address match interrupt 2nd instruction during this period 3rd instruction Rewrite IPL to a smaller value 1st instruction Do not set address match interrupt 2nd instruction during this period 3rd instruction * To return from an interrupt to the address set in an address match interrupt register using return instruction (reit or freit) To rewrite the interrupt control register within the interrupt routine, add the below processing to the end of the routine (immediately before the reit or freit instruction). Also, if multiple interrupts are enabled with other interrupts, add the below processing to the end of the interrupt that enables the multiple interrupts. If the interrupt control register is being rewritten within the non-maskable interrupt routine, add the below processing to the end of all interrupts. Additional process fclr U pushm R0 mov.w 6[SP],R0 ldc R0,FLG popm R0 nop reit ; ; ; ; ; ; ; ; ; Execute after the register reset instruction (popm instruction) Select ISP (Unnecessary if the ISP has been selected) Store R0 register Read FLG on stack (use "stc SVF,R0" when high-speed interrupt) Set in FLG Restore R0 register Dummy Interrupt completed (use freit when high-speed interrupt) Rev.1.00 Aug. 02, 2005 Page 76 REJ09B0187-0100 of 329 M16C/80 Group 9. Interrupt Outline Example 5) If rewriting the interrupt control register for interrupt B with the interrupt A routine and enabling multiple interrupts with interrupt C, the above processing is required at the end of the interrupt A and interrupt C routines. Interrupt A routine Interrupt_A: pushm R0,R1,R2,R3,A0,A1 **** bclr 3,TA0IC **** popm R0,R1,R2,R3,A0,A1 fclr U pushm R0 mov.w 6[SP],R0 ldc R0,FLG popm R0 nop reit ; Store registers ; Rewrite interrupt control register of interrupt B ; ; ; ; ; ; ; ; Restore registers Select ISP (Unnecessary if the ISP has been selected) Store R0 register Read FLG on stack Set in FLG Restore R0 register Dummy Interrupt completed Interrupt C routine Interrupt_C: pushm R0,R1,R2,R3,A0,A1 fset I **** **** popm R0,R1,R2,R3,A0,A1 fclr U pushm R0 mov.w 6[SP],R0 ldc R0,FLG popm R0 nop reit ; Store registers ; Multiple interrupt enabled ;Restore registers ; Select ISP (Unnecessary if the ISP has been selected) ; Store R0 register ; Read FLG on stack ; Set in FLG ; Restore R0 register ; Dummy ; Interrupt completed Rev.1.00 Aug. 02, 2005 Page 77 REJ09B0187-0100 of 329 M16C/80 Group 10. Watchdog Timer 10. Watchdog Timer The watchdog timer has the function of detecting when the program is out of control. Therefore, we recommend using the watchdog timer to improve reliability of a system. The watchdog timer is a 15-bit counter which down-counts the clock derived by dividing the BCLK using the prescaler. Whether a watchdog timer interrupt is generated or reset is selected when an underflow occurs in the watchdog timer. Watchdog timer interrupt is selected when bit 6 of the system control register 0 (address 000816 :CM06) is "0" and reset is selected when CM06 is "1". No value other than "1" can be written in CM06. Once when reset is selected (CM06="1"), watchdog timer interrupt cannot be selected by software. When XIN is selected for the BCLK, bit 7 of the watchdog timer control register (address 000F16) selects the prescaler division ratio (by 16 or by 128). When XCIN is selected as the BCLK, the prescaler is set for division by 2 regardless of bit 7 of the watchdog timer control register (address 000F16). Therefore, the watchdog timer cycle can be calculated as follows. However, errors can arise in the watchdog timer cycle due to the prescaler. When XIN is selected in BCLK Watchdog timer cycle = When XCIN is selected in BCLK Watchdog timer cycle = Prescaler division ratio (2) x watchdog timer count (32768) BCLK Prescaler division ratio (16 or 128) x watchdog timer count (32768) BCLK For example, when BCLK is 20MHz and the prescaler division ratio is set to 16, the monitor timer cycle is approximately 26.2 ms. The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by writing to the watchdog timer start register (address 000E16). CM06 is initialized only at reset. After reset, watchdog timer interrupt is selected. The watchdog timer and the prescaler stop in stop mode, wait mode and hold status. After exiting these modes and status, counting starts from the value remained before. In the stop mode, wait mode and hold state, the watchdog timer and prescaler are stopped. Counting is resumed from the held value when the modes or state are released. Figure 10.1 shows the block diagram of the watchdog timer. Figure 10.2 shows the watchdog timer-related registers. Prescaler "CM07 = 0" "WDC7 = 0" "CM06=0" 1/16 BCLK HOLD Watchdog timer interrupt request "CM07 = 0" "WDC7 = 1" 1/128 Watchdog timer "CM06=1" "CM07 = 1" 1/2 Write to the watchdog timer start register (address 000E16) Reset Set to "7FFF16" RESET Figure 10.1 Block diagram of watchdog timer Rev.1.00 Aug. 02, 2005 Page 78 REJ09B0187-0100 of 329 M16C/80 Group 10. Watchdog Timer Watchdog timer control register b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol WDC Bit symbol Address 000F16 Bit name When reset 000XXXXX2 Function RW High-order bit of watchdog timer Reserved bit WDC7 Must always be set to "0" Prescaler select bit 0 : Divided by 16 1 : Divided by 128 Watchdog timer start register b7 b0 Symbol WDTS Address 000E16 When reset Indeterminate RW Function The watchdog timer is initialized and starts counting after a write instruction to this register. The watchdog timer value is always initialized to "7FFF16" regardless of whatever value is written. System clock control register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol CM0 Bit symbol CM00 CM01 CM02 Address 000616 Bit name Clock output function select bit (Note 2) When reset 0816 Function b1 b0 RW 0 0 1 1 0 1 0 1 : : : : I/O port P53 fC output (Note 3) f8 output (Note 3) f32 output (Note 3) WAIT peripheral function clock stop bit 0 : Do not stop peripheral clock in wait mode 1 : Stop peripheral clock in wait mode (Note 10) CM03 CM04 CM05 CM06 CM07 XCIN-XCOUT drive capacity 0 : LOW select bit (Note 4) 1 : HIGH Port XC select bit 0 : I/O port 1 : XCIN-XCOUT generation (Note 11) Main clock (XIN-XOUT) stop bit (Note 5, 6) Watchdog timer function select bit System clock select bit (Note 9) 0 : On 1 : Off (Note 7) 0 : Watchdog timer interrupt 1 : Reset (Note 8) 0 : XIN, XOUT 1 : XCIN, XCOUT Note 1: Set bit 0 of the protect register (address 000A16) to "1" before writing to this register. Note 2: When outputting BCLK (bit 7 of processor mode register 0 is "0"), set these bits to "00". When outputting ALE to P53 (bit 5 and 4 of processor mode register 0 is "01"), set these bits to "00". The port P53 function is not selected even when you set "00" in microprocessor or memory expansion mode and bit 7 of the processor mode register 0 is "1". Note 3: When selecting fC, f8 or f32 in single chip mode, must use P57 as input port. Note 4: Changes to "1" when shifting to stop mode or reset. Note 5: When entering the power saving mode, the main clock is stopped using this bit. To stop the main clock, set system clock stop bit (CM07) to "1" while an oscillation of sub clock is stable. Then set this bit to "1". Note 6: When this bit is "1", XOUT is "H". Also, the internal feedback resistance remains ON, so XIN is pulled up to XOUT ("H" level) via the feedback resistance. Note 7: When the main clock is stopped, the main clock division register (address 000C16) is set to the division by 8 mode. Note 8: When "1" has been set once, "0" cannot be written by software. Note 9: To set CM07 "1" from "0", first set CM04 to "1", and an oscillation of sub clock is stable. Then set CM07. Also, to set CM07 "0" from "1", first set CM05 to "1", and an oscillation of main clock is stable. Then set CM07. Do not rewrite CM04 and CM05 simultaneously. Note 10: fc32 is not included. Note 11: When XcIN-XcOUT is used, set port P86 and P87 to no pull-up resistance with the input port. Figure 10.2 Watchdog timer control and start registers Rev.1.00 Aug. 02, 2005 Page 79 REJ09B0187-0100 of 329 M16C/80 Group 11. DMAC 11. DMAC This microcomputer has four DMAC (direct memory access controller) channels that allow data to be sent to memory without using the CPU. DMAC is a function that to transmit 1 data of a source address (8 bits / 16 bits) to a destination address when transmission request occurs. When using three or more DMAC channels, the register bank 1 register and high-speed interrupt register are used as DMAC registers. If you are using three or more DMAC channels, you cannot, therefore, use high-speed interrupts. The CPU and DMAC use the same data bus, but the DMAC has a higher bus access privilege than the CPU, and because of the use of cycle-steeling, operations are performed at high-speed from the occurrence of a transfer request until one word (16 bits) or 1 byte (8 bits) of data have been sent. Figure 11.1 shows the mapping of registers used by the DMAC. Table 11.1 shows DMAC specifications. Figures 11.2 to 11.5 show the structures of the registers used. As the registers shown in Figure 11.1 is allocated in CPU, use LDC instruction when writing. When writing to DCT2, DCT3, DRC2, DRC3, DMA2 and DMA3, set register bank select flag (B flag) to "1" and use MOV instruction to set R0 to R3, A0 and A1 registers. When writing to DSA2 and DSA3, set register bank select flag (B flag) to "1" and use LDC instruction to set SB and FB registers. DMAC related register DMD0 DMD1 DCT0 DCT1 DRC0 DRC1 DMA0 DMA1 DSA0 DSA1 DRA0 DRA1 DMA0, 1 memory address reload register DMA0, 1 SFR address register DMA0, 1 memory address register DMA0,1 transfer count reload register DMA0, 1 transfer count register DMA mode register 0, 1 When using three or more DMAC channels The register bank 1 is used as a DMAC register DCT2 (R0) DCT3 (R1) DRC2 (R2) DRC3 (R3) DMA2 (A0) DMA3 (A1) DSA2 (SB) DSA3 (FB) DMA2 transfer count register DMA3 transfer count register DMA2 transfer count reload register DMA3 transfer count reload register DMA2 memory address register DMA3 memory address register DMA2 SFR address register DMA3 SFR address register When using three or more DMAC channels The high-speed interrupt register is used as a DMAC register SVF DRA2 (SVP) DRA1 (VCT) Flag save register DMA2 memory address reload register DMA3 memory address reload register When using DMA2 and DMA3, use the CPU registers shown in parentheses. Figure 11.1 Register map using DMAC In addition to writing to the software DMA request bit to start DMAC transfer, the interrupt request signals output from the functions specified in the DMA request factor select bits are also used. However, in contrast to the interrupt requests, repeated DMA requests can be received, regardless of the interrupt flag. (Note, however, that the number of actual transfers may not match the number of transfer requests if the DMA request cycle is shorter than the DMR transfer cycle. For details, see the description of the DMAC request bit.) Rev.1.00 Aug. 02, 2005 Page 80 REJ09B0187-0100 of 329 M16C/80 Group 11. DMAC Table 11.1 DMAC specifications Item Specification No. of channels 4 (cycle steal method) Transfer memory space * From any address in the 16 Mbytes space to a fixed address (16 Mbytes space) * From a fixed address (16 Mbytes space) to any address in the 16 M bytes space Maximum No. of bytes transferred 128 Kbytes (with 16-bit transfers) or 64 Kbytes (with 8-bit transfers) ________ ________ DMA request factors (Note) Falling edge of INT0 to INT3 or both edge Timer A0 to timer A4 interrupt requests Timer B0 to timer B5 interrupt requests UART0 to UART4 transmission and reception interrupt requests A/D conversion interrupt requests Software triggers Channel priority DMA0 > DMA1 > DMA2 > DMA3 (DMA0 is the first priority) Transfer unit 8 bits or 16 bits Transfer address direction forward/fixed (forward direction cannot be specified for both source and destination simultaneously) * Single transfer Transfer ends when the transfer count register is "000016". * Repeat transfer When the transfer counter is "000016", the value in the transfer counter reload register is reloaded into the transfer counter and the DMA transfer is continued DMA interrupt request generation timing When the transfer counter register changes from "000116" to "000016". DMA startup * Single transfer Transfer starts when DMA transfer count register is more than "000116" and the DMA is requested after "012" is written to the channel i transfer mode select bits * Repeat transfer Transfer starts when the DMA is requested after "112" is written to the channel i transfer mode select bits DMA shutdown * Single transfer When "002" is written to the channel i transfer mode select bits and DMA transfer count register becomes "000016" by DMA transfer or write * Repeat transfer When "002" is written to the channel i transfer mode select bits Reload timing When the transfer counter register changes from "000116" to "000016" in repeat transfer mode. Reading / writing the register Registers are always read/write enabled. Number of DMA transfer cycles Between SFR and internal RAM : 3 cycles Between external I/O and external memory : minimum 3 cycles Transfer mode Note: DMA transfer is not effective to any interrupt. Rev.1.00 Aug. 02, 2005 Page 81 REJ09B0187-0100 of 329 M16C/80 Group 11. DMAC DMAi request cause select register (i = 0 to 3)(Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol DMiSL Address 037816 to 037B16 When reset 0X0000002 Function Bit symbol Bit name DMA request cause select bit (Note 2) b4 b3 b2 b1 b0 R W DSEL0 DSEL1 DSEL2 DSEL3 DSEL4 0 0 0 0 0 : Software trigger 0 0 0 0 1 : Falling edge of INTi pin (Note 3) 0 0 0 1 0 : Two edges of INTi pin (Note 3) 0 0 0 1 1 : Timer A0 0 0 1 0 0 : Timer A1 0 0 1 0 1 : Timer A2 0 0 1 1 0 : Timer A3 0 0 1 1 1 : Timer A4 0 1 0 0 0 : Timer B0 0 1 0 0 1 : Timer B1 0 1 0 1 0 : Timer B2 0 1 0 1 1 : Timer B3 0 1 1 0 0 : Timer B4 0 1 1 0 1 : Timer B5 0 1 1 1 0 : UART0 transmit 0 1 1 1 1 : UART0 receive 1 0 0 0 0 : UART1 transmit 1 0 0 0 1 : UART1 receive 1 0 0 1 0 : UART2 transmit 1 0 0 1 1 : UART2 receive/ACK (Note 4) 1 0 1 0 0 : UART3 transmit 1 0 1 0 1 : UART3 receive/ACK (Note 4) 1 0 1 1 0 : UART4 transmit 1 0 1 1 1 : UART4 receive/ACK (Note 4) 1 1 0 0 0 : A/D conversion 1 1 0 0 1 to 1 1 1 1 1 : Inhibit DSR Software DMA request bit (Note 5) If software trigger is selected, a DMA request is generated by setting this bit to "1" (When read, the value of this bit is always "0") Nothing is assigned. When write, set "0". When read, its content is indeterminate. DRQ DMA request bit (Note 5,6) 0 : Not requested 1 : Requested Note 1: Please refer to DMAC precautions. Note 2: Set DMA inhibit before changing the DMA request cause. Set DRQ to "1" simultaneously. e.g.) MOV.B #083h, DMiSL ; Set timer A0 Note 3: DMA0-INT0, DMA1-INT1, DMA2-INT2, and DMA3-INT3 correspond to DMAi and INTi. However, when INT3 pin becomes data bus in microprocessor mode, DMA3INT3 cannot be used. Note 4: UARTi reception and ACK switching are effected using the UARTi special mode register and UARTi special mode register 2. Note 5: When setting DSR to "1", set DRQ to "1" using OR instruction etc. simultaneously. e.g.) OR.B #0A0h, DMiSL Note 6: Do not write "0" to this bit. There is no need to clear the DMA request bit. Figure 11.2 DMAC register (1) Rev.1.00 Aug. 02, 2005 Page 82 REJ09B0187-0100 of 329 M16C/80 Group 11. DMAC DMA mode register 0 (CPU internal register) b7 b6 b5 b4 b3 b2 b1 b0 Symbol DMD0 When reset 0016 Bit symbol Bit name Channel 0 transfer mode select bit b1 b0 Function 0 0 : DMA inhibit 0 1 : Single transfer 1 0 : Reserved 1 1 : Repeat transfer 0 : 8 bits 1 : 16 bits 0 : Fixed address to memory (forward direction) 1 : Memory (forward direction) to fixed address b5 b4 RW MD00 MD01 BW0 RW0 MD10 MD11 BW1 RW1 Channel 0 transfer unit select bit Channel 0 transfer direction select bit Channel 1 transfer mode select bit 0 0 : DMA inhibit 0 1 : Single transfer 1 0 : Reserved 1 1 : Repeat transfer 0 : 8 bits 1 : 16 bits Channel 1 transfer unit select bit Channel 1 transfer 0 : Fixed address to memory (forward direction) direction select bit 1 : Memory (forward direction) to fixed address DMA mode register 1 (CPU internal register) b7 b6 b5 b4 b3 b2 b1 b0 Symbol DMD1 When reset 0016 Bit symbol Bit name b1 b0 Function RW MD20 MD21 BW2 RW2 MD30 MD31 BW3 RW3 Channel 2 transfer 0 0 : DMA inhibit mode select bit 0 1 : Single transfer 1 0 : Reserved 1 1 : Repeat transfer Channel 2 transfer 0 : 8 bits unit select bit 1 : 16 bits Channel 2 transfer 0 : Fixed address to memory (forward direction) direction select bit 1 : Memory (forward direction) to fixed address Channel 3 transfer b5 b4 0 0 : DMA inhibit mode select bit 0 1 : Single transfer 1 0 : Reserved 1 1 : Repeat transfer Channel 3 transfer 0 : 8 bits unit select bit 1 : 16 bits Channel 3 transfer 0 : Fixed address to memory (forward direction) direction select bit 1 : Memory (forward direction) to fixed address Figure 11.3 DMAC register (2) Rev.1.00 Aug. 02, 2005 Page 83 REJ09B0187-0100 of 329 M16C/80 Group 11. DMAC DMAi transfer count register (i = 0 to 3) (CPU internal register) b15 b0 Symbol DCT0 DCT1 DCT2 (bank 1;R0) (Note 1) DCT3 (bank 1;R1) (Note 1) When reset XXXX16 XXXX16 000016 000016 Function * Transfer counter Set transfer number Transfer count specification 000016 to FFFF16 RW Note 1: When setting DCT2 and DCT3, set "1" to the register bank select flag (B flag) of flag register (FLG), and then set desired value to R0 and R1 of register bank 1. Note 2: When "0" is set to this register, data transfer is not done even if DMA is requested. DMAi transfer count reload register (i = 0 to 3) (CPU internal register) b15 b0 Symbol DRC0 DRC1 DRC2 (bank 1;R2) (Note 1) DRC3 (bank 1;R3) (Note 1) When reset XXXX16 XXXX16 000016 000016 Function * Transfer count register reload value Set transfer number Transfer count specification 000016 to FFFF16 RW Note: When setting DRC2 and DRC3, set "1" to the register bank select flag (B flag) of flag register (FLG), and then set desired value to R2 and R3 of register bank 1. Figure 11.4 DMAC register (3) Rev.1.00 Aug. 02, 2005 Page 84 REJ09B0187-0100 of 329 M16C/80 Group 11. DMAC DMAi memory address register (i = 0 to 3) (CPU internal register) b23 b0 Symbol DMA0 DMA1 DMA2 (bank 1;A0) (Note 1) DMA3 (bank 1;A1) (Note 1) When reset XXXXXX16 XXXXXX16 00000016 00000016 Function * Memory address (Note 2) Set source or destination memory address Transfer address specification area 00000016 to FFFFFF16 (16 Mbytes area) RW Note 1: When setting DMA2 and DMA3, set "1" to the register bank select flag (B flag) of flag register (FLG), and set desired value to A0 and A1 of register bank 1. Note 2: When the transfer direction select bit is "0" (fixed address to memory), this register is destination memory address. When the transfer direction select bit is "1" (memory to fixed address), this register is source memory address. DMAi SFR address register (i = 0 to 3) (CPU internal register) b23 b0 Symbol DSA0 DSA1 DSA2 (bank 1;SB) (Note 1) DSA3 (bank 1;FB) (Note 1) When reset XXXXXX16 XXXXXX16 00000016 00000016 Function * SFR address (Note 2) Set source or destination fixed address Transfer address specification area 00000016 to FFFFFF16 (16 Mbytes area) RW Note 1: When setting DSA2, set "1" to the register bank select flag (B flag) of flag register (FLG), and set desired value to SB of register bank 1. When setting DSA3, set "1" to the register bank select flag (B flag) of flag register (FLG), and set desired value to FB of register bank 1. Note 2: When the transfer direction select bit is "0" (fixed address to memory), this register is source fixed address. When the transfer direction select bit is "1" (memory to fixed address), this register is destination fixed address. DMAi memory address reload register (i = 0 to 3) (CPU internal register) b23 b0 Symbol DRA0 DRA1 DRA2 (SVP) (Note) DRA3 (VCT) (Note) When reset XXXXXX16 XXXXXX16 XXXXXX16 XXXXXX16 Function * Memory address register reload value Set source or destination memory address Transfer address specification area 00000016 to FFFFFF16 (16 Mbytes area) RW Note: When setting DRA2, set desired value to save PC register (SVP). When setting DRA3, set desired value to vector register (VCT). Figure 11.5 DMAC register (4) Rev.1.00 Aug. 02, 2005 Page 85 REJ09B0187-0100 of 329 M16C/80 Group 11. DMAC (1) Transfer cycle The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area (source read) and the bus cycle in which the data is written to memory or to the SFR area (destination write). The number of read and write bus cycles depends on the source and destination addresses. In memory expansion mode and microprocessor mode, the number of read and write bus cycles also depends on the level of the BYTE pin. Also, the bus cycle itself is longer when software waits are inserted. (a) Effect of source and destination addresses When 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd addresses, there are one more source read cycle and destination write cycle than when the source and destination both start at even addresses. (b) Effect of external data bus width control register When in memory expansion mode or microprocessor mode, the transfer cycle changes according to the data bus width at the source and destination. 1. When transferring 16 bits of data and the data bus width at the source and at the destination is 8 bits (data bus width bit = "0"), there are two 8-bit data transfers. Therefore, two bus cycles are required for reading and two cycles for writing. 2. When transferring 16 bits of data and the data bus width at the source is 8 bits (data bus width bit = "0") and the data bus width at the destination is 16 bits (data bus width bit = "1"), the data is read in two 8-bit blocks and written as 16-bit data. Therefore, two bus cycles are required for reading and one cycle for writing. 3. When transferring 16 bits of data and the data bus width at the source is 16 bits (data bus width bit = "1") and the data bus width at the destination is 8 bits (data bus width bit = "0"), 16 bits of data are read and written as two 8-bit blocks. Therefore, one bus cycle is required for reading and two cycles for writing. (c) Effect of software wait When the SFR area or a memory area with a software wait is accessed, the number of cycles is increased for the wait by 1 bus cycle. The length of the cycle is determined by BCLK. Figure 11.6 shows the example of the transfer cycles for a source read. Figure 11.6 shows the destination is external area, the destination write cycle is shown as two cycle (one bus cycle) and the source read cycles for the different conditions. In reality, the destination write cycle is subject to the same conditions as the source read cycle, with the transfer cycle changing accordingly. When calculating the transfer cycle, remember to apply the respective conditions to both the destination write cycle and the source read cycle. For example (2) in Figure 11.6, if data is being transferred in 16-bit units on an 8-bit bus, two bus cycles are required for both the source read cycle and the destination write cycle. Rev.1.00 Aug. 02, 2005 Page 86 REJ09B0187-0100 of 329 M16C/80 Group 11. DMAC (1) *When 8-bit data is transferred *When 16-bit data is transferred on a 16-bit data bus and the source address is even BCLK Address bus RD signal WR signal Data bus CPU use Source Destination CPU use CPU use Source Destination CPU use (2) *When 16-bit data is transferred and the source address is odd *When 16-bit data is transferred and the width of data bus at the source is 8-bit (When the width of data bus at the destination is 8-bit, there are also two destination write cycles). BCLK Address bus RD signal WR signal Data bus CPU use Source Source + 1 Destination CPU use CPU use Source Source + 1 Destination CPU use (3) *When one wait is inserted into the source read under the conditions in (1) BCLK Address bus RD signal WR signal Data bus CPU use Source Destination CPU use CPU use Source Destination CPU use (4) *When one wait is inserted into the source read under the conditions in (2) (When 16-bit data is transferred and the width of data but at the destination is 8-bit, there are two destination write cycles). BCLK Address bus RD signal WR signal Data bus CPU use Source Source + 1 Destination CPU use CPU use Source Source + 1 Destination CPU use Note: The same timing changes occur with the respective conditions at the destination as at the source. Figure 11.6 Example of the transfer cycles for a source read Rev.1.00 Aug. 02, 2005 Page 87 REJ09B0187-0100 of 329 M16C/80 Group 11. DMAC (2) DMAC transfer cycles Any combination of even or odd transfer read and write addresses is possible. Table 11.2 shows the number of DMAC transfer cycles. The number of DMAC transfer cycles can be calculated as follows: No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k Table 11.2 No. of DMAC transfer cycles Transfer unit Bus width Access address Memory expansion mode Microprocessor mode No. of read No. of write No. of read No. of write cycles cycles cycles cycles 1 1 1 1 1 1 1 1 -- -- 1 1 -- -- 1 1 1 1 1 1 2 2 2 2 -- -- 2 2 -- -- 2 2 Single-chip mode 8-bit transfers (BWi = "0") 16-bit transfers (BWi = "1") 16-bit (DSi = "1") 8-bit (DSi = "0") 16-bit (DSi = "1") 8-bit (DSi = "0") Even Odd Even Odd Even Odd Even Odd Coefficient j, k Internal Memory Internal ROM/RAM SFR area No wait With wait j=1 j=2 j=2 k=1 k=2 k=2 No wait j=1 k=2 External Memory Separate bus Multiplex bus One wait Two waits Three waits Two waits Three waits j=2 j=3 j=4 j=3 j=4 k=2 k=3 k=4 k=3 k=4 DMA Request Bit The DMAC can issue DMA requests using preselected DMA request factors for each channel as triggers. The DMA transfer request factors include the reception of DMA request signals from the internal peripheral functions, software DMA factors generated by the program, and external factors using input from external interrupt signals. See the description of the DMAi factor selection register for details of how to select DMA request factors. DMA requests are received as DMA requests when the DMAi request bit is set to "1" and the channel i transfer mode select bits are "01" or "11". Therefore, even if the DMAi request bit is "1", no DMA request is received if the channel i transfer mode select bit is "00". In this case, DMAi request bit is cleared. Because the channel i transfer mode select bits default to "00" after a reset, remember to set the channel i transfer mode select bit for the channel to be activated after setting the DMAC related registers. This enables receipt of the DMA requests for that channel, and DMA transfers are then performed when the DMAi request bit is set. The following describes when the DMAi request bit is set and cleared. Rev.1.00 Aug. 02, 2005 Page 88 REJ09B0187-0100 of 329 M16C/80 Group 11. DMAC (1) Internal factors The DMAi request flag is set to "1" in response to internal factors at the same time as the interrupt request bit of the interrupt control register for each factor is set. This is because, except for software trigger DMA factors, they use the interrupt request signals output by each function. The DMAi request bit is cleared to "0" when the DMA transfer starts or the DMA transfer is in disable state (channel i transfer mode select bits are "00" and the DMAi transfer count register is "0"). (2) External factors ______ These are DMA request factors that are generated by the input edge from the INTi pin (where i indi______ cates the DMAC channel). When the INTi pin is selected by the DMAi request factor select bit as an external factor, the inputs from these pins become the DMA request signals. When an external factor is selected, the DMAi request bit is set, according to the function specified in the ______ DMA request factor select bit, on either the falling edge of the signal input via the INTi pins, or both edges. When an external factor is selected, the DMAi request bit is cleared, in the same way as the DMAi request bit is cleared for internal factors, when the DMA transfer starts or the DMA transfer is in disable state. (3) Relationship between external factor request input and DMAi request flag, and DMA transfer timing When the request inputs to DMAi occur in the same sampling cycle (between the falling edge of BCLK and the next falling edge), the DMAi request bits are set simultaneously, but if the DMAi enable bits are all set, DMA0 takes priority and the transfer starts. When one transfer unit is complete, the bus privilege is returned to the CPU. When the CPU has completed one bus access, DMA1 transfer starts, and, when one transfer unit is complete, the privilege is again returned to the CPU. The priority is as follows: DMA0 > DMA1 > DMA2 > DMA3. Figure 11.7. DMA transfer example by external factors shows what happens when DMA0 and DMA1 requests occur in the same sampling cycle. In this example, DMA transfer request signals are input simultaneously from external factors and the DMA transfers are executed in the minimum cycles. BCLK DMA0 DMA1 CPU INT0 DMA0 request bit INT1 DMA1 request bit Bus priviledge acquired Figure 11.7 DMA transfer example by external factors Rev.1.00 Aug. 02, 2005 Page 89 REJ09B0187-0100 of 329 M16C/80 Group 11. DMAC Precautions for DMAC (1) Do not clear the DMA request bit of the DMAi request cause select register. In M16C/80, when a DMA request is generated while the channel is disabled (Note), the DMA transfer is not executed and the DMA request bit is cleared automatically. Note :The DMA is disabled or the transfer count register is "0". (2) When DMA transfer is done by a software trigger, set DSR and DRQ of the DMAi request cause select register to "1" simultaneously using the OR instruction. e.g.) OR.B #0A0h, DMiSL ; DMiSL is DMAi request cause select register (3) When changing the DMAi request cause select bit of the DMAi request cause select register, set "1" to the DMA request bit, simultaneously. In this case, set the corresponding DMA channel to disabled before changing the DMAi request cause select bit. At least 26 cycles are needed from the instruction to write to the DMAi request cause select register to enable DMA. Example) When DMA request cause is changed to timer A0 and using DMA0 in single transfer after DMA initial setting push.w R0 ; Store R0 register stc DMD0, R0 ; Read DMA mode register 0 and.b #11111100b, R0L ; Clear DMA0 transfer mode select bit to "00" ldc R0, DMD0 ; DMA0 disabled mov.b #10000011b, DM0SL ; Select timer A0 ; (Write "1" to DMA request bit simultaneously) push.w R0 ; Store R0 register mov.w #6,R0 ; dummy_loop: At least 26 cycles are needed sbjnz.w #1,R0,dummy_loop ; Dummy cycle until DMA enabled. pop.w R0 ; Restore R0 register or.b #00000001b, R0L ; Set DMA0 single transfer ldc R0, DMD0 ; DMA0 enabled pop.w R0 ; Restore R0 register (4) Recommended procedure for starting DMA transfer *When writing to the DMAi request cause register including overwriting the same value to the DMAi request cause register; 1. Disable the corresponding channel i DMA in DMA mode registers 0 and 1. 2. Set up the peripheral used as the source of the DMA transfer. However, the peripheral should remain disabled at this time. For example, when using UART0 transmit, disable UART0 transmit. 3. Set the DMAi request cause select register. At this time, write a '1' to the DMA request bit (bit 7) Rev.1.00 Aug. 02, 2005 Page 90 REJ09B0187-0100 of 329 M16C/80 Group 11. DMAC 4. Set the following SFR registers: *DMAiSFR address register *DMAI memory address reload register *DMAi memory address register *DMAi transfer count reload register *DMAi transfer count register 5. At this point, if the number of elapsed cycles are less than 26, add code (NOP's or other processing) to make up some time. 6. Enable the corresponding channel i DMA in the DMA mode registers 0 and 1. 7. Enable the peripheral used as the source of the DMA transfer. For example, when using UART0 transmit, enable UART0 transmit. *When not writing to the DMAi request cause register; 1. Disable the corresponding channel i DMA in the DMA mode registers 0 and 1. 2. Set up the peripheral used as the source of the DMA transfer. However, the peripheral should remain disabled at this time. For example, when using UART0 transmit, disable UART0 transmit. 3. Set up the following SFR registers: *DMAiSFR address register *DMAI memory address reload register *DMAi memory address register *DMAi transfer count reload register *DMAi transfer count register 4. Enable the corresponding channel i DMA in the DMA mode registers 0 and 1. 5. Enable the peripheral used as the source of the DMA transfer. For example, when using UART0 transmit, enable UART0 transmit. (5) Recommended procedure after completing DMA transfer *Disable the peripheral used as source of the DMA transfer to prevent generating a DMA request. *Disable the corresponding channel i DMA in the DMA mode registers 0 and 1. Rev.1.00 Aug. 02, 2005 Page 91 REJ09B0187-0100 of 329 M16C/80 Group 12. Timer 12. Timer There are eleven 16-bit timers. These timers can be classified by function into timers A (five) and timers B (six). All these timers function independently. Count source for each timer becomes an operation clock for timer operation as counting and reloading, etc. Figures 12.1 and 12.2 show the block diagram of timers. Clock prescaler XIN 1/8 1/4 f1 f8 f32 fC32 f1 f8 f32 XCIN Clock prescaler reset flag (bit 7 at address 034116) set to "1" 1/32 Reset fC32 * Timer mode * One-shot timer mode * PWM mode Timer A0 interrupt TA0IN Noise filter Timer A0 * Event counter mode * Timer mode * One-shot timer mode * PWM mode Timer A1 interrupt TA1IN Noise filter Timer A1 * Event counter mode * Timer mode * One-shot timer mode * PWM mode Timer A2 interrupt TA2IN Noise filter Timer A2 * Event counter mode * Timer mode * One-shot timer mode * PWM mode Timer A3 interrupt TA3IN Noise filter Timer A3 * Event counter mode * Timer mode * One-shot timer mode * PWM mode Timer A4 interrupt TA4IN Noise filter Timer A4 * Event counter mode Timer B2 overflow Figure 12.1 Timer A block diagram Rev.1.00 Aug. 02, 2005 Page 92 REJ09B0187-0100 of 329 M16C/80 Group 12. Timer Clock prescaler XIN 1/8 1/4 f1 f8 f32 fC32 Timer B2 overflow (to timer A count source) f1 f8 f32 XCIN Clock prescaler reset flag (bit 7 at address 034116) set to "1" 1/32 Reset fC32 * Timer mode * Pulse width measuring mode TB0IN Noise filter Timer B0 interrupt Timer B0 * Event counter mode * Timer mode * Pulse width measuring mode Timer B1 interrupt TB1IN Noise filter Timer B1 * Event counter mode * Timer mode * Pulse width measuring mode Timer B2 interrupt TB2IN Noise filter Timer B2 * Event counter mode * Timer mode * Pulse width measuring mode TB3IN Noise filter Timer B3 interrupt Timer B3 * Event counter mode * Timer mode * Pulse width measuring mode Timer B4 interrupt TB4IN Noise filter Timer B4 * Event counter mode * Timer mode * Pulse width measuring mode Timer B5 interrupt TB5IN Noise filter Timer B5 * Event counter mode Figure 12.2 Timer B block diagram Rev.1.00 Aug. 02, 2005 Page 93 REJ09B0187-0100 of 329 M16C/80 Group 13. Timer A 13. Timer A Figure 13.1 shows the block diagram of timer A. Figures 13.2 to 13.4 show the timer A-related registers. Except in event counter mode, timers A0 through A4 all have the same function. Use the timer Ai mode register (i = 0 to 4) bits 0 and 1 to choose the desired mode. Timer A has the four operation modes listed as follows: * Timer mode: The timer counts an internal count source. * Event counter mode: The timer counts pulses from an external source or a timer over flow. * One-shot timer mode: The timer stops counting when the count reaches "000016". * Pulse width modulation (PWM) mode: The timer outputs pulses of a given width. Data bus high-order bits Clock source selection f1 f8 f32 fC32 Polarity selection TAiIN (i = 0 to 4) * Timer * One shot * PWM * Timer (gate function) * Event counter Data bus low-order bits Low-order 8 bits Reload register (16) High-order 8 bits Counter (16) Clock selection Up count/down count Always down count except in event counter mode TAi Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Addresses 034716 034616 034916 034816 034B16 034A16 034D16 034C16 034F16 034E16 TAj Timer A4 Timer A0 Timer A1 Timer A2 Timer A3 TAk Timer A1 Timer A2 Timer A3 Timer A4 Timer A0 Count start flag (Address 034016) Down count External trigger TB2 overflow TAj overflow (j = i - 1. Note, however, that j = 4 when i = 0) Up/down flag (Address 034416) TAk overflow (k = i + 1. Note, however, that k = 0 when i = 4) TAiOUT (i = 0 to 4) Pulse output Toggle flip-flop Figure 13.1 Block diagram of timer A Timer Ai mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TAiMR(i=0 to 4) Address When reset 035616 to 035A16 00000X002 Bit symbol TMOD0 Bit name Operation mode select bit b1 b0 Function 0 0 : Timer mode 0 1 : Event counter mode 1 0 : One-shot timer mode 1 1 : Pulse width modulation (PWM) mode RW TMOD1 MR0 MR1 MR2 MR3 TCK0 TCK1 This bit is invalid in M16C/80 series. Port output control is set by the function select registers A and B. -- Function varies with each operation mode Count source select bit (Function varies with each operation mode) Figure 13.2 Timer A-related registers (1) Rev.1.00 Aug. 02, 2005 Page 94 REJ09B0187-0100 of 329 M16C/80 Group 13. Timer A Timer Ai register (Note 1) (b15) b7 (b8) b0b7 b0 Symbol TA0 TA1 TA2 TA3 TA4 Function Address 034716,034616 034916,034816 034B16,034A16 034D16,034C16 034F16,034E16 When reset Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Values that can be set RW * Timer mode Counts an internal count source * Event counter mode Counts pulses from an external source or timer overflow * One-shot timer mode (Note 2, 3) Counts a one shot width * Pulse width modulation mode (16-bit PWM) (Note 2, 4) Functions as a 16-bit pulse width modulator * Pulse width modulation mode (8-bit PWM) (Note 2, 4) Timer low-order address functions as an 8-bit prescaler and high-order address functions as an 8-bit pulse width modulator 000016 to FFFF16 000016 to FFFF16 000016 to FFFF16 000016 to FFFE16 0016 to FE16 (High-order address) 0016 to FF16 (Low-order address) Note 1: Read and write data in 16-bit units. Note 2: Use MOV instruction to write to this register. Note 3: When the timer Ai register is set to "000016", the counter does not operate and the timer Ai interrupt request is not generated. When the pulse is set to output, the pulse does not output from the TAiOUT pin. Note 4: When the timer Ai register is set to "000016", the pulse width modulator does not operate and the output level of the TAiOUT pin remains "L" level, therefore the timer Ai interrupt request is not generated. This also occurs in the 8-bit pulse width modulator mode when the significant 8 high-order bits in the timer Ai register are set to "0016". Count start flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol TABSR Address 034016 When reset 0016 Bit symbol TA0S TA1S TA2S TA3S TA4S TB0S TB1S TB2S Bit name Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Timer B0 count start flag Timer B1 count start flag Timer B2 count start flag Function 0 : Stops counting 1 : Starts counting RW Up/down flag (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol UDF Address 034416 When reset 0016 Bit symbol TA0UD TA1UD TA2UD TA3UD TA4UD TA2P TA3P TA4P Bit name Timer A0 up/down flag Timer A1 up/down flag Timer A2 up/down flag Timer A3 up/down flag Timer A4 up/down flag Timer A2 two-phase pulse signal processing select bit Timer A3 two-phase pulse signal processing select bit Timer A4 two-phase pulse signal processing select bit Function 0 : Down count 1 : Up count This specification becomes valid when the up/down flag content is selected for up/down switching cause 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing enabled (Note 2) When not using the two-phase pulse signal processing function, set the select bit to "0" RW Note 1: Use MOV instruction to write to this register. Note 2: Set the corresponding port function select register A to I/O port, and port direction register to "0". Figure 13.3 Timer A-related registers (2) Rev.1.00 Aug. 02, 2005 Page 95 REJ09B0187-0100 of 329 M16C/80 Group 13. Timer A One-shot start flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol ONSF Address 034216 When reset 0016 Bit symbol TA0OS TA1OS TA2OS TA3OS TA4OS TAZIE Bit name Timer A0 one-shot start flag Timer A1 one-shot start flag Timer A2 one-shot start flag Timer A3 one-shot start flag Timer A4 one-shot start flag Z phase input enable bit Timer A0 event/trigger select bit 0 : Invalid 1 : Valid b7 b6 Function 1 : Timer start When read, the value is "0" RW TA0TGL TA0TGH 0 0 : Input on TA0IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA4 overflow is selected 1 1 : TA1 overflow is selected Note: Set the corresponding function select register A to I/O port, and port direction register to "0". Trigger select register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRGSR Address 034316 When reset 0016 Bit symbol TA1TGL Bit name Timer A1 event/trigger select bit Function b1 b0 RW TA1TGH TA2TGL 0 0 : Input on TA1IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA0 overflow is selected 1 1 : TA2 overflow is selected b3 b2 Timer A2 event/trigger select bit TA2TGH TA3TGL TA3TGH 0 0 : Input on TA2IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA1 overflow is selected 1 1 : TA3 overflow is selected b5 b4 Timer A3 event/trigger select bit 0 0 : Input on TA3IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA2 overflow is selected 1 1 : TA4 overflow is selected b7 b6 TA4TGL TA4TGH Timer A4 event/trigger select bit 0 0 : Input on TA4IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA3 overflow is selected 1 1 : TA0 overflow is selected Note: Set the corresponding function select register A to I/O port, and port direction register to "0". Clock prescaler reset flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol CPSRF Address 034116 When reset 0XXXXXXX2 Bit symbol Bit name Function RW Nothing is assigned. When write, set "0". When read, their contents are indeterminate. CPSR Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is "0") Figure 13.4 Timer A-related registers (3) Rev.1.00 Aug. 02, 2005 Page 96 REJ09B0187-0100 of 329 M16C/80 Group 13. Timer A (1) Timer mode In this mode, the timer counts an internally generated count source. (See Table 13.1) Figure 13.5 shows the timer Ai mode register in timer mode. Table 13.1 Specifications of timer mode Item Specification Count source f1, f8, f32, fc32 Count operation * Down count * When the timer underflows, it reloads the reload register contents before continuing counting Divide ratio 1/(n+1) n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing When the timer underflows TAiIN pin function Programmable I/O port or gate input Programmable I/O port or pulse output (Setting by the corresponding function TAiOUT pin function select registers A and B) Read from timer Count value can be read out by reading timer Ai register Write to timer * When not counting Value written to timer Ai register is written to both reload register and counter * When counting Value written to timer Ai register is written to only reload register (Transferred to counter at next reload time) Select function * Gate function Counting can be started and stopped by the TAiIN pin's input signal * Pulse output function Each time the timer underflows, the TAiOUT pin's polarity is reversed Timer Ai mode register b7 b6 b5 b4 b3 b2 b1 b0 0 00 Symbol TAiMR(i=0 to 4) Bit symbol TMOD0 TMOD1 MR0 MR1 Address When reset 035616 to 035A16 00000X002 Bit name Function b1 b0 RW Operation mode select bit 0 0 : Timer mode This bit is invalid in M16C/80 series. Port output control is set by the function select registers A and B. Gate function select bit b4 b3 -- 0 X (Note 1): Gate function not available (TAiIN pin is a normal port pin) MR2 1 0 : Timer counts only when TAiIN pin is held "L" (Note 2) 1 1 : Timer counts only when TAiIN pin is held "H" (Note 2) 0 (Set to "0" in timer mode) Count source select bit b7 b6 MR3 TCK0 TCK1 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 Note 1: The bit can be "0" or "1". Note 2: Set the corresponding port function select register to I/O port, and port direction register to "0". Figure 13.5 Timer Ai mode register in timer mode Rev.1.00 Aug. 02, 2005 Page 97 REJ09B0187-0100 of 329 M16C/80 Group 13. Timer A (2) Event counter mode In this mode, the timer counts an external signal or an internal timer's overflow. Timers A0 and A1 can count a singlephase external signal. Timers A2, A3, and A4 can count a single-phase and a two-phase external signal. Table 13.2 lists timer specifications when counting a single-phase external signal. Figure 13.6 shows the timer Ai mode register in event counter mode. Table 13.3 lists timer specifications when counting a two-phase external signal. Figure 13.7 shows the timer Ai mode register in event counter mode. Table 13.2 Timer specifications in event counter mode (when not processing two-phase pulse signal) Item Specification Count source * External signals input to TAiIN pin (effective edge can be selected by software) * TB2 overflows or underflows, TAj overflows or underflows Count operation * Up count or down count can be selected by external signal or software * When the timer overflows or underflows, it reloads the reload register con tents before continuing counting (Note) Divide ratio * 1/ (FFFF16 - n + 1) for up count * 1/ (n + 1) for down count n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing The timer overflows or underflows TAiIN pin function Programmable I/O port or count source input Programmable I/O port, pulse output, or up/down count select input (Setting by TAiOUT pin function the corresponding function select registers A and B) Read from timer Count value can be read out by reading timer Ai register Write to timer * When not counting Value written to timer Ai register is written to both reload register and counter * When counting Value written to timer Ai register is written to only reload register (Transferred to counter at next reload time) Select function * Free-run count function Even when the timer overflows or underflows, the reload register content is not reloaded to it * Pulse output function Each time the timer overflows or underflows, the TAiOUT pin's polarity is reversed Note: This does not apply when the free-run function is selected. Timer Ai mode register (When not using two-phase pulse signal processing) b7 b6 b5 b4 b3 b2 b1 b0 0 0 1 Symbol TAiMR(i=0 to 4) Bit symbol TMOD0 TMOD1 MR0 MR1 MR2 MR3 TCK0 TCK1 Address When reset 035616 to 035A16 00000X002 Bit name Function b1 b0 RW Operation mode select bit 0 1 : Event counter mode This bit is invalid in M16C/80 series. Port output control is set by the function select registers A and B. Count polarity select bit (Note 1) Up/down switching cause select bit 0 : Counts external signal's falling edges 1 : Counts external signal's rising edges 0 : Up/down flag's content 1 : TAiOUT pin's input signal (Note 2) -- 0 : (Set to "0" in event counter mode) Count operation type select bit Two-phase pulse signal processing operation select bit 0 : Reload type 1 : Free-run type When not using two-phase pulse signal processing, set this bit to "0" Note 1: This bit is valid when only counting an external signal. Note 2: Set the corresponding function select register A to I/O port, and port direction register to "0". Figure 13.6 Timer Ai mode register in event counter mode Rev.1.00 Aug. 02, 2005 Page 98 REJ09B0187-0100 of 329 M16C/80 Group 13. Timer A Table 13.3 Timer specifications in event counter mode (when processing two-phase pulse signal with timers A2, A3, and A4) Item Specification Count source * Two-phase pulse signals input to TAiIN or TAiOUT pins (i=2 to 4) Count operation * Up count or down count can be selected by two-phase pulse signal * When the timer overflows or underflows, the reload register content is reloaded and the timer starts over again (Note) Divide ratio * 1/ (FFFF16 - n + 1) for up count * 1/ (n + 1) for down count n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing Timer overflows or underflows TAiIN pin function Two-phase pulse input (Set the corresponding function select registers A to I/ O port, and port direction register to "0") TAiOUT pin function Two-phase pulse input (Set the corresponding function select registers A to I/ O port, and port direction register to "0") Read from timer Write to timer Count value can be read out by reading timer A2, A3, or A4 register * When not counting Value written to timer Ai register is written to both reload register and counter * When counting Value written to timer Ai register is written to only reload register (Transferred to counter at next reload time) * Normal processing operation (TimerA2 and timer A3) The timer counts up rising edges or counts down falling edges on the TAiIN pin when input signal on the TAiOUT pin is "H" Select function (Note 2) TAiOUT TAiIN (i=2,3) Up count Up count Up count Down count Down count Down count * Multiply-by-4 processing operation (TimerA3 and timer A4) If the phase relationship is such that the TAiIN pin goes "H" when the input signal on the TAiOUT pin is "H", the timer counts up rising and falling edges on the TAiOUT and TAiIN pins. If the phase relationship is such that the TAiIN pin goes "L" when the input signal on the TAiOUT pin is "H", the timer counts down rising and falling edges on the TAiOUT and TAiIN pins. TAiOUT Count up all edges Count down all edges TAiIN (i=3,4) Count up all edges Count down all edges Note 1: This does not apply when the free-run function is selected. Note 2: Timer A3 is selectable. Timer A2 is fixed to normal processing operation and timer A4 is fixed to multiply-by-4 operation. Rev.1.00 Aug. 02, 2005 Page 99 REJ09B0187-0100 of 329 M16C/80 Group 13. Timer A Timer Ai mode register (When using two-phase pulse signal processing) b7 b6 b5 b4 b3 b2 b1 b0 010 01 Symbol TAiMR(i=2 to 4) Address When reset 035816 to 035A16 00000X002 Bit symbol TMOD0 TMOD1 MR0 MR1 MR2 MR3 TCK0 TCK1 Bit name Operation mode select bit b1 b0 Function 0 1 : Event counter mode RW (Note 1) This bit is invalid in M16C/80 series. -- Port output control is set by the function select registers A and B. 0 (Set to "0" when using two-phase pulse signal processing) 1 (Set to "1" when using two-phase pulse signal processing) 0 (Set to "0" when using two-phase pulse signal processing) Count operation type select bit Two-phase pulse processing operation select bit (Note 2)(Note 3) 0 : Reload type 1 : Free-run type 0 : Normal processing operation 1 : Multiply-by-4 processing operation Note 1: Set the corresponding function select register A to I/O port. Note 2: This bit is valid for timer A3 mode register. Timer A2 is fixed to normal processing operation and timer A4 is fixed to multiply-by-4 processing operation. Note 3: When performing two-phase pulse signal processing, make sure the two-phase pulse signal processing operation select bit (address 034416) is set to "1". Also, always be sure to set the event/trigger select bit (addresses 034316) to "00". Figure 13.7 Timer Ai mode register in event counter mode Rev.1.00 Aug. 02, 2005 Page 100 of 329 REJ09B0187-0100 M16C/80 Group 13. Timer A * Counter Resetting by Two-Phase Pulse Signal Processing This function resets the timer counter to "0" when the Z-phase (counter reset) is input during twophase pulse signal processing. This function can only be used in timer A3 event counter mode, two-phase pulse signal processing, free-run type, and multiply-by-4 processing. The Z phase is input to the INT2 pin. When the Z-phase input enable bit (bit 5 at address 034216) is set to "1", the counter can be reset by Z-phase input. For the counter to be reset to "0" by Z-phase input, you must first write "000016" to the timer A3 register (address 034D16 and 034C16). The Z-phase is input when the INT2 input edge is detected. The edge polarity is selected by the INT2 polarity switch bit (bit 4 at address 009C16). The Z-phase must have a pulse width greater than 1 cycle of the timer A3 count source. Figure 13.8 shows the relationship between the two-phase pulse (A phase and B phase) and the Z phase. The counter is reset at the count source following Z-phase input. Figure 13.9 shows the timing at which the counter is reset to "0". TA3OUT (A phase) TA3IN (B phase) Count source INT2 (Note) (Z phase) The pulse must be wider than this width. Note: When the rising edge of INT2 is selected Figure 13.8 The relationship between the two-phase pulse (A phase and B phase) and the Z phase Rev.1.00 Aug. 02, 2005 Page 101 REJ09B0187-0100 of 329 M16C/80 Group 13. Timer A TA3OUT (A phase) TA3IN (B phase) Count source INT2 (Note) (Z phase) Count value m m+1 1 2 3 4 5 Becoming "0" at this timing. Note: When the rising edge of INT2 is selected Figure 13.9 The counter reset timing Note that timer A3 interrupt requests occur successively two times when timer A3 underflow and INT2 input reload are happened at the same timing. Do not use timer A3 interrupt request when this function is used. Rev.1.00 Aug. 02, 2005 Page 102 of 329 REJ09B0187-0100 M16C/80 Group 13. Timer A (3) One-shot timer mode In this mode, the timer operates only once. (See Table 13.4) When a trigger occurs, the timer starts up and continues operating for a given period. Figure 13.10 shows the timer Ai mode register in one-shot timer mode. Table 13.4 Timer specifications in one-shot timer mode Item Specification Count source f1, f8, f32, fC32 Count operation * The timer counts down * When the count reaches 000016, the timer stops counting after reloading a new count * If a trigger occurs when counting, the timer reloads a new count and restarts counting Divide ratio 1/n n : Set value Count start condition * An external trigger is input * The timer overflows * The one-shot start flag is set (= 1) Count stop condition * A new count is reloaded after the count has reached 000016 * The count start flag is reset (= 0) Interrupt request generation timing The count reaches 000016 TAiIN pin function Programmable I/O port or trigger input TAiOUT pin function Programmable I/O port or pulse output (Setting by the corresponding function select registers A and B) Read from timer When timer Ai register is read, it indicates an indeterminate value Write to timer * When not counting Value written to timer Ai register is written to both reload register and counter * When counting Value written to timer Ai register is written to only reload register (Transferred to counter at next reload time) Timer Ai mode register b7 b6 b5 b4 b3 b2 b1 b0 0 10 Symbol TAiMR(i=0 to 4) Bit symbol TMOD0 TMOD1 MR0 MR1 MR2 Address When reset 035616 to 035A16 00000X002 Bit name Function b1 b0 RW Operation mode select bit 1 0 : One-shot timer mode This bit is invalid in M16C/80 series. Port output control is set by the function select registers A and B. External trigger select bit (Note 1) Trigger select bit 0 : Falling edge of TAiIN pin's input signal (Note 2) 1 : Rising edge of TAiIN pin's input signal (Note 2) -- 0 : One-shot start flag is valid 1 : Selected by event/trigger select bit MR3 TCK0 TCK1 0 (Set to "0" in one-shot timer mode) Count source select bit b7 b6 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 Note 1: Valid only when the TAiIN pin is selected by the event/trigger select bit (addresses 034216 and 034316). If timer overflow is selected, this bit can be "1" or "0". Note 2: Set the corresponding port function select register to I/O port, and port direction register to "0". Figure 13.10 Timer Ai mode register in one-shot timer mode Rev.1.00 Aug. 02, 2005 Page 103 REJ09B0187-0100 of 329 M16C/80 Group 13. Timer A (4) Pulse width modulation (PWM) mode In this mode, the timer outputs pulses of a given width in succession. (See Table 13.5) In this mode, the counter functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Figure 13.11 shows the timer Ai mode register in pulse width modulation mode. Figure 13.12 shows the example of how a 16-bit pulse width modulator operates. Figure 13.13 shows the example of how an 8-bit pulse width modulator operates. Table 13.5 Timer specifications in pulse width modulation mode f1, f8, f32, fC32 * The timer counts down (operating as an 8-bit or a 16-bit pulse width modulator) * The timer reloads a new count at a rising edge of PWM pulse and continues counting * The timer is not affected by a trigger that occurs when counting 16-bit PWM * High level width n / fi n : Set value * Cycle time (216-1) / fi fixed * High level width n (m+1) / fi n : values set to timer Ai register's high-order address 8-bit PWM * Cycle time (28-1) (m+1) / fi m:values set to timer Ai register's low-order address Count start condition * External trigger is input * The timer overflows * The count start flag is set (= 1) Count stop condition * The count start flag is reset (= 0) Interrupt request generation timing PWM pulse goes "L" TAiIN pin function Programmable I/O port or trigger input TAiOUT pin function Pulse output (TAiOUT output is selected by the corresponding function select registers A and B) Read from timer When timer Ai register is read, it indicates an indeterminate value Write to timer * When not counting Value written to timer Ai register is written to both reload register and counter * When counting Value written to timer Ai register is written to only reload register (Transferred to counter at next reload time) Item Count source Count operation Specification Timer Ai mode register b7 b6 b5 b4 b3 b2 b1 b0 1 1 Symbol TAiMR(i=0 to 4) Bit symbol TMOD0 TMOD1 MR0 MR1 MR2 MR3 Address When reset 035616 to 035A16 00000X002 Function b1 b0 Bit name Operation mode select bit RW 1 1 : Pulse width modulaten (PWM) mode This bit is invalid in M16C/80 series. Port output control is set by the function select registers A and B. External trigger select bit (Note 1) Trigger select bit 16/8-bit PWM mode select bit Count source select bit 0: Falling edge of TAiIN pin's input signal (Note 2) 1: Rising edge of TAiIN pin's input signal (Note 2) -- 0: Count start flag is valid 1: Selected by event/trigger select bit 0: Functions as a 16-bit pulse width modulator 1: Functions as an 8-bit pulse width modulator b7 b6 TCK0 TCK1 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 Note 1: Valid only when the TAiIN pin is selected by the event/trigger select bit (addresses 034216 and 034316). If timer overflow is selected, this bit can be "1" or "0". Note 2: Set the corresponding function select register A to I/O port, and port direction register to "0". Figure 13.11 Timer Ai mode register in pulse width modulation mode Rev.1.00 Aug. 02, 2005 Page 104 of 329 REJ09B0187-0100 M16C/80 Group 13. Timer A Condition : Reload register = 000316, when external trigger (rising edge of TAiIN pin input signal) is selected 1 / fi X (2 16 - 1) Count source TAiIN pin input signal "H" "L" Trigger is not generated by this signal 1 / fi X n PWM pulse output from TAiOUT pin Timer Ai interrupt request bit "H" "L" "1" "0" fi : Frequency of count source (f1, f8, f32, fC32) Cleared to "0" when interrupt request is accepted, or cleared by software Note: n = 000016 to FFFE16. Figure 13.12 Example of how a 16-bit pulse width modulator operates Condition : Reload register high-order 8 bits = 0216 Reload register low-order 8 bits = 0216 External trigger (falling edge of TAiIN pin input signal) is selected 1 / fi X (m + 1) X (2 8 - 1) Count source (Note1) TAiIN pin input signal "H" "L" 1 / fi X (m + 1) "H" Underflow signal of 8-bit prescaler (Note2) "L" 1 / fi X (m + 1) X n PWM pulse output from TAiOUT pin Timer Ai interrupt request bit "H" "L" "1" "0" fi : Frequency of count source (f1, f8, f32, fC32) Cleared to "0" when interrupt request is accepted, or cleaerd by software Note 1: The 8-bit prescaler counts the count source. Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal. Note 3: m = 0016 to FE16; n = 0016 to FE16. Figure 13.13 Example of how an 8-bit pulse width modulator operates Rev.1.00 Aug. 02, 2005 Page 105 REJ09B0187-0100 of 329 M16C/80 Group 14. Timer B 14. Timer B Figure 14.1 shows the block diagram of timer B. Figures 14.2 and 14.3 show the timer B-related registers. Use the timer Bi mode register (i = 0 to 5) bits 0 and 1 to choose the desired mode. Timer B has three operation modes listed as follows: * Timer mode: The timer counts an internal count source. * Event counter mode: The timer counts pulses from an external source or a timer overflow. * Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or pulse width. Data bus high-order bits Data bus low-order bits Low-order 8 bits High-order 8 bits Clock source selection f1 f8 f32 fC32 TBiIN (i = 0 to 5) * Timer * Pulse period/pulse width measurement Reload register (16) * Event counter Polarity switching and edge pulse Count start flag (address 034016) Counter reset circuit Can be selected in only event counter mode TBj overflow (j = i - 1. Note, however, j = 2 when i = 0, j = 5 when i = 3) TBi Timer B0 Timer B1 Timer B2 Timer B3 Timer B4 Timer B5 Counter (16) Address 035116 035016 035316 035216 035516 035416 031116 031016 031316 031216 031516 031416 TBj Timer B2 Timer B0 Timer B1 Timer B5 Timer B3 Timer B4 Figure 14.1 Block diagram of timer B Timer Bi mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address TBiMR(i = 0 to 5) 035B16 to 035D16 031B16 to 031D16 When reset 00XX00002 00XX00002 Bit symbol TMOD0 TMOD1 Bit name Operation mode select bit b1 b0 Function 0 0 : Timer mode 0 1 : Event counter mode 1 0 : Pulse period/pulse width measurement mode 1 1 : Must not be set R W MR0 MR1 MR2 Function varies with each operation mode (Note 1) (Note 2) MR3 TCK0 TCK1 Count source select bit (Function varies with each operation mode) Note 1: Timer B0, timer B3. Note 2: Timer B1, timer B2, timer B4, timer B5. Figure 14.2 Timer B-related registers (1) Rev.1.00 Aug. 02, 2005 Page 106 of 329 REJ09B0187-0100 M16C/80 Group 14. Timer B Timer Bi register (Note) (b15) b7 (b8) b0 b7 b0 Symbol TB0 TB1 TB2 TB3 TB4 TB5 Address 035116, 035016 035316, 035216 035516, 035416 031116, 031016 031316, 031216 031516, 031416 When reset Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Values that can be set Function * Timer mode Counts the timer's period * Event counter mode Counts external pulses input or a timer overflow * Pulse period / pulse width measurement mode Measures a pulse period or width RW 000016 to FFFF16 000016 to FFFF16 Note: Read and write data in 16-bit units. Count start flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol TABSR Address 034016 When reset 0016 Bit symbol TA0S TA1S TA2S TA3S TA4S TB0S TB1S TB2S Bit name Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Timer B0 count start flag Timer B1 count start flag Timer B2 count start flag Function 0 : Stops counting 1 : Starts counting RW Timer B3, 4, 5 count start flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol TBSR Address 030016 When reset 000XXXXX2 Bit symbol Bit name Function RW Nothing is assigned. When write, set "0". When read, the value of these bits is indeterminate. TB3S TB4S TB5S Timer B3 count start flag Timer B4 count start flag Timer B5 count start flag 0 : Stops counting 1 : Starts counting Clock prescaler reset flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol CPSRF Address 034116 When reset 0XXXXXXX2 Bit symbol Bit name Function RW Nothing is assigned. When write, set "0". When read, the value of these bits is indeterminate. CPSR Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is "0") Figure 14.3 Timer B-related registers (2) Rev.1.00 Aug. 02, 2005 Page 107 REJ09B0187-0100 of 329 M16C/80 Group 14. Timer B (1) Timer mode In this mode, the timer counts an internally generated count source. (See Table 14.1) Figure 14.4 shows the timer Bi mode register in timer mode. Table 14.1 Timer specifications in timer mode Specification f1, f8, f32, fC32 * Counts down * When the timer underflows, it reloads the reload register contents before continuing counting Divide ratio 1/(n+1) n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing The timer underflows TBiIN pin function Programmable I/O port Read from timer Count value is read out by reading timer Bi register Write to timer * When not counting Value written to timer Bi register is written to both reload register and counter * When counting Value written to timer Bi register is written to only reload register (Transferred to counter at next reload time) Item Count source Count operation Timer Bi mode register b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol Address TBiMR(i = 0 to 5) 035B16 to 035D16 031B16 to 031D16 Bit symbol TMOD0 TMOD1 MR0 MR1 MR2 Invalid in timer mode Can be "0" or "1" When reset 00XX00002 00XX00002 Bit name Operation mode select bit b1 b0 Function 0 0 : Timer mode R W 0 (Set to "0" in timer mode ; i = 0, 3) Nothing is assiigned (i = 1, 2, 4, 5). When write, set "0". When read, its content is indeterminate. (Note 1) (Note 2) MR3 Invalid in timer mode. When write, set "0". When read in timer mode, its content is indeterminate. Count source select bit b7 b6 TCK0 TCK1 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 Note 1: Timer B0, timer B3. Note 2: Timer B1, timer B2, timer B4, timer B5. Figure 14.4 Timer Bi mode register in timer mode Rev.1.00 Aug. 02, 2005 Page 108 of 329 REJ09B0187-0100 M16C/80 Group 14. Timer B (2) Event counter mode In this mode, the timer counts an external signal or an internal timer's overflow. (See Table 14.2) Figure 14.5 shows the timer Bi mode register in event counter mode. Table 14.2 Timer specifications in event counter mode Item Specification Count source * External signals input to TBiIN pin Effective edge of count source can be a rising edge, a falling edge, or falling and rising edges as selected by software * TBi overflows or underflows Count operation * Counts down * When the timer underflows, it reloads the reload register contents before continuing counting Divide ratio 1/(n+1) n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing The timer underflows TBiIN pin function Programable I/O port or Count source input (Set the corresponding function select register A to I/O port.) Read from timer Count value can be read out by reading timer Bi register Write to timer * When not counting Value written to timer Bi register is written to both reload register and counter * When counting Value written to timer Bi register is written to only reload register (Transferred to counter at next reload time) Timer Bi mode register b7 b6 b5 b4 b3 b2 b1 b0 01 Symbol Address TBiMR(i = 0 to 5) 035B16 to 035D16 031B16 to 031D16 When reset 00XX00002 00XX00002 Bit symbol TMOD0 TMOD1 MR0 Bit name Operation mode select bit Count polarity select bit (Note 1) b1 b0 Function 0 1 : Event counter mode b3 b2 R W MR1 0 0 : Counts external signal's falling edges 0 1 : Counts external signal's rising edges 1 0 : Counts external signal's falling and rising edges 1 1 : Must not be set (Note 2) MR2 0 (Set to "0" in event counter mode; i = 0, 3) Nothing is assigned (i = 1, 2, 4, 5). When write, set "0". When read, its content is indeterminate. (Note 3) MR3 Invalid in event counter mode. When write, set "0". When read in event counter mode, its content is indeterminate. Invalid in event counter mode. Can be "0" or "1". Event clock select 0 : Input from TBiIN pin (Note 4) 1 : TBj overflow (j = i - 1; however, j = 2 when i = 0, j = 5 when i = 3) TCK0 TCK1 Note 1: Valid only when input from the TBiIN pin is selected as the event clock. If timer's overflow is selected, this bit can be "0" or "1". Note 2: Timer B0, timer B3. Note 3: Timer B1, timer B2, timer B4, timer B5. Note 4: Set the corresponding function select register A to I/O port, and port direction register to "0". Figure 14.5 Timer Bi mode register in event counter mode Rev.1.00 Aug. 02, 2005 Page 109 REJ09B0187-0100 of 329 M16C/80 Group 14. Timer B (3) Pulse period/pulse width measurement mode In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table 14.3) Figure 14.6 shows the timer Bi mode register in pulse period/pulse width measurement mode. Figure 14.7 shows the operation timing when measuring a pulse period. Figure 14.8 shows the operation timing when measuring a pulse width. Table 14.3 Timer specifications in pulse period/pulse width measurement mode Specification f1, f8, f32, fc32 * Up count * Counter value "000016" is transferred to reload register at measurement pulse's effective edge and the timer continues counting Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing * When measurement pulse's effective edge is input (Note 1) * Timer overflow. When an overflow occurs, the timer Bi overflow flag set to "1" simultaneously. The timer Bi overflow flag cleared to "0" by writing to the timer mode register at the next count timing or later after the timer Bi overflow flag was set to "1". At this time, make sure the timer start flag is set to "1". TBiIN pin function Measurement pulse input (Set the corresponding function select register A to I/O port.) Read from timer When timer Bi register is read, it indicates the reload register's content (measurement result) (Note 2) Write to timer Cannot be written to Note 1: An interrupt request is not generated when the first effective edge is input after the timer has started counting. Note 2: The value read out from the timer Bi register is indeterminate until the second effective edge is input after the timer. Timer Bi mode register b7 b6 b5 b4 b3 b2 b1 b0 Item Count source Count operation 10 Symbol Address TBiMR(i = 0 to 5) 035B16 to 035D16 031B16 to 031D16 When reset 00XX00002 00XX00002 Bit symbol TMOD0 TMOD1 MR0 Bit name Operation mode select bit Measurement mode select bit b1 b0 Function 1 0 : Pulse period / pulse width measurement mode b3 b2 R W MR1 0 0 : Pulse period measurement (Interval between measurement pulse's falling edge to falling edge) 0 1 : Pulse period measurement (Interval between measurement pulse's rising edge to rising edge) 1 0 : Pulse width measurement (Interval between measurement pulse's falling edge to rising edge, and between rising edge to falling edge) 1 1 : Must not be set MR2 0 (Set to "0" in pulse period/pulse width measurement mode; i = 0, 3) Nothing is assigned (i = 1, 2, 4, 5). When write, set "0". When read, its content is indeterminate. (Note 2) (Note 3) MR3 TCK0 TCK1 Timer Bi overflow flag ( Note 1) Count source select bit 0 : Timer did not overflow 1 : Timer has overflowed b7 b6 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 Note 1: This flag is indeterminate after reset. When the timer Bi start flag = 1, the timer Bi overflow flag is cleared to "0" by writing to the timer Bi mode register at the next count timing or later after the timer Bi overflow flag was set to "1". The Timer Bi overflow flag cannot be set to "1" in a program. Note 2: Timer B0, timer B3. Note 3: Timer B1, timer B2, timer B4, timer B5. Figure 14.6 Timer Bi mode register in pulse period/pulse width measurement mode Rev.1.00 Aug. 02, 2005 Page 110 of 329 REJ09B0187-0100 M16C/80 Group 14. Timer B When measuring measurement pulse time interval from falling edge to falling edge Count source Measurement pulse "H" "L" Transfer (indeterminate value) Transfer (measured value) Reload register transfer timing counter (Note 1) (Note 1) (Note 2) Timing at which counter reaches "000016" Count start flag "1" "0" Timer Bi interrupt request bit "1" "0" Cleared to "0" when interrupt request is accepted, or cleared by software. Timer Bi overflow flag "1" "0" Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflowed. Figure 14.7 Operation timing when measuring a pulse period Count source Measurement pulse "H" "L" Transfer (indeterminate value) Transfer (measured value) Transfer (measured value) Transfer (measured value) Reload register transfer timing counter (Note 1) (Note 1) (Note 1) (Note 1) (Note 2) Timing at which counter reaches "000016" "1" "0" Count start flag Timer Bi interrupt request bit "1" "0" Cleared to "0" when interrupt request is accepted, or cleared by software. Timer Bi overflow flag "1" "0" Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflowed. Figure 14.8 Operation timing when measuring a pulse width Rev.1.00 Aug. 02, 2005 Page 111 REJ09B0187-0100 of 329 M16C/80 Group 15. Three-phase motor control timers' functions 15. Three-phase motor control timers' functions Use of more than one built-in timer A and timer B provides the means of outputting three-phase motor driving waveforms. Figures 15.1 through 15.3 show registers related to timers for three-phase motor control. Three-phase PWM control register 0 b7 b6 b5 b4 b3 b2 b1 b0 (Note 5) Symbol INVC0 Address 030816 When reset 0016 R W Bit symbol INV00 Effective interrupt output polarity select bit Bit name Description 0: A timer B2 interrupt occurs when the timer A1 reload control signal is "0". 1: A timer B2 interrupt occurs when the timer A1 reload control signal is "1". Effective only in three-phase mode 1 0: Not specified. 1: Selected by the effective interrupt output polarity selection bit. Effective only in three-phase mode 1 0: Normal mode 1: Three-phase PWM output mode 0: Output disabled 1: Output enabled INV01 Effective interrupt output specification bit (Note 4) INV02 INV03 Mode select bit (Note 2) Output control bit INV04 0: Feature disabled Positive and negative phases concurrent L output 1: Feature enabled disable function enable bit 0: Not detected yet Positive and negative phases concurrent L output 1: Already detected detect flag Modulation mode select bit (Note 3) Software trigger bit 0: Triangular wave modulation mode 1: Sawtooth wave modulation mode 1: Trigger generated The value, when read, is "0". INV05 INV06 INV07 (Note 1) Note 1: No value other than "0" can be written. Note 2: Selecting three-phase PWM output mode causes the dead time timer, the U, V, W phase output control circuits, and the timer B2 interrupt occurrences frequency set circuit works. For U, U, V, V, W and W output from P80, P81, and P72 through P75, setting of function select registers A, B and C is required. Note 3: In triangular wave modulation mode: The dead time timer starts in synchronization with the falling edge of timer Ai output. The data transfer from the three-phase buffer register to the three-phase output shift register is made only once in synchronization with the transfer trigger signal after writing to the three-phase output buffer register. In sawtooth wave modulation mode: The dead time timer starts in synchronization with the falling edge of timer A output and with the transfer trigger signal. The data transfer from the three-phase output buffer register to the threephase output shift register is made with respect to every transfer trigger. Note 4: Set bit 1 of this register to "1" after setting timer B2 interrupt frequency set counter. Note 5: Rewrite the INV00 to INV02 and INV06 bits when the timers A1,A2,A4 and B stop. Three-phase PWM control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol INVC1 Address 030916 When reset XXX0X0002 R W Bit symbol INV10 Bit name Timer Ai start trigger signal select bit Timer A1-1, A2-1, A4-1 control bit Dead time timer count source select bit Carrier wave detect flag (Note) Output porality control bit Description 0: Timer B2 overflow signal 1: Timer B2 overflow signal, signal for writing to timer B2 0: Three-phase mode 0 1: Three-phase mode 1 0 : f1 1 : f1/2 0: Rising edge of triangular waveform 1: Falling edge of triangular waveform 0 : Low active 1 : High active INV11 INV12 INV13 INV14 X Noting is assigned. When write, set "0". When read, their contents are "0". Note : INV13 is valid when INV06 = 0 and INV11 = 1. - - Figure 15.1 Registers related to timers for three-phase motor control Rev.1.00 Aug. 02, 2005 Page 112 of 329 REJ09B0187-0100 M16C/80 Group 15. Three-phase motor control timers' functions Three-phase output buffer register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol IDB0 Bit Symbol Address 030A16 When reset 3F16 Bit name U phase output buffer 0 U phase output buffer 0 V phase output buffer 0 V phase output buffer 0 W phase output buffer 0 W phase output buffer 0 Function Setting in U phase output buffer 0 Setting in U phase output buffer 0 Setting in V phase output buffer 0 Setting in V phase output buffer 0 Setting in W phase output buffer 0 Setting in W phase output buffer 0 RW Note Note Note Note Note Note DU0 DUB0 DV0 DVB0 DW0 DWB0 Nothing is assigned. When write, set "0". When read, its content is "0". Note: When executing read instruction of this register, the contents of three-phase shift register is read out. Three-phase output buffer register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol IDB1 Bit Symbol Address 030B16 When reset 3F16 Bit name U phase output buffer 1 U phase output buffer 1 V phase output buffer 1 V phase output buffer 1 W phase output buffer 1 W phase output buffer 1 Function Setting in U phase output buffer 1 Setting in U phase output buffer 1 Setting in V phase output buffer 1 Setting in V phase output buffer 1 Setting in W phase output buffer 1 Setting in W phase output buffer 1 RW Note Note Note Note Note Note DU1 DUB1 DV1 DVB1 DW1 DWB1 Nothing is assigned. When write, set "0". When read, its content is "0". Note: When executing read instruction of this register, the contents of three-phase shift register is read out. Dead time timer (Note) b7 b0 Symbol DTT Address 030C16 When reset Indeterminate Function Set dead time timer Note: Use MOV instruction to write to this register. Values that can be set 1 to 255 RW Timer B2 interrupt occurrences frequency set counter (Note 1 to 4) b3 b0 Symbol ICTB2 Address 030D16 When reset Indeterminate Function Set occurrence frequency of timer B2 interrupt request Values that can be set 1 to 15 R W Note 1: When the effective interrupt output specification bit (INV01: bit 1 at 030816) is set to "1" and three-phase motor control timer is operating, do not rewrite to this register. Note 2: Do not write to this register at the timing of timer B2 overflow. Note 3: Use MOV instruction to write to this register. Note 4: Setting of this register is valid only when bit 2(INV02) of three-phase PWM control register 0 is set to "1". Figure 15.2 Registers related to timers for three-phase motor control Rev.1.00 Aug. 02, 2005 Page 113 REJ09B0187-0100 of 329 M16C/80 Group 15. Three-phase motor control timers' functions Timer Ai register (Note1) (b15) b7 (b8) b0 b7 b0 Symbol TA1 TA2 TA4 TB2 Function Address 034916,034816 034B16,034A16 034F16,034E16 035516,035416 When reset Indeterminate Indeterminate Indeterminate Indeterminate Values that can be set RW * Timer mode Counts an internal count source * One-shot timer mode Counts a one shot width 000016 to FFFF16 000016 to FFFF16 (Note 2, 3) Note 1: Read and write data in 16-bit units. Note 2: When the timer Ai register is set to "000016", the counter does not operate and a timer Ai interrupt does not occur. Note 3: When writing to this register, use MOV instruction. Timer Ai-1 register (Note 1 to 2) (b15) b7 (b8) b0 b7 b0 Symbol TA11 TA21 TA41 Function Address 030316,030216 030516,030416 030716,030616 When reset Indeterminate Indeterminate Indeterminate Values that can be set RW Counts an internal count source 000016 to FFFF16 Note 1: Read and write data in 16-bit units. Note 2: Do not write to these register at the timing of timer B2 overflow. Trigger select register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRGSR Bit symbol TA1TGL Address 034316 Bit name Timer A1 event/trigger select bit When reset 0016 Function b1 b0 RW TA1TGH TA2TGL 0 0 : Input on TA1IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA0 overflow is selected 1 1 : TA2 overflow is selected b3 b2 Timer A2 event/trigger select bit TA2TGH TA3TGL TA3TGH 0 0 : Input on TA2IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA1 overflow is selected 1 1 : TA3 overflow is selected b5 b4 Timer A3 event/trigger select bit 0 0 : Input on TA3IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA2 overflow is selected 1 1 : TA4 overflow is selected b7 b6 TA4TGL TA4TGH Timer A4 event/trigger select bit 0 0 : Input on TA4IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA3 overflow is selected 1 1 : TA0 overflow is selected Note: Set the corresponding port function select register to I/O port, and port direction register to "0". Count start flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol TABSR Bit symbol TA0S TA1S TA2S TA3S TA4S TB0S TB1S TB2S Address 034016 Bit name Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Timer B0 count start flag Timer B1 count start flag Timer B2 count start flag When reset 0016 Function 0 : Stops counting 1 : Starts counting RW Figure 15.3 Registers related to timers for three-phase motor control Rev.1.00 Aug. 02, 2005 Page 114 of 329 REJ09B0187-0100 M16C/80 Group 15. Three-phase motor control timers' functions Three-phase motor driving waveform output mode (three-phase PWM output mode) Setting "1" in the mode select bit (bit 2 at 030816) shown in Figure 15.1 causes three-phase PWM output mode that uses four timers A1, A2, A4, and B2 to be selected. As shown in Figure 15.4, set timers A1, A2, and A4 in one-shot timer mode, set the trigger in timer B2, and set timer B2 in timer mode using the respective timer mode registers. Timer Ai mode register b7 b6 b5 b4 b3 b2 b1 b0 01 10 Symbol TA1MR TA2MR TA3MR Address 035716 035816 035A16 Bit name Operation mode select bit When reset 00000X002 00000X002 00000X002 Function b1 b0 Bit symbol TMOD0 TMOD1 MR0 RW 1 0 : One-shot timer mode This bit is invalid in M16C/80 series. Port output control is set by the function select registers A and B. -- MR1 MR2 MR3 TCK0 TCK1 External trigger select bit Trigger select bit Invalid in three-phase PWM output mode. 1 : Selected by event/trigger select register 0 (Set to "0" in one-shot timer mode) Count source select bit b7 b6 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 Timer B2 mode register b7 b6 b5 b4 b3 b2 b1 b0 0 00 Symbol TB2MR Address 035D16 When reset 00XX00002 Bit symbol TMOD0 TMOD1 MR0 MR1 MR2 MR3 Bit name Operation mode select bit b1 b0 Function 0 0 : Timer mode RW Invalid in timer mode Can be "0" or "1" 0 (Set to "0" in timer mode) Invalid in timer mode. When write, set "0". When read in timer mode, its content is indeterminate. Count source select bit b7 b6 TCK0 TCK1 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 Figure 15.4 Timer mode registers in three-phase PWM output mode Rev.1.00 Aug. 02, 2005 Page 115 REJ09B0187-0100 of 329 M16C/80 Group 15. Three-phase motor control timers' functions Figure 15.5 shows the block diagram for three-phase waveform mode. In "L" active output polarity in three-phase waveform mode, the positive-phase waveforms (U phase, V phase, and W phase) and ___ ___ ___ negative waveforms (U phase, V phase, and W phase), six waveforms in total, are output from P80, P81, P72, P73, P74, and P75 as active on the "L" level. Of the timers used in this mode, timer A4 controls the U ___ ___ phase and U phase, timer A1 controls the V phase and V phase, and timer A2 controls the W phase and ___ W phase respectively; timer B2 controls the periods of one-shot pulse output from timers A4, A1, and A2. In outputting a waveform, dead time can be set so as to cause the "L" level of the positive waveform ___ output (U phase, V phase, and W phase) not to lap over the "L" level of the negative waveform output (U ___ ___ phase, V phase, and W phase). To set short circuit time, use three 8-bit timers sharing the reload register for setting dead time. A value from 1 through 255 can be set as the count of the timer for setting dead time. The timer for setting dead time works as a one-shot timer. If a value is written to the dead timer (030C16), the value is written to the reload register shared by the three timers for setting dead time. Any of the timers for setting dead time takes the value of the reload register into its counter, if a start trigger comes from its corresponding timer, and performs a down count in line with the clock source selected by the dead time timer count source select bit (bit 2 at 030916). The timer can receive another trigger again before the workings due to the previous trigger are completed. In this instance, the timer performs a down count from the reload register's content after its transfer, provoked by the trigger, to the timer for setting dead time. Since the timer for setting dead time works as a one-shot timer, it starts outputting pulses if a trigger comes; it stops outputting pulses as soon as its content becomes 0016, and waits for the next trigger to come. ___ ___ The positive waveforms (U phase, V phase, and W phase) and the negative waveforms (U phase, V ___ phase, and W phase) in three-phase waveform mode are output from respective ports by means of setting "1" in the output control bit (bit 3 at 030816). Setting "0" in this bit causes the ports to be the highimpedance state. This bit can be set to "0" not only by use of the applicable instruction, but by entering a _______ falling edge in the NMI terminal or by resetting. Also, if "1" is set in the positive and negative phases ___ concurrent L output disable function enable bit (bit 4 at 030816) causes one of the pairs of U phase and U ___ ___ phase, V phase and V phase, and W phase and W phase concurrently go to "L", as a result, the output control bit becomes the high-impedance state. Rev.1.00 Aug. 02, 2005 Page 116 of 329 REJ09B0187-0100 INV13 INV01 INV11 Circuit foriInterrupt occurrence frequency set counter M16C/80 Group INV00 1 Interrupt request bit 0 f1 0 1/2 Trigger Trigger Dead time timer setting (8) n = 1 to 255 Bit 0 at 030B16 Bit 0 at 030A16 DQ T INV06 U phase output control circuit DU0 U phase output signal 1 n = 1 to 255 Reload register Interrupt occurrence frequency set counter n = 1 to 15 RESET NMI R INV03 D Q Overflow INV05 INV04 INV14 Signal to be written to B2 INV10 INV07 Timer B2 Rev.1.00 Aug. 02, 2005 Page 117 REJ09B0187-0100 U(P80) DU1 D Q D Q T T (Timer mode) Trigger signal for timer Ai start Figure 15.5 Block diagram for three-phase waveform mode Trigger signal for transfer Three-phase output shift register (U phase) DUB1 U phase output signal DUB0 of 329 D Q D Q T T Timer A4 Reload Timer A4-1 Trigger Timer A4 counter (One-shot timer mode) INV11 DQ T TQ U(P81) To be set to "0" when timer A4 stops Trigger Trigger Dead time timer setting (8) n = 1 to 255 INV06 DQ T V(P72) Timer A1 Reload Timer A1-1 Trigger V phase output control circuit V phase output signal V phase output signal Timer A1 counter V(P73) DQ T For short circuit prevention (One-shot timer mode) INV11 TQ To be set to "0" when timer A1 stops Trigger Trigger INV06 W phase output control circuit W(P74) n = 1 to 255 W phase output signal W phase output signal DQ T DQ T Dead time timer setting (8) Timer A2 Reload Timer A2-1 Trigger Timer A2 counter W(P75) 15. Three-phase motor control timers' functions (One-shot timer mode) INV11 TQ To be set to "0" when timer A2 stops Diagram for switching to P80, P81 and P72 - P75 is not shown. M16C/80 Group 15. Three-phase motor control timers' functions Triangular wave modulation To generate a PWM waveform of triangular wave modulation, set "0" in the modulation mode select bit (bit 6 at 030816). Also, set "1" in the timers A4-1, A1-1, A2-1 control bit (bit 1 at 030916). In this mode, each of timers A4, A1, and A2 has two timer registers, and alternately reloads the timer register's content to the counter every time timer B2 counter's content becomes 000016. If "0" is set to the effective interrupt output specification bit (bit 1 at 030816), the frequency of interrupt requests that occur every time the timer B2 counter's value becomes 000016 can be set by use of the timer B2 counter (030D16) for setting the frequency of interrupt occurrences. The frequency of occurrences is given by (setting; setting 0). Setting "1" in the effective interrupt output specification bit (bit 1 at 030816) provides the means to choose which value of the timer A1 reload control signal to use, "0" or "1", to cause timer B2's interrupt request to occur. To make this selection, use the effective interrupt output polarity selection bit (bit 0 at 030816). An example of U phase waveform is shown in Figure 15.6, and the description of waveform output workings is given below. Set "1" in DU0 (bit 0 at 030A16). And set "0" in DUB0 (bit 1 at 030A16). In addition, set "0" in DU1 (bit 0 at 030B16) and set "1" in DUB1 (bit 1 at 030B16). Also, set "0" in the effective interrupt output specification bit (bit 1 at 030816) to set a value in the timer B2 interrupt occurrence frequency set counter. By this setting, a timer B2 interrupt occurs when the timer B2 counter's content becomes 000016 as many as (setting) times. Furthermore, set "1" in the effective interrupt output specification bit (bit 1 at 030816), set in the effective interrupt polarity select bit (bit 0 at 030816) and set "1" in the interrupt occurrence frequency set counter (030D16). These settings cause a timer B2 interrupt to occur every other interval when the U phase output goes to "H". When the timer B2 counter's content becomes 000016, timer A4 starts outputting one-shot pulses. In this instance, the content of DU1 (bit 0 at 030B16) and that of DU0 (bit 0 at 030A16) are set in the three-phase output shift register (U phase), the content of DUB1 (bit 1 at 030B16) and that of DUB0 (bit 1 at 030A16) ___ are set in the three-phase shift register (U phase). After triangular wave modulation mode is selected, however, no setting is made in the shift register even though the timer B2 counter's content becomes 000016. ___ The value of DU0 and that of DUB0 are output to the U terminal (P80) and to the U terminal (P81) respectively. When the timer A4 counter counts the value written to timer A4 (034F16, 034E16) and when timer A4 finishes outputting one-shot pulses, the three-phase shift register's content is shifted one posi___ tion, and the value of DU1 and that of DUB1 are output to the U phase output signal and to U phase output signal respectively. At this time, one-shot pulses are output from the timer for setting dead time used for ___ setting the time over which the "L" level of the U phase waveform doesn't lap over the "L" level of the U phase waveform, which has the opposite phase of the former. The U phase waveform output that started from the "H" level keeps its level until the timer for setting dead time finishes outputting one-shot pulses even though the three-phase output shift register's content changes from "1" to "0" by the effect of the one-shot pulses. When the timer for setting dead time finishes outputting one-shot pulses, "0" already shifted in the three-phase shift register goes effective, and the U phase waveform changes to the "L" level. When the timer B2 counter's content becomes 000016, the timer A4 counter starts counting the value written to timer A4-1 (030716, 030616), and starts outputting one-shot pulses. When timer A4 finishes outputting one-shot pulses, the three-phase shift register's content is shifted one position, but if the three-phase output shift register's content changes from "0" to "1" as a result of the shift, the output level changes from "L" to "H" without waiting for the timer for setting dead time to finish outputting one-shot pulses. A U phase waveform is generated by these workings repeatedly. With the exception that the three-phase output shift register on the U phase side is used, the workings in generating a U phase waveform, which has the opposite phase of the U phase waveform, are the same as in generating a U Rev.1.00 Aug. 02, 2005 Page 118 of 329 REJ09B0187-0100 M16C/80 Group 15. Three-phase motor control timers' functions phase waveform. In this way, a waveform can be picked up from the applicable terminal in a manner in which the "L" level of the U phase waveform doesn't lap over that of the U phase waveform, which has the opposite phase of the U phase waveform. The width of the "L" level too can be adjusted by varying the ___ ___ values of timer B2, timer A4, and timer A4-1. In dealing with the V and W phases, and V and W phases, the latter are of opposite phase of the former, have the corresponding timers work similarly to dealing with ___ the U and U phases to generate an intended waveform. A carrier wave of triangular waveform Carrier wave Signal wave Timer B2 Trigger signal for timer Ai start (timer B2 overflow signal) Timer A4 output m Timber B2 interrupt occurres Rewriting timer A4 and timer A4-1. Possible to set the number of overflows to generate an interrupt by use of the interrupt occurrences frequency set circuit n m n m p o Control signal for timer A4 reload U phase output signal U phase output signal U phase (Note 1) The three-phase shift register shifts in synchronization with the falling edge of the A4 output. U phase Dead time U phase (Note 2) U phase Dead time INV13(Triangular wave modulation detect flag) (Note 3) Note 1: When INV14="0" (output wave Low active) Note 2: When INV14="1" (output wave High active) Note 3: Set to triangular wave modulation mode and to three-phase mode 1. Figure 15.6 Timing chart of operation (1) Rev.1.00 Aug. 02, 2005 Page 119 REJ09B0187-0100 of 329 M16C/80 Group 15. Three-phase motor control timers' functions Assigning certain values to DU0 (bit 0 at 030A16) and DUB0 (bit 1 at 030A16), and to DU1 (bit 0 at 030B16) and DUB1 (bit 1 at 030B16) allows you to output the waveforms as shown in Figure 15.7, that is, to output ___ ___ the U phase alone, to fix U phase to "H", to fix the U phase to "H," or to output the U phase alone. A carrier wave of triangular waveform Carrier wave Signal wave Timer B2 Rewriting timer A4 every timer B2 interrupt occurres. Timer B2 interrupt occurres. Rewriting three-phase buffer register. Trigger signal for timer Ai start (timer B2 overflow signal) Timer A4 output m n m n m p o Control signal for timer A4 reload U phase output signal U phase output signal U phase U phase Dead time Note: Set to triangular wave modulation mode and to three-phase mode 1. Figure 15.7 Timing chart of operation (2) Rev.1.00 Aug. 02, 2005 Page 120 of 329 REJ09B0187-0100 M16C/80 Group 15. Three-phase motor control timers' functions Sawtooth modulation To generate a PWM waveform of sawtooth wave modulation, set "1" in the modulation mode select bit (bit 6 at 030816). Also, set "0" in the timers A4, A1, and A2-1 control bit (bit 1 at 030916). In this mode, the timer registers of timers A4, A1, and of A2 comprise conventional timers A4, A1, and A2 alone, and reload the corresponding timer register's content to the counter every time the timer B2 counter's content becomes 000016. The effective interrupt output specification bit (bit 1 at 030816) and the effective interrupt output polarity select bit (bit 0 at 030816) go nullified. An example of U phase waveform is shown in Figure 15.8, and the description of waveform output workings is given below. Set "1" in DU0 (bit 0 at 030A16), and set "0" in DUB0 (bit 1 at 030A16). In addition, set "0" in DU1 (bit 0 at 030B16) and set "1" in DUB1 (bit 1 at 030B16). When the timber B2 counter's content becomes 000016, timer B2 generates an interrupt, and timer A4 starts outputting one-shot pulses at the same time. In this instance, the contents of the three-phase buffer registers DU1 and DU0 are set in the three-phase output shift register (U phase), and the contents of DUB1 and DUB0 are set in the three-phase output register (U phase). After this, the three-phase buffer register's content is set in the three-phase shift register every time the timer B2 counter's content becomes 000016. ___ The value of DU0 and that of DUB0 are output to the U terminal (P80) and to the U terminal (P81) respectively. When the timer A4 counter counts the value written to timer A4 (034F16, 034E16) and when timer A4 finishes outputting one-shot pulses, the three-phase output shift register's content is shifted one ___ position, and the value of DU1 and that of DUB1 are output to the U phase output signal and to the U output signal respectively. At this time, one-shot pulses are output from the timer for setting dead time used for setting the time over which the "L" level of the U phase waveform doesn't lap over the "L" level of ___ the U phase waveform, which has the opposite phase of the former. The U phase waveform output that started from the "H" level keeps its level until the timer for setting dead time finishes outputting one-shot pulses even though the three-phase output shift register's content changes from "1" to "0 "by the effect of the one-shot pulses. When the timer for setting dead time finishes outputting one-shot pulses, 0 already shifted in the three-phase shift register goes effective, and the U phase waveform changes to the "L" level. When the timer B2 counter's content becomes 000016, the contents of the three-phase buffer registers DU1 and DU0 are set in the three-phase shift register (U phase), and the contents of DUB1 and ___ DUB0 are set in the three-phase shift register (U phase) again. A U phase waveform is generated by these workings repeatedly. With the exception that the three-phase ___ ___ output shift register on the U phase side is used, the workings in generating a U phase waveform, which has the opposite phase of the U phase waveform, are the same as in generating a U phase waveform. In this way, a waveform can be picked up from the applicable terminal in a manner in which the "L" level of the U phase waveform doesn't lap over that of the U phase waveform, which has the opposite phase of the U phase waveform. The width of the "L" level too can be adjusted by varying the values of timer B2 ___ ___ and timer A4. In dealing with the V and W phases, and V and W phases, the latter are of opposite phase ___ of the former, have the corresponding timers work similarly to dealing with the U and U phases to generate an intended waveform. Rev.1.00 Aug. 02, 2005 Page 121 REJ09B0187-0100 of 329 M16C/80 Group 15. Three-phase motor control timers' functions A carrier wave of sawtooth waveform Carrier wave Signal wave Timer B2 Trigger signal for timer Ai start (timer B2 overflow signal) Interrupt occurres. Rewriting the value of timer A4. Data transfer is made from the threephase buffer register to the threephase shift register in step with the timing of the timer B overflow. Timer A4 output m n o p U phase output signal U phase output signal U phase U phase The three-phase shift register shifts in synchronization with the falling edge of timer A4. Dead time Note: Set to sawtooth modulation mode and to three-phase mode 0. Figure 15.8 Timing chart of operation (3) Rev.1.00 Aug. 02, 2005 Page 122 of 329 REJ09B0187-0100 M16C/80 Group 15. Three-phase motor control timers' functions ___ Setting "1" both in DUB0 and in DUB1 provides a means to output the U phase alone and to fix the U phase output to "H" as shown in Figure 15.9. A carrier wave of sawtooth waveform Carrier wave Signal wave Timer B2 Interrupt occurres. Rewriting the value of timer A4. Interrupt occurres. Rewriting the value of timer A4. Trigger signal for timer Ai start (timer B2 overflow signal) Rewriting three-phase output buffer register Data transfer is made from the threephase buffer register to the threephase shift register in step with the timing of the timer B overflow. Timer A4 output m n p The three-phase shift register shifts in synchronization with the falling edge of timer A4. U phase output signal U phase output signal U phase U phase Dead time Note: Set to sawtooth modulation mode and to three-phase mode 0. Figure 15.9 Timing chart of operation (4) Rev.1.00 Aug. 02, 2005 Page 123 REJ09B0187-0100 of 329 M16C/80 Group 16. Serial I/O 16. Serial I/O Serial I/O is configured as five channels: UART0 to UART4. UART0 to 4 UART0 to UART4 each have an exclusive timer to generate a transfer clock, so they operate independently of each other. Figures 16.1 and 16.2 show the block diagram of UARTi (i=0 to 4). Figures 16.3 and 16.4 show the block diagram of the transmit/receive unit. UARTi has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous serial I/O mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses 036016, 036816, 033816, 032816 and 02F816) determine whether UARTi is used as a clock synchronous serial I/O or as a UART. Although a few functions are different, UART0 to UART4 have almost the same functions. UART2 to UART4, in particular, are compliant with the SIM interface with some extra settings added in clock-asynchronous serial I/O mode (Note). It also has the bus collision detection function that generates an interrupt request if the TxD pin and the RxD pin are different in level. Table 16.1 shows the comparison of functions of UART0 to UART4, and Figures 16.5 through 16.11 show the registers related to UARTi. Note: SIM : Subscriber Identity Module Table 16.1 Comparison of functions of UART0 to UART4 Function CLK polarity selection UART0 UART1 UART2 UART3 Possible Possible Possible (Note 1) UART4 Possible Possible Possible (Note 1) (Note 1) Possible (Note 1) Possible(Note 1) Possible LSB first / MSB first selection Possible (Note 1) Possible(Note 1) Possible(Note 2) Continuous receive mode selection Transfer clock output from multiple pins selection Separate CTS/RTS pins Serial data logic switch Sleep mode selection TxD, RxD I/O polarity switch TxD, RxD port output format Parity error signal output Bus collision detection Possible (Note 1) Impossible Possible Impossible Possible(Note 3) Impossible CMOS output Impossible Impossible Possible(Note 1) Possible(Note 1) Possible(Note 1) Impossible Impossible Impossible Impossible Possible (Note 4) (Note 2) (Note 2) (Note 1) (Note 1) Impossible Impossible Possible (Note 4) Impossible Impossible Possible (Note 4) Possible (Note 3) Impossible Impossible CMOS output Impossible Impossible Possible Impossible Possible Impossible Possible CMOS output Possible Possible (Note 4) N-channel open CMOS output drain output Possible(Note 4) Possible Possible Possible (Note 4) Note 1: Only when clock synchronous serial I/O mode. Note 2: Only when clock synchronous serial I/O mode and 8-bit UART mode. Note 3: Only when UART mode. Note 4: Using for SIM interface. Rev.1.00 Aug. 02, 2005 Page 124 of 329 REJ09B0187-0100 M16C/80 Group 16. Serial I/O (UART0) RxD0 UART reception TxD0 1/16 Clock source selection f1 f8 f32 Internal Bit rate generator Clock synchronous type 1/16 Reception control circuit Receive clock Transmit/ receive unit 1 / (n0+1) External UART transmission Clock synchronous type Transmission control circuit Transmit clock Clock synchronous type 1/2 (when internal clock is selected) Clock synchronous type (when internal clock is selected) CLK0 CLK polarity reversing circuit CTS/RTS disabled CTS/RTS selected Clock synchronous type (when external clock is selected) CTS0 / RTS0 CTS0 from UART1 CTS/RTS separated CTS/RTS disabled Vss RTS0 CTS0 (UART1) RxD1 Clock source selection f1 f8 f32 Internal Bit rate generator 1/16 TxD1 UART reception Reception control circuit Receive clock Transmit/ receive unit Clock synchronous type UART transmission 1/16 1 / (n1+1) External Clock synchronous type Clock synchronous type 1/2 (when internal clock is selected) Transmission control circuit Transmit clock CLK1 CLK polarity reversing circuit Clock synchronous type (when internal clock is selected) Clock synchronous type (when external clock is selected) CTS1 / RTS1 / CTS0 / CLKS1 CTS/RTS disabled CTS/RTS separated Clock output pin select switch CTS/RTS disabled RTS1 CTS1 VSS CTS0 (UART2) RxD2 RxD polarity reversing circuit 1/16 CTS0 to UART0 TxD polarity reversing circuit Transmit/ receive unit TxD2 UART reception Clock source selection f1 f8 f32 Internal Bit rate generator Clock synchronous type UART transmission 1/16 Reception control circuit Receive clock 1 / (n2+1) External Clock synchronous type Clock synchronous type 1/2 Transmission control circuit Transmit clock (when internal clock is selected) CLK2 CLK polarity reversing circuit Clock synchronous type (when internal clock is selected) Clock synchronous type (when external clock is selected) CTS/RTS selected CTS/RTS disabled CTS2 / RTS2 RTS2 CTS/RTS disabled CTS2 n0 : Values set to UART0 bit rate generator (BRG0) n1 : Values set to UART1 bit rate generator (BRG1) n2 : Values set to UART2 bit rate generator (BRG2) Vss Figure 16.1 Block diagram of UARTi (i = 0 to 2) Rev.1.00 Aug. 02, 2005 Page 125 REJ09B0187-0100 of 329 M16C/80 Group 16. Serial I/O (UART3) RxD3 RxD polarity reversing circuit 1/16 UART reception Clock source selection f1 f8 f32 Internal Bit rate generator Clock synchronous type UART transmission 1/16 Reception control circuit Receive clock TxD polarity reversing circuit Transmit/ receive unit TxD3 1 / (n2+1) External Clock synchronous type Clock synchronous type 1/2 Transmission control circuit Transmit clock (when internal clock is selected) CLK3 CLK polarity reversing circuit Clock synchronous type (when internal clock is selected) Clock synchronous type (when external clock is selected) CTS/RTS selected CTS/RTS disabled CTS3 / RTS3 CTS/RTS disabled RTS3 CTS3 Vss (UART4) RxD4 RxD polarity reversing circuit UART reception 1/16 Clock source selection f1 f8 f32 Internal Bit rate generator Clock synchronous type UART transmission 1/16 Reception control circuit Receive clock Transmit clock TxD polarity reversing circuit Transmit/ receive unit TxD4 1 / (n2+1) External Clock synchronous type Clock synchronous type 1/2 Transmission control circuit (when internal clock is selected) CLK4 CLK polarity reversing circuit Clock synchronous type (when internal clock is selected) Clock synchronous type (when external clock is selected) CTS/RTS selected CTS/RTS disabled CTS4 / RTS4 CTS/RTS disabled RTS4 CTS4 n3 : Values set to UART3 bit rate generator (BRG3) n4 : Values set to UART4 bit rate generator (BRG4) Vss Figure 16.2 Block diagram of UARTi (i = 3, 4) Rev.1.00 Aug. 02, 2005 Page 126 of 329 REJ09B0187-0100 M16C/80 Group 16. Serial I/O Clock synchronous type UART (7 bits) UART (8 bits) 1SP SP SP 2SP PAR PAR disabled Clock synchronous type UART (7 bits) UARTi receive register RxDi PAR enabled UART UART (9 bits) Clock synchronous type UART (8 bits) UART (9 bits) 0 0 0 0 0 0 0 D8 D7 D6 D5 D4 D3 D2 D1 D0 UARTi receive buffer register Address 036616 Address 036716 Address 036E16 Address 036F16 MSB/LSB conversion circuit Data bus high-order bits Data bus low-order bits MSB/LSB conversion circuit D8 D7 D6 D5 D4 D3 D2 D1 D0 UARTi transmit buffer register Address 036216 Address 036316 Address 036A16 Address 036B16 UART (8 bits) UART (9 bits) UART (9 bits) Clock synchronous type 2SP SP SP 1SP PAR PAR enabled UART TxDi PAR disabled Clock synchronous type UART (7 bits) UART (7 bits) UART (8 bits) Clock synchronous type UARTi transmit register "0" SP: Stop bit PAR: Parity bit Figure 16.3 Block diagram of UARTi (i = 0, 1) transmit/receive unit Rev.1.00 Aug. 02, 2005 Page 127 REJ09B0187-0100 of 329 M16C/80 Group 16. Serial I/O No reverse RxDi RxD data reverse circuit Reverse Clock synchronous type 1SP SP 2SP SP PAR PAR disabled Clock synchronous type UART (7 bits) UART (8 bits) UART(7 bits) UARTi receive register PAR enabled UART UART (9 bits) Clock synchronous type UART (8 bits) UART (9 bits) 0 0 0 0 0 0 0 D8 D7 D6 D5 D4 D3 D2 D1 D0 UARTi receive buffer register Address 033E16 Address 033F16 Address 032E16 Address 032F16 Address 02FE16 Address 02FF16 Logic reverse circuit + MSB/LSB conversion circuit Data bus high-order bits Data bus low-order bits Logic reverse circuit + MSB/LSB conversion circuit D8 D7 D6 D5 D4 D3 D2 D1 D0 UART2 transmit buffer register Address 033A16 Address 033B16 Address 032A16 Address 032B16 Address 02FA16 Address 02FB16 UART (8 bits) UART (9 bits) PAR enabled UART (9 bits) UART Clock synchronous type 2SP SP SP 1SP PAR PAR disabled Clock synchronous type "0" UART (7 bits) UART (8 bits) Clock synchronous type UART(7 bits) UARTi transmit register Error signal output disable No reverse Error signal output circuit Error signal output enable Reverse TxD data reverse circuit TxDi SP : Stop bit PAR : Parity bit i : 2 to 4 Figure 16.4 Block diagram of UARTi (i = 2 to 4) transmit/receive unit Rev.1.00 Aug. 02, 2005 Page 128 of 329 REJ09B0187-0100 M16C/80 Group 16. Serial I/O UARTi transmit buffer register (Note) (b15) b7 (b8) b0 b7 b0 Symbol U0TB U1TB U2TB U3TB U4TB Address 036316, 036216 036B16, 036A16 033B16, 033A16 032B16, 032A16 02FB16, 02FA16 Function When reset Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate RW Transmit data Nothing is assigned. When write, set "0". When read, their contents are indeterminate. Note: Use MOV instruction to write to this register. UARTi receive buffer register (b15) b7 (b8) b0 b7 b0 Symbol U0RB U1RB U2RB U3RB U4RB Bit name Address 036716, 036616 036F16, 036E16 033F16, 033E16 032F16, 032E16 02FF16, 02FE16 When reset Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Function (During UART mode) Receive data RW Bit symbol Function (During clock synchronous serial I/O mode) Receive data Nothing is assigned. When write, set "0". When read, the value of these bits is "0". ABT OER FER PER SUM Arbitration lost detecting flag (Note 2) 0 : Not detected 1 : Detected Invalid 0 : No overrun error 1 : Overrun error found 0 : No framing error 1 : Framing error found 0 : No parity error 1 : Parity error found 0 : No error 1 : Error found Overrun error flag (Note 1) 0 : No overrun error 1 : Overrun error found Framing error flag (Note 1) Invalid Parity error flag (Note 1) Error sum flag (Note 1) Invalid Invalid Note 1: Bits 15 through 12 are set to "0" when the serial I/O mode select bit (bits 2 to 0 at addresses 036016, 036816, 033816, 032816 and 02F816) are set to "0002" or the receive enable bit is set to "0". (Bit 15 is set to "0" when bits 14 to 12 all are set to "0".) Bits 14 and 13 are also set to "0" when the lower byte of the UARTi receive buffer register (addresses 036616, 036E16, 033E16, 032E16 and 02FE16) is read out. Note 2: Arbitration lost detecting flag is allocated to U2RB, U3RB and U4RB and nothing but "0" may be written. Nothing is assigned in bit 11 of U0RB and U1RB. When write, set "0". When read, the value of this bit is "0". UARTi bit rate generator (Note 1, 2) b7 b0 Symbol U0BRG U1BRG U2BRG U3BRG U4BRG Function Address 036116 036916 033916 032916 02F916 When reset Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Values that can be set 0016 to FF16 RW Assuming that set value = n, BRGi divides the count source by n+1 Note 1: Use MOV instruction to write to this register. Note 2: Write a value to this register while transmit/receive halts. Figure 16.5 Serial I/O-related registers (1) Rev.1.00 Aug. 02, 2005 Page 129 REJ09B0187-0100 of 329 M16C/80 Group 16. Serial I/O UARTi transmit/receive mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol UiMR(i=0,1) Address 036016, 036816 When reset 0016 Bit symbol SMD0 SMD1 SMD2 Bit name Serial I/O mode select bit Function (During clock synchronous serial I/O mode) Must be fixed to 001 b2 b1 b0 Function (During UART mode) b2 b1 b0 RW 0 0 0 : Serial I/O invalid 0 1 0 : Must not be set 0 1 1 : Must not be set 1 1 1 : Must not be set 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 0 0 : Serial I/O invalid 0 1 0 : Must not be set 0 1 1 : Must not be set 1 1 1 : Must not be set 0 : Internal clock 1 : External clock (Note 2) 0 : One stop bit 1 : Two stop bits Valid when bit 6 = "1" 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : Sleep mode deselected 1 : Sleep mode selected CKDIR Internal/external clock select bit STPS PRY Stop bit length select bit 0 : Internal clock (Note 1) 1 : External clock (Note 2) Invalid Odd/even parity select bit Invalid PRYE SLEP Parity enable bit Sleep select bit Invalid Set to "0" Note 1: Select CLK output by the corresponding function select registers A, B and C. Note 2: Set the corresponding function select register A to the I/O port. UARTi transmit/receive mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol UiMR (i=2 to 4) Address 033816, 032816, 02F816 When reset 0016 Bit symbol SMD0 SMD1 SMD2 Bit name Serial I/O mode select bit Function (During clock synchronous serial I/O mode) Must be fixed to 001 b2 b1 b0 Function (During UART mode) b2 b1 b0 RW 0 0 0 : Serial I/O invalid 0 1 0 : (Note) 0 1 1 : Must not be set 1 1 1 : Must not be set 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 0 0 : Serial I/O invalid 0 1 0 : Must not be set 0 1 1 : Must not be set 1 1 1 : Must not be set 0 : Internal clock 1 : External clock (Note 3) 0 : One stop bit 1 : Two stop bits Valid when bit 6 = "1" 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : No reverse 1 : Reverse Usually set to "0" CKDIR Internal/external clock select bit STPS PRY Stop bit length select bit 0 : Internal clock (Note 2) 1 : External clock (Note 3) Invalid Odd/even parity select bit Invalid PRYE IOPOL Parity enable bit TxD, RxD I/O polarity reverse bit Invalid 0 : No reverse 1 : Reverse Usually set to "0" Note 1: Bit 2 to bit 0 are set to "0102" when I2C mode is used. Note 2: Select CLK output by the corresponding function select registers A, B and C. Note 3: Set the corresponding function select register A to the I/O port. Figure 16.6 Serial I/O-related registers (2) Rev.1.00 Aug. 02, 2005 Page 130 of 329 REJ09B0187-0100 M16C/80 Group 16. Serial I/O UARTi transmit/receive control register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol UiC0(i=0,1) Bit symbol CLK0 CLK1 CRS Address 036416, 036C16 Bit name When reset 0816 Function (During UART mode) b1 b0 Function (During clock synchronous serial I/O mode) b1 b0 RW BRG count source select bit 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set Valid when bit 4 = "0" 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set Valid when bit 4 = "0" 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) CTS/RTS function select bit TXEPT 0 : Data present in transmit 0 : Data present in transmit register Transmit register empty register (during transmission) (during transmission) flag 1 : No data present in transmit 1 : No data present in transmit register (transmission completed) register (transmission completed) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled 0: TXDi pin is CMOS output 1: TXDi pin is N-channel open drain output CRD NCH CTS/RTS disable bit Data output select bit 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled 0 : TXDi pin is CMOS output 1 : TXDi pin is N-channel open drain output 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge CKPOL CLK polarity select bit Set to "0" UFORM Transfer format select bit 0 : LSB first 1 : MSB first Set to "0" Note 1: Set the corresponding function select register A to I/O port, and port direction register to "0". Note 2: Select RTS output using the corresponding function select registers A and B. UART2 transmit/receive control register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2C0 Bit symbol CLK0 CLK1 CRS CTS/RTS function select bit Bit name BRG count source select bit Address 033C16 When reset 0816 Function (During clock synchronous serial I/O mode) Function (During UART mode) b1 b0 RW b1 b0 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set Valid when bit 4 = "0" 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set Valid when bit 4 = "0" 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) TXEPT 0 : Data present in transmit 0 : Data present in transmit register Transmit register empty register (during transmission) (during transmission) flag 1 : No data present in transmit 1 : No data present in transmit register (transmission completed) register (transmission completed) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled 0: TXDi pin is CMOS output 1: TXDi pin is N-channel open-drain output CRD CTS/RTS disable bit 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled 0 : TXDi pin is CMOS output Nothing is assigned. 1 : value is this bit is When write, set "0". When read, theTXDi pin of N-channel "0". CKPOL CLK polarity select bit open-drain output 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge Set to "0" UFORM Transfer format select bit 0 : LSB first 1 : MSB first (Note 3) 0 : LSB first 1 : MSB first Note 1: Set the corresponding function select register A to I/O port, and port direction register to "0". Note 2: Select RTS output using the corresponding function select registers A and B. Note 3: Only clock synchronous serial I/O mode and 8-bit UART mode are valid. Figure 16.7 Serial I/O-related registers (3) Rev.1.00 Aug. 02, 2005 Page 131 REJ09B0187-0100 of 329 M16C/80 Group 16. Serial I/O UARTi transmit/receive control register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol UiC0(i=3,4) Bit symbol CLK0 CLK1 CRS Address When reset 032C16, 02FC16 0816 Bit name Function (During clock synchronous serial I/O mode) b1 b0 b1 b0 Function (During UART mode) 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set Valid when bit 4 = "0" 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) RW BRG count source select bit 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set Valid when bit 4 = "0" 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) CTS/RTS function select bit TXEPT 0 : Data present in transmit 0 : Data present in transmit register Transmit register empty register (during transmission) (during transmission) flag 1 : No data present in transmit 1 : No data present in transmit register (transmission completed) register (transmission completed) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled CRD CTS/RTS disable bit 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled NCH Data output select bit 0 : TXDi pin is CMOS output 1 : TXDi pin is N-channel open drain output 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge 0: TXDi pin is CMOS output 1: TXDi pin is N-channel open drain output CKPOL CLK polarity select bit Set to "0" UFORM Transfer format select bit 0 : LSB first 1 : MSB first (Note 3) 0 : LSB first 1 : MSB first Note 1: Set the corresponding function select register A to I/O port, and port direction register to "0". Note 2: Select RTS output using the corresponding function select registers A and B. Note 3: Valid only in clock syncronous serial I/O mode and 8 bits UART mode. Figure 16.8 Serial I/O-related registers (4) Rev.1.00 Aug. 02, 2005 Page 132 of 329 REJ09B0187-0100 M16C/80 Group 16. Serial I/O UARTi transmit/receive control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol UiC1(i=0,1) Address 036516,036D16 When reset 0216 Bit symbol TE TI Bit name Transmit enable bit Transmit buffer empty flag Function (During clock synchronous serial I/O mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register Function (During UART mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register RW RE RI Receive enable bit Receive complete flag Nothing is assigned. When write, set "0". When read, the value of these bits is "0". UARTi transmit/receive control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol UiC1 (i=2 to 4) Address 033D16, 032D16, 02FD16 When reset 0216 Bit symbol TE TI Bit name Transmit enable bit Transmit buffer empty flag Function (During clock synchronous serial I/O mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : Transmit buffer empty (TI = 1) 1 : Transmit is completed (TXEPT = 1) 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled 0 : No reverse 1 : Reverse Set to "0" Function (During UART mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : Transmit buffer empty (TI = 1) 1 : Transmit is completed (TXEPT = 1) Set to "0" RW RE RI Receive enable bit Receive complete flag UiIRS UARTi transmit interrupt cause select bit UiRRM UARTi continuous receive mode enable bit UiLCH UiERE Data logic select bit Error signal output enable bit 0 : No reverse 1 : Reverse 0 : Output disabled 1 : Output enabled Figure 16.9 Serial I/O-related registers (5) Rev.1.00 Aug. 02, 2005 Page 133 REJ09B0187-0100 of 329 M16C/80 Group 16. Serial I/O UART transmit/receive control register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol UCON Address 037016 When reset X0XX00002 Bit symbol U0IRS Bit name UART0 transmit interrupt cause select bit UART1 transmit interrupt cause select bit Function (During clock synchronous serial I/O mode) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) Function (During UART mode) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) RW U1IRS 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) U0RRM UART0 continuous receive mode enable bit 0 : Continuous receive mode disabled 1 : Continuous receive mode enable 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled Set to "0" U1RRM UART1 continuous receive mode enable bit Set to "0" Nothing is assigned. When write, set "0". When read, its content is indeterminate. RCSP Separate CTS/RTS bit 0 : CTS/RTS shared pin 1 : CTS/RTS separated 0 : CTS/RTS shared pin 1 : CTS/RTS separated Nothing is assigned. When write, set "0". When read, its content is indeterminate. UARTi special mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol UiSMR (i=2 to 4) Address 033716, 032716, 02F716 When reset 0016 Bit symbol IICM ABC BBS LSYN Bit name IIC mode select bit Arbitration lost detecting flag control bit Bus busy flag SCLL sync output enable bit Bus collision detect sampling clock select bit Auto clear function select bit of transmit enable bit Transmit start condition select bit Function (During clock synchronous serial I/O mode) 0 : Normal mode 1 : IIC mode 0 : Update per bit 1 : Update per byte 0 : STOP condition detected 1 : START condition detected Function (During UART mode) Set to "0" Set to "0" Set to "0" RW (Note1) 0 : Disabled 1 : Enabled Set to "0" Set to "0" 0 : Rising edge of transfer clock 1 : Underflow signal of timer Ai (Note 2) ABSCS ACSE Set to "0" 0 : No auto clear function 1 : Auto clear at occurrence of bus collision 0 : Ordinary 1 : Falling edge of RxDi SSS Set to "0" Nothing is assigned. When write, set "0". When read, its content is indeterminate. Note 1: Nothing but "0" may be written. Note 2: UART2 : timer A0 underflow signal, UART3 : timer A3 underflow signal, UART4 : timer A4 underflow signal. Figure 16.10 Serial I/O-related registers (6) Rev.1.00 Aug. 02, 2005 Page 134 of 329 REJ09B0187-0100 M16C/80 Group 16. Serial I/O UARTi special mode register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol UiSMR2 (i=2 to 4) Address 033616, 032616, 02F616 When reset 0016 Bit symbol IICM2 Bit name IIC mode select bit 2 Function 0 : NACK/ACK interrupt DMA source - ACK Transfer to receive buffer at the rising edge of last bit of receive clock Receive interrupt is occurred at the rising edge of last bit of receive clock 1 : UART transfer/receive interrupt DMA source - UART receive Transfer to receive buffer at the falling edge of last bit of receive clock Receive interrupt is occurred at the falling edge of last bit of receive clock 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : UARTi clock 1 : 0 output 0 : Enabled 1 : Disabled (high impedance) Must set to "1" in selecting IIC mode. RW CSC SWC Clock synchronous bit SCL wait output bit ALS SDA output stop flag STC UARTi initialize bit SWC2 SCL wait output bit 2 SDHI SHTC SDA output inhibit bit Start/stop condition control bit Figure 16.11 Serial I/O-related registers (7) Rev.1.00 Aug. 02, 2005 Page 135 REJ09B0187-0100 of 329 M16C/80 Group 16. Serial I/O UART2 special mode register 3 b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2SMR3 Bit symbol Address 033516 When reset 000XXXXX2 Bit name Function RW Nothing is assigned. These bits can neither be set nor reset. When read, their contents are indeterminate. DL0 SDA2(TxD2) digital delay time set bit (Note 1,2) b7 b6 b5 DL1 DL2 000:Without delay 001:1 to 2 cycles of 1/f(XIN) 010:2 to 3 cycles of 1/f(XIN) 011:3 to 4 cycles of 1/f(XIN) 100:4 to 5 cycles of 1/f(XIN) 101:5 to 6 cycles of 1/f(XIN) 110:6 to 7 cycles of 1/f(XIN) 111:7 to 8 cycles of 1/f(XIN) Note 1: These bits are used for SDA2(TxD2) output digital delay when using UART2 for IIC interface. Otherwise, must set to "000". Note 2: When external clock is selected, delay is increased approx. 100ns. UARTi special mode register 3 (i=3,4) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U3SMR3 U4SMR3 Bit symbol Address 032516 02F516 When reset 000000002 000000002 Bit name Function RW SSE CKPH DINC SS port function enable bit 0: SS function disable (Note 3) 1: SS function enable Clock phase set bit Serial input port set bit 0: Without clock delay 1: With clock delay 0: Select TxDi and RxDi (master mode) (Note 5) 1: Select STxDi and SRxDi (slave mode) (Note 6) 0: CLKi is CMOS output 1: CLKi is N-channel open drain output 0: Without fault error 1: With fault error b7 b6 b5 NODC ERR Clock output select bit Fault error flag SDAi(TxD2) digital delay time set bit (Note 1,2) (Note 4) DL0 DL1 DL2 000 :Without delay 001 :1 to 2 cycles of 1/f(XIN) 010 :2 to 3 cycles of 1/f(XIN) 011 :3 to 4 cycles of 1/f(XIN) 100 :4 to 5 cycles of 1/f(XIN) 101 :5 to 6 cycles of 1/f(XIN) 110 :6 to 7 cycles of 1/f(XIN) 111 :7 to 8 cycles of 1/f(XIN) Note 1: These bits are used for SDAi(TxDi) output digital delay when using UARTi for IIC interface. Otherwise, must set to "000". Note 2: When external clock is selected, delay is increased approx. 100ns. Note 3: Set SS function after setting CTS/RTS disable bit (bit 4 of UARTi transfer/receive control register 0) to "1". Note 4: Nothing but "0" may be written. Note 5: Set CLKi and TxDi both for output using the CLKi and TxDi function select register A. Set the RxDi function select register A for input/output port and the port direction register to "0". Note 6: Set STxDi for output using the STxDi function select registers A and B. Set the CLKi and SRxDi function select register A for input/output port and the port direction register to "0". Figure 16.12 Serial I/O-related registers (8) Rev.1.00 Aug. 02, 2005 Page 136 of 329 REJ09B0187-0100 M16C/80 Group 17. Clock synchronous serial I/O mode 17. Clock synchronous serial I/O mode The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Tables 17.1 and 17.2 list the specifications of the clock synchronous serial I/O mode. Figure 17.1 shows the UARTi transmit/receive mode register. Table 17.1 Specifications of clock synchronous serial I/O mode (1) Item Specification Transfer data format * Transfer data length: 8 bits Transfer clock * When internal clock is selected (bit 3 at addresses 036016, 036816, 033816, 032816, 02F816 = "0") : fi/ 2(n+1) (Note) fi = f1, f8, f32 _ CLK is selected by the corresponding port function select register, peripheral function select register and peripheral subfunction select register. * When external clock is selected (bit 3 at addresses 036016, 036816, 033816 , 032816, 02F816= "1") : Input from CLKi pin _ Set the corresponding function select register A to I/O port _______ _______ _______ _______ Transmission/reception control * CTS function/RTS function/CTS, RTS function chosen to be invalid Transmission start condition * To start transmission, the following requirements must be met: _ Transmit enable bit (bit 0 at addresses 036516, 036D16, 033D16, 032D16, 02FD16) = "1" _ Transmit buffer empty flag (bit 1 at addresses 036516, 036D16, 033D16, 032D16, 02FD16) = "0" _______ _______ _ When CTS function selected, CTS input level = "L" _ TxD output selected by the corresponding function select register A, B and C. * Furthermore, if external clock is selected, the following requirements must also be met: _ CLKi polarity select bit (bit 6 at addresses 036416, 036C16, 033C16, 032C16, 02FC16) = "0": CLKi input level = "H" _ CLKi polarity select bit (bit 6 at addresses 036416, 036C16, 033C16, 032C16, 02FC16) = "1": CLKi input level = "L" Reception start condition * To start reception, the following requirements must be met: _ Receive enable bit (bit 2 at addresses 036516, 036D16, 033D16, 032D16, 02FD16) = "1" _ Transmit enable bit (bit 0 at addresses 036516, 036D16, 033D16, 032D16, 02FD16) = "1" _ Transmit buffer empty flag (bit 1 at addresses 036516, 036D16, 033D16, 032D16, 02FD16) = "0" * Furthermore, if external clock is selected, the following requirements must also be met: _ CLKi polarity select bit (bit 6 at addresses 036416, 036C16, 033C16, 032C16, 02FC16) = "0": CLKi input level = "H" _ CLKi polarity select bit (bit 6 at addresses 036416, 036C16, 033C16, 032C16, 02FC16) = "1": CLKi input level = "L" * When transmitting _ Transmit interrupt cause select bit (bits 0, 1 at address 037016, bit 4 at address Interrupt request 033D16, 032D16, 02FD16) = "0": Interrupts requested when data transfer from generation timing UARTi transfer buffer register to UARTi transmit register is completed _ Transmit interrupt cause select bit (bits 0, 1 at address 037016, bit 4 at address 033D16, 032D16, 02FD16) = "1": Interrupts requested when data transmission from UARTi transfer register is completed * When receiving _ Interrupts requested when data transfer from UARTi receive register to UARTi receive buffer register is completed Note : "n" denotes the value 0016 to FF16 that is set to the UART bit rate generator. Rev.1.00 Aug. 02, 2005 Page 137 REJ09B0187-0100 of 329 M16C/80 Group 17. Clock synchronous serial I/O mode Table 17.2 Specifications of clock synchronous serial I/O mode (2) Item Error detection Specification * Overrun error (Note 1) This error occurs when the next data is ready before contents of UARTi receive buffer register are read out * CLK polarity selection Whether transmit data is output/input at the rising edge or falling edge of the transfer clock can be selected * LSB first/MSB first selection Whether transmission/reception begins with bit 0 or bit 7 can be selected * Continuous receive mode selection Reception is enabled simultaneously by a read from the receive buffer register * Transfer clock output from multiple pins selection (UART1) (Note 2) UART1 transfer clock can be chosen by software to be output from one of the two pins set _______ _______ * Separate CTS/RTS pins (UART0) (Note 2) _______ _______ UART0 CTS and RTS pins each can be assigned to separate pins * Switching serial data logic (UART2 to UART4) Whether to reverse data in writing to the transmission buffer register or reading the reception buffer register can be selected. * TxD, RxD I/O polarity reverse (UART2 to UART4) This function is reversing TxD port output and RxD port input. All I/O data level is reversed. Select function Note 1: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that the UARTi receive interrupt request bit will not change. _______ _______ Note 2: The transfer clock output from multiple pins and the separate CTS/RTS pins functions cannot be selected simultaneously. Rev.1.00 Aug. 02, 2005 Page 138 of 329 REJ09B0187-0100 M16C/80 Group 17. Clock synchronous serial I/O mode UARTi transmit/receive mode registers b7 b6 b5 b4 b3 b2 b1 b0 0 001 Symbol UiMR(i=0,1) Bit symbol SMD0 SMD1 SMD2 CKDIR STPS PRY PRYE SLEP Address 036016, 036816 Bit name When reset 0016 Function b2 b1 b0 RW Serial I/O mode select bit 0 0 1 : Clock synchronous serial I/O mode 0 : Internal clock (Note 1) 1 : External clock (Note 2) Internal/external clock select bit Invalid in clock synchronous serial I/O mode 0 (Set to "0" in clock synchronous serial I/O mode) Note 1: Select CLK output by the corresponding function select registers A, B and C. Note 2: Set the corresponding function select register A to the I/O port. UART2 transmit/receive mode register b7 b6 b5 b4 b3 b2 b1 b0 0 001 Symbol UiMR (i=2 to 4) Bit symbol SMD0 SMD1 SMD2 CKDIR STPS PRY PRYE IOPOL Address 033816, 032816, 02F816 Bit name When reset 0016 Function RW Serial I/O mode select bit b2 b1 b0 0 0 1 : Clock synchronous serial I/O mode 0 : Internal clock (Note 2) 1 : External clock (Note 3) Internal/external clock select bit Invalid in clock synchronous serial I/O mode TxD, RxD I/O polarity reverse bit (Note 1) 0 : No reverse 1 : Reverse Note 1: Usually set to "0". Note 2: Select CLK output by the corresponding function select registers A, B and C. Note 3: Set the corresponding function select register A to the I/O port. Figure 17.1 UARTi transmit/receive mode register in clock synchronous serial I/O mode Rev.1.00 Aug. 02, 2005 Page 139 REJ09B0187-0100 of 329 M16C/80 Group 17. Clock synchronous serial I/O mode Table 17.3 lists the functions of the input/output pins during clock synchronous serial I/O mode. This _______ table shows the pin functions when the transfer clock output from multiple pins and the separate CTS/ _______ RTS pins functions are not selected. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a "H". (If the N-channel open drain is selected, this pin is in floating state.) Table 17.3 Input/output pin functions in clock synchronous serial I/O mode Pin name Function Method of selection (Outputs dummy data when performing reception only) TxDi Serial data output (P63, P67, P70, (Note 1) P92, P96) RxDi Serial data input (P62, P66, P71, (Note 2) P91, P97) Transfer clock output CLKi (P61, P65, P72, (Note 1) P90, P95) Transfer clock input (Note 2) Port P62, P66, P71, P91 and P97 direction register (bits 2 and 6 at address 03C216, bit 1 at address 03C316, bit 1 and 7 at address 03C716)= "0" (Can be used as an input port when performing transmission only) Internal/external clock select bit (bit 3 at addresses 036016, 036816, 033816, 032816, 02F816) = "0" Internal/external clock select bit (bit 3 at addresses 036016, 036816, 033816, 032816, 02F816) = "1" Port P61, P65, P72, P90 and P95 direction register (bits 1 and 5 at address 03C216, bit 2 at address 03C316, bit 0 and 5 at address 03C716) = "0" CTS/RTS disable bit (bit 4 at addresses 036416, 036C16, 033C16, 032C16, 02FC16) ="0" CTS/RTS function select bit (bit 2 at addresses 036416, 036C16, 033C16, 032C16, 02FC16) = "0" Port P60, P64, P73, P93 and P94 direction register (bits 0 and 4 at address 03C216, bit 3 at address 03C316, bits 3 and 4 at address 03C716) = "0" CTS/RTS disable bit (bit 4 at addresses 036416, 036C16, 033C16, 032C16, 02FC16) = "0" CTS/RTS function select bit (bit 2 at addresses 036416, 036C16, 033C16, 032C16, 02FC16) = "1" CTS/RTS disable bit (bit 4 at addresses 036416, 036C16, 033C16, 032C16, 02FC16) = "1" _______ _______ ________ CTSi/RTSi CTS input (P60, P64, P73, (Note 2) P93, P94) RTS output (Note 1) Programmable I/O port (Note 2) (when transfer clock output from multiple pins and separate CTS/RTS pins functions are not selected) Note 1: Select TxD output, CLK output and RTS output by the corresponding function select registers A, B and C. Note 2: Select I/O port by the corresponding function select register A. Rev.1.00 Aug. 02, 2005 Page 140 of 329 REJ09B0187-0100 M16C/80 Group 17. Clock synchronous serial I/O mode * Example of transmit timing (when internal clock is selected) Tc Transfer clock "1" "0" "1" "0" Transferred from UARTi transmit buffer register to UARTi transmit register "H" Data is set in UARTi transmit buffer register Transmit enable bit (TE) Transmit buffer empty flag (Tl) CTSi "L" TCLK Stopped pulsing because CTS = "H" Stopped pulsing because transfer enable bit = "0" CLKi TxDi Transmit register empty flag (TXEPT) "1" "0" D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Transmit interrupt "1" request bit (IR) "0" Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings: * Internal clock is selected. * CTS function is selected. * CLK polarity select bit = "0". * Transmit interrupt cause select bit = "0". Tc = TCLK = 2(n + 1) / fi fi: frequency of BRGi count source (f1, f8, f32) n: value set to BRGi * Example of receive timing (when external clock is selected) Receive enable bit (RE) Transmit enable bit (TE) Transmit buffer empty flag (Tl) RTSi "1" "0" "1" "0" "1" "0" "H" "L" Dummy data is set in UARTi transmit buffer register Transferred from UARTi transmit buffer register to UARTi transmit register 1 / fEXT Receive data is taken in CLKi RxDi Receive complete "1" flag (Rl) "0" Receive interrupt request bit (IR) "1" "0" D0 D1 D2 D3 D4 D5 D6 D7 Transferred from UARTi receive register to UARTi receive buffer register D0 D1 D2 D3 D4 D5 Read out from UARTi receive buffer register Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings: * External clock is selected. * RTS function is selected. * CLK polarity select bit = "0". fEXT: frequency of external clock Meet the following conditions are met when the CLKi input before data reception = "H" * Transmit enable bit "1" * Receive enable bit "1" * Dummy data write to UARTi transmit buffer register Figure 17.2 Typical transmit/receive timings in clock synchronous serial I/O mode Rev.1.00 Aug. 02, 2005 Page 141 REJ09B0187-0100 of 329 M16C/80 Group 17. Clock synchronous serial I/O mode (a) Polarity select function As shown in Figure 17.3, the CLK polarity select bit (bit 6 at addresses 036416, 036C16, 033C16, 032C16, 02FC16) allows selection of the polarity of the transfer clock. * When CLK polarity select bit = "0" CLKi TXDi RXDi D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 Note 1: The CLK pin level when not transferring data is "H". * When CLK polarity select bit = "1" CLKi TXDi RXDi D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 Note 2: The CLK pin level when not transferring data is "L". Figure 17.3 Polarity of transfer clock (b) LSB first/MSB first select function As shown in Figure 17.4, when the transfer format select bit (bit 7 at addresses 036416, 036C16, 033C16, 032C16, 02FC16) = "0", the transfer format is "LSB first"; when the bit = "1", the transfer format is "MSB first". * When transfer format select bit = "0" CLKi TXDi RXDi D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 LSB first D7 * When transfer format select bit = "1" CLKi TXDi RXDi D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 MSB first D0 Note: This applies when the CLK polarity select bit = "0". Figure 17.4 Transfer format Rev.1.00 Aug. 02, 2005 Page 142 of 329 REJ09B0187-0100 M16C/80 Group 17. Clock synchronous serial I/O mode (c) Transfer clock output from multiple pins function (UART1) This function allows the setting two transfer clock output pins and choosing one of the two to output a clock by using the port function select register (bits of related to-P64 and P65). (See Figure 17.5) The multiple pins function is valid only when the internal clock is selected for UART1. Note that when this _______ _______ function is selected, UART1 CTS/RTS function cannot be used. Microcomputer TXD1 (P67) CLKS1 (P64) CLK1 (P65) IN CLK IN CLK Note: This applies when the internal clock is selected and transmission is performed only in clock synchronous serial I/O mode. Figure 17.5 The transfer clock output from the multiple pins function usage (d) Continuous receive mode If the continuous receive mode enable bit (bits 2 and 3 at address 037016, bit 5 at address 033D16, 032D16, 02FD16) is set to "1", the unit is placed in continuous receive mode. In this mode, when the receive buffer register is read out, the unit simultaneously goes to a receive enable state without having to set dummy data to the transmit buffer register back again. _______ _______ (e) Separate CTS/RTS pins function (UART0) This function works the same way as in the clock asynchronous serial I/O (UART) mode. The method of setting and the input/output pin functions are both the same, so refer to select function in the next section, "(2) Clock asynchronous serial I/O (UART) mode." Note that this function is invalid if the transfer clock output from the multiple pins function is selected. (f) Serial data logic switch function (UART2 to UART4) When the data logic select bit (bit6 at address 033D16, 032D16, 02FD16) = "1", and writing to transmit buffer register or reading from receive buffer register, data is reversed. Figure 17.6 shows the example of serial data logic switch timing. *When LSB first Transfer clock TxDi TxDi "H" "L" "H" (no reverse) "L" "H" D0 D1 D2 D3 D4 D5 D6 D7 (reverse) "L" D0 D1 D2 D3 D4 D5 D6 D7 Figure 17.6 Serial data logic switch timing Rev.1.00 Aug. 02, 2005 Page 143 REJ09B0187-0100 of 329 M16C/80 Group 18. Clock asynchronous serial I/O (UART) mode 18. Clock asynchronous serial I/O (UART) mode The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. Tables 18.1 and 18.2 list the specifications of the UART mode. Figure 18.1 shows the UARTi transmit/receive mode register. Table 18.1 Specifications of UART Mode (1) Item Specification Transfer data format * Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected * Start bit: 1 bit * Parity bit: Odd, even, or nothing as selected * Stop bit: 1 bit or 2 bits as selected Transfer clock * When internal clock is selected (bit 3 at addresses 036016, 036816, 033816, 032816, 02F816 = "0") : fi/16(n+1) (Note 1) fi = f1, f8, f32 * When external clock is selected (bit 3 at addresses 036016, 036816, 033816, 032816, 02F816 ="1") : fEXT/16(n+1)(Note 1) (Note 2) _______ _______ _______ _______ Transmission/reception control * CTS function/RTS function/CTS, RTS function chosen to be invalid Transmission start condition * To start transmission, the following requirements must be met: - Transmit enable bit (bit 0 at addresses 036516, 036D16, 033D16, 032D16, 02FD16) = "1" - Transmit buffer empty flag (bit 1 at addresses 036516, 036D16, 033D16, 032D16, 02FD16) = "0" _______ _______ - When CTS function selected, CTS input level = "L" - TxD output is selected by the corresponding function select register A, B and C. Reception start condition * To start reception, the following requirements must be met: - Receive enable bit (bit 2 at addresses 036516, 036D16, 033D16, 032D16, 02FD16) = "1" - Start bit detection Interrupt request * When transmitting generation timing - Transmit interrupt cause select bits (bits 0,1 at address 037016, bit 4 at address 033D16, 032D16, 02FD16) = "0": Interrupts requested when data transfer from UARTi transfer buffer register to UARTi transmit register is completed - Transmit interrupt cause select bits (bits 0, 1 at address 037016, bit 4 at address 033D16, 032D16, 02FD16) = "1": Interrupts requested when data transmission from UARTi transfer register is completed * When receiving - Interrupts requested when data transfer from UARTi receive register to UARTi receive buffer register is completed Note 1: `n' denotes the value 0016 to FF16 that is set to the UARTi bit rate generator. Note 2: fEXT is input from the CLKi pin. Rev.1.00 Aug. 02, 2005 Page 144 of 329 REJ09B0187-0100 M16C/80 Group 18. Clock asynchronous serial I/O (UART) mode Table 18.2 Specifications of UART Mode (2) Item Specification Error detection * Overrun error (Note) This error occurs when the next data is ready before contents of UARTi receive buffer register are read out * Framing error This error occurs when the number of stop bits set is not detected * Parity error This error occurs when if parity is enabled, the number of 1's in parity and character bits does not match the number of 1's set * Error sum flag This flag is set (= 1) when any of the overrun, framing, and parity errors is Select function encountered _______ _______ * Separate CTS/RTS pins (UART0) _______ _______ UART0 CTS and RTS pins each can be assigned to separate pins * Sleep mode selection (UART0, UART1) This mode is used to transfer data to and from one of multiple slave microcomputers * Serial data logic switch (UART2 to UART4) This function is reversing logic value of transferring data. Start bit, parity bit and stop bit are not reversed. * TxD, RxD I/O polarity switch (UART2 to UART4) This function is reversing TxD port output and RxD port input. All I/O data level is reversed. Note: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that the UARTi receive interrupt request bit will not change. Rev.1.00 Aug. 02, 2005 Page 145 REJ09B0187-0100 of 329 M16C/80 Group 18. Clock asynchronous serial I/O (UART) mode UARTi transmit / receive mode registers b7 b6 b5 b4 b3 b2 b1 b0 Symbol UiMR(i=0,1) Address 036016, 036816 When reset 0016 Bit symbol SMD0 SMD1 SMD2 CKDIR STPS PRY Bit name Serial I/O mode select bit b2 b1 b0 Function 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 : Internal clock 1 : External clock (Note) 0 : One stop bit 1 : Two stop bits Valid when bit 6 = "1" 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : Sleep mode deselected 1 : Sleep mode selected RW Internal / external clock select bit Stop bit length select bit Odd / even parity select bit Parity enable bit Sleep select bit PRYE SLEP Note: Set the corresponding port function select register A to I/O port. UARTi transmit / receive mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol UiMR (i=2 to 4) Address 033816, 032816, 02F816 When reset 0016 Bit symbol SMD0 SMD1 SMD2 CKDIR STPS PRY Bit name Serial I/O mode select bit b2 b1 b0 Function 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 : Internal clock 1 : External clock (Note 2) 0 : One stop bit 1 : Two stop bits Valid when bit 6 = "1" 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : No reverse 1 : Reverse RW Internal / external clock select bit Stop bit length select bit Odd / even parity select bit Parity enable bit TxD, RxD I/O polarity reverse bit (Note 1) PRYE IOPOL Note 1: Usually set to "0". Note 2: Set the corresponding port function select register A to I/O port. Figure 18.1 UARTi transmit/receive mode register in UART mode Rev.1.00 Aug. 02, 2005 Page 146 of 329 REJ09B0187-0100 M16C/80 Group 18. Clock asynchronous serial I/O (UART) mode Table 18.3 lists the functions of the input/output pins during UART mode. This table shows the pin _______ _______ functions when the separate CTS/RTS pins function is not selected. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a "H". (If the N-channel open drain is selected, this pin is in floating state.) Table 18.3 Input/output pin functions in UART mode Pin name TxDi (P63, P67, P70, P92, P96) RxDi (P62, P66, P71, P91, P97) CLKi (P61, P65, P72, P90, P95) Function Serial data output (Note 1) Serial data input (Note 2) Programmable I/O port (Note 2) Transfer clock input (Note 2) Port P62, P66, P71, P91 and P97 direction register (bits 2 and 6 at address 03C216, bit 1 at address 03C316, bit 1 and 7 at address 03C716)= "0" (Can be used as an input port when performing transmission only) Internal/external clock select bit (bit 3 at addresses 036016, 036816, 033816, 032816, 02F816) = "0" Internal/external clock select bit (bit 3 at addresses 036016, 036816, 033816, 032816, 02F816) = "1" Port P61, P65, P72, P90 and P95 direction register (bits 1 and 5 at address 03C216, bit 2 at address 03C316, bits 0 and 5 at address 03C716) = "0" CTS/RTS disable bit (bit 4 at addresses 036416, 036C16, 033C16, 032C16, 02FC16) ="0" CTS/RTS function select bit (bit 2 at addresses 036416, 036C16, 033C16, 032C16, 02FC16) = "0" Port P60, P64, P73, P93 and P94 direction register (bits 0 and 4 at address 03C216, bit 3 at address 03C316, bits 3 and 4 at address 03C716) = "0" CTS/RTS disable bit (bit 4 at addresses 036416, 036C16, 033C16, 032C16, 02FC16) = "0" CTS/RTS function select bit (bit 2 at addresses 036416, 036C16, 033C16, 032C16, 02FC16) = "1" CTS/RTS disable bit (bit 4 at addresses 036416, 036C16, 033C16, 032C16, 02FC16) = "1" ________ Method of selection CTSi/RTSi (P60, P64, P73, P93, P94) CTS input (Note 2) RTS output (Note 1) Programmable I/O port (Note 2) ________ _______ (When separate CTS/RTS pins function is not selected) Note 1: Select TxD output, CLK output and RTS output by the corresponding function select registers A, B and C. Note 2: Select I/O port by the corresponding function select register A. Rev.1.00 Aug. 02, 2005 Page 147 REJ09B0187-0100 of 329 M16C/80 Group 18. Clock asynchronous serial I/O (UART) mode * Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) The transfer clock stops momentarily as CTS is "H" when the stop bit is checked. The transfer clock starts as the transfer starts immediately CTS changes to "L". Tc Transfer clock Transmit enable bit(TE) Transmit buffer empty flag(TI) "1" "0" "1" "0" Data is set in UARTi transmit buffer register. Transferred from UARTi transmit buffer register to UARTi transmit register "H" CTSi "L" Start bit TxDi "1" Transmit register empty flag (TXEPT) "0" "1" "0" Parity bit P Stop bit SP Stopped pulsing because transmit enable bit = "0" ST D0 D1 ST D0 D1 D2 D3 D4 D5 D6 D7 ST D0 D1 D2 D3 D4 D5 D6 D7 P SP Transmit interrupt request bit (IR) Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : * Parity is enabled. * One stop bit. * CTS function is selected. * Transmit interrupt cause select bit = "1". Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of BRGi count source (f1, f8, f32) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi * Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits) Tc Transfer clock Transmit enable bit(TE) Transmit buffer empty flag(TI) "1" "0" "1" "0" Data is set in UARTi transmit buffer register Transferred from UARTi transmit buffer register to UARTi transmit register Start bit TxDi "1" Transmit register empty flag (TXEPT) Stop bit Stop bit ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SPSP ST D0 D1 ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP "0" "1" "0" Transmit interrupt request bit (IR) Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : * Parity is disabled. * Two stop bits. * CTS function is disabled. * Transmit interrupt cause select bit = "0". Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of BRGi count source (f1, f8, f32) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi Figure 18.2 Typical transmit timings in UART mode Rev.1.00 Aug. 02, 2005 Page 148 of 329 REJ09B0187-0100 M16C/80 Group 18. Clock asynchronous serial I/O (UART) mode * Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) BRGi count source Receive enable bit RxDi "1" "0" Start bit Sampled "L" Receive data taken in Transfer clock Receive complete flag RTSi Receive interrupt request bit Reception triggered when transfer clock "1" is generated by falling edge of start bit "0" "H" "L" "1" "0" Cleared to "0" when interrupt request is accepted, or cleared by software The above timing applies to the following settings : *Parity is disabled. *One stop bit. *RTS function is selected. Transferred from UARTi receive register to UARTi receive buffer register Stop bit D0 D1 D7 Figure 18.3 Typical receive timing in UART mode _______ _______ (a) Separate CTS/RTS pins function (UART0) _______ _______ _______ With the separate CTS/RTS bit (bit 6 at address 037016) is set to "1", the unit outputs/inputs the CTS _______ and RTS signals on different pins. (See Figure 18.4) This function is valid only for UART0. Note that _______ _______ if this function is selected, the CTS/RTS function for UART1 cannot be used. _______ _______ _______ _______ Set both CTS/RTS function select bit (bit 2 at address 036C16) of UART1and CTS/RTS disable bit (bit 4 at address 036C16)of UART1 to "0" and set P64 to input port by the function select register. Microcomputer TXD0 (P63) RXD0 (P62) IN OUT IC RTS0 (P60) CTS0 (P64) CTS RTS _______ _______ Figure 18.4 The separate CTS/RTS pins function usage (b) Sleep mode (UART0, UART1) This mode is used to transfer data between specific microcomputers among multiple microcomputers connected using UARTi. The sleep mode is selected when the sleep select bit (bit 7 at addresses 036016, 036816) is set to "1" during reception. In this mode, the unit performs receive operation when the MSB of the received data = "1" and does not perform receive operation when the MSB = "0". Rev.1.00 Aug. 02, 2005 Page 149 REJ09B0187-0100 of 329 M16C/80 Group 18. Clock asynchronous serial I/O (UART) mode (c) Function for switching serial data logic (UART2 to UART4) When the data logic select bit (bit 6 of address 033D16, 032D16, 02FD16) is assigned 1, data is inverted in writing to the transmission buffer register or reading the reception buffer register. Figure 18.5 shows the example of timing for switching serial data logic. * When LSB first, parity enabled, one stop bit Transfer clock TxDi (no reverse) "H" "L" "H" "L" "H" "L" ST D0 D1 D2 D3 D4 D5 D6 D7 P SP TxDi (reverse) ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST : Start bit P : Even parity SP : Stop bit Figure 18.5 Timing for switching serial data logic (d) TxD, RxD I/O polarity reverse function (UART2 to UART4) This function is to reverse TxD pin output and RxD pin input. The level of any data to be input or output (including the start bit, stop bit(s), and parity bit) is reversed. Set this function to "0" (not to reverse) for usual use. (e) Bus collision detection function (UART2 to UART4) This function is to sample the output level of the TxD pin and the input level of the RxD pin at the rising edge of the transfer clock; if their values are different, then an interrupt request occurs. Figure 18.6 shows the example of detection timing of a buss collision (in UART mode). Transfer clock "H" "L" TxDi "H" "L" ST SP RxDi Bus collision detection interrupt request signal Bus collision detection interrupt request bit "H" "L" "1" "0" "1" "0" ST SP ST : Start bit SP : Stop bit Figure 18.6 Detection timing of a bus collision (in UART mode) Rev.1.00 Aug. 02, 2005 Page 150 of 329 REJ09B0187-0100 M16C/80 Group 19. Clock-asynchronous serial I/O mode (compliant with the SIM interface) 19. Clock-asynchronous serial I/O mode (compliant with the SIM interface) The SIM interface is used for connecting the microcomputer with a memory card I/C or the like; adding some extra settings in UART2 to UART4 clock-asynchronous serial I/O mode allows the user to effect this function. Table 19.1 shows the specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface). Table 19.1 Specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface) Item Transfer data format Specification * Transfer data 8-bit UART mode (bit 2 to 0 of addresses 033816, 032816, 02F816 = "1012") * One stop bit (bit 4 of addresses 033816, 032816, 02F816 = "0") * With the direct format chosen Set parity to "even" (bit 5 and 6 of addresses 033816, 032816, 02F816 = "1" and "1" respectively) Set data logic to "direct" (bit 6 of address 033D16, 032D16, 02FD16 = "0"). Set transfer format to LSB (bit 7 of address 033C16, 032C16, 02FC16 = "0"). * With the inverse format chosen Set parity to "odd" (bit 5 and 6 of addresses 033816, 032816, 02F816 = "0" and "1" respectively) Set data logic to "inverse" (bit 6 of address 033D16, 032D16, 02FD16 = "1") Set transfer format to MSB (bit 7 of address 033C16, 032C16, 02FC16 = "1") Transfer clock * With the internal clock chosen (bit 3 of addresses 033816, 032816, 02F816 = "0") : fi / 16 (n + 1) (Note 1) : fi=f1, f8, f32 * With an external clock chosen (bit 3 of addresses 033816, 032816, 02F816 = "1") : fEXT / 16 (n+1) (Note 1) (Note 2) _______ _______ Transmission / reception control * Disable the CTS and RTS function (bit 4 of address 033C16, 032C16, 02FC16 = "1") Other settings * The sleep mode select function is not available for UART2 and UART3 * Set transmission interrupt factor to "transmission completed" (bit 4 of address 033D16, 032D16, 02FD16 = "1") * Set N-channel open drain output to TxD and RxD pins in UART3 and 4 (bit 5 of address 032C16, 02FC16 = "1") Transmission start condition * To start transmission, the following requirements must be met: - Transmit enable bit (bit 0 of address 033D16, 032D16, 02FD16) = "1" - Transmit buffer empty flag (bit 1 of address 033D16, 032D16, 02FD16) = "0" * To start reception, the following requirements must be met: - Reception enable bit (bit 2 of address 033D16, 032D16, 02FD16) = "1" - Detection of a start bit Interrupt request generation timing * When transmitting When data transmission from the UART2 to UART4 transfer register is completed (bit 4 of address 033D16, 032D16, 02FD16 = "1") * When receiving When data transfer from the UART2 to UART4 receive register to the UART2 to UART4 receive buffer register is completed Error detection * Overrun error (see the specifications of clock-asynchronous serial I/O) (Note 3) * Framing error (see the specifications of clock-asynchronous serial I/O) * Parity error (see the specifications of clock-asynchronous serial I/O) - On the reception side, an "L" level is output from the TxDi pin by use of the parity error signal output function (bit 7 of address 033D16, 032D16, 02FD16 = "1") when a parity error is detected - On the transmission side, a parity error is detected by the level of input to the RxDi pin when a transmission interrupt occurs * The error sum flag (see the specifications of clock-asynchronous serial I/O) Note 1: `n' denotes the value 0016 to FF16 that is set to the UARTi bit rate generator. Note 2: fEXT is input from the CLKi pin. Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that the UARTi receive interrupt request bit will not change. Rev.1.00 Aug. 02, 2005 Page 151 REJ09B0187-0100 of 329 Reception start condition M16C/80 Group 19. Clock-asynchronous serial I/O mode (compliant with the SIM interface) Tc Transfer Clock Transmit rnable bit (TE) Transmit enable empty flag (TI) "1" "0" "1" "0" Transferred from the UARTi transmit buffer register to the UARTi transmit register Start bit Parity Stop bit bit D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 An "L" level returns from SIM card due to the occurrence of a parity error SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP P SP Data is set in the UARTi transmit buffer register (Note 1) TxDi RxDi Signal conductor level (Note 2) Transmit register empty flag (TXEPT) Transmit interrupt request bit (IR) "1" "0" "1" "0" ST D0 D1 The level is detected by the interrupt routine ST D0 D1 D2 D3 D4 D5 D6 D7 P The level is detected by the interrupt routine Cleared to "0" when interrupt request is accepted, or cleared by software Shown in () are bit symbols. The above timing applies to the following settings : * Parity is enabled. * One stop bit * Transmit interrupt cause select bit = "1". Tc = 16 ( n + 1 ) / fi or 16 ( n + 1 ) / fEXT fi : frequency of BRGi rcount source (f1, f8, f32) fEXT : frequency of BRGi rcount source (external clock) n : value set to BRGi Tc Transfer Clock Receive enable bit (RE) "1 " "0 " Start bit ST D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop bit bit P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP RxDi TxDi An "L" level returns from TxDi due to the occurrence of a parity error ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP Signal conductor level (Note 2) Transmit register empty flag (TXEPT) Transmit interrupt request bit (IR) "1" "0 " "1" "0" Read to receive buffer Read to receive buffer Cleared to "0" when interrupt request is accepted, or cleared by software Shown in () are bit symbols. The above timing applies to the following settings : * Parity is enabled. * One stop bit * Transmit interrupt cause select bit = "0". Tc = 16 ( n + 1 ) / fi or 16 ( n + 1 ) / fEXT fi : frequency of BRGi rcount source (f1, f8, f32) fEXT : frequency of BRGi rcount source (external clock) n : value set to BRGi Note 1: After writing to the transfer buffer at above timing, transmission starts at the timing of BRG overflow. Note 2: Equal in waveform because TxDi and RxDi are connected. Figure 19.1 Typical transmit/receive timing in UART mode (compliant with the SIM interface) Rev.1.00 Aug. 02, 2005 Page 152 of 329 REJ09B0187-0100 M16C/80 Group 19. Clock-asynchronous serial I/O mode (compliant with the SIM interface) (a) Function for outputting a parity error signal During reception, with the error signal output enable bit (bit 7 of address 033D16, 032D16, 02FD16) assigned "1", you can output an "L" level from the TxDi pin when a parity error is detected. If the UARTi receive buffer register is read while outputting a parity error signal, the parity error flag is cleared to "0" and at the same time the TxDi output is returned high. And during transmission, comparing with the case in which the error signal output enable bit (bit 7 of address 033D16, 032D16, 02FD16) is assigned "0", the transmission completion interrupt occurs in the half cycle later of the transfer clock. Therefore parity error signals can be detected by a transmission completion interrupt program. Figure 19.2 shows the output timing of the parity error signal. * LSB first Transfer clock RxDi TxDi Receive complete flag "H" "L" "H" "L" "H" "L" "1" "0" ST D0 D1 D2 D3 D4 D5 D6 D7 P SP Hi-Z ST : Start bit P : Even Parity SP : Stop bit Figure 19.2 Output timing of the parity error signal (b) Direct format/inverse format Connecting the SIM card allows you to switch between direct format and inverse format. If you choose the direct format, D0 data is output from TxDi. If you choose the inverse format, D7 data is inverted and output from TxDi. Figure 19.3 shows the SIM interface format. Transfer clcck TxDi (direct) TxDi (inverse) D0 D1 D2 D3 D4 D5 D6 D7 P D7 D6 D5 D4 D3 D2 D1 D0 P P : Even parity Figure 19.3 SIM interface format Rev.1.00 Aug. 02, 2005 Page 153 REJ09B0187-0100 of 329 M16C/80 Group 19. Clock-asynchronous serial I/O mode (compliant with the SIM interface) Figure 19.4 shows the example of connecting the SIM interface. Connect TxDi and RxDi and apply pullup. Microcomputer (Note) SIM card TxDi RxDi Note :TxDi pin is N-channel open drain and needs a pull-up resistance. Figure 19.4 Connecting the SIM interface Rev.1.00 Aug. 02, 2005 Page 154 of 329 REJ09B0187-0100 M16C/80 Group 20. UARTi Special Mode Register (i = 2 to 4) 20. UARTi Special Mode Register (i = 2 to 4) UART2 to UART4 operate the IIC bus interface (simple IIC bus) using the UARTi special mode register (addresses 033616, 032616 and 02F616 [i = 2 to 4]) and UARTi special mode register 2 (addresses 033616, 032616 and 02F616 [i = 2 to 4]). UART3 and UART4 add special functions using UARTi special mode resister 3 (addresses 032516 and 02F516 [i = 3 or 4]). (1) IIC Bus Interface Mode The I2C bus interface mode is provided with UART2 to UART4. Table 20.1 shows the construction of the UARTi special mode register and UARTi special mode register 2. When the I2C mode select bit (bit 0 in addresses 033716, 032716 and 02F716) is set to "1", the I2C bus (simple I2C bus) interface circuit is enabled. To use the I2C bus, set the SCLi and the SDAi of both master and slave to output with the function select register. In UART3 and 4, set the data output select bit (bit 5 in address 032C16 and 02FC16) to N-channel open drain output. Table 20.1 shows the relationship of the IIC mode select bit to control. To use the chip in the clock synchronized serial I/O mode or clock asynchronized serial I/O mode, always set this bit to "0". Table 20.1 Features in I2C mode Function 1 2 3 4 5 6 Factor of interrupt number 39 to 41 (Note 2) Factor of interrupt number 33, 35, 37 (Note 2) Factor of interrupt number 34, 36, 38 (Note 2) UARTi transmission output delay P70, P92, P96 at the time when UARTi is in use P71, P91, P97 at the time when UARTi is in use Normal mode Bus collision detection UARTi transmission UARTi reception Not delayed TxDi (output) RxDi (input) CLKi UARTi reception 15ns Reading the terminal when 0 is assigned to the direction register H level (when 0 is assigned to the CLK polarity select bit) I2C mode (Note 1) Start condition detection or stop condition detection No acknowledgment detection (NACK) Acknowledgment detection (ACK) Delayed SDAi (input/output) (Note 3) SCLi (input/output) P72, P90, P95 Acknowledgment detection (ACK) 50ns Reading the terminal regardless of the value of the direction register The value set in latch P70, P92, P96 when the port is selected (Note 3) 7 P72, P90, P95 at the time when UARTi is in use 8 9 DMA1 factor at the time when 1 1 0 1 is assigned to the DMA request factor selection bits Noise filter width 10 Reading P71, P91, P97 11 Initial value of UARTi output Note 1: Make the settings given below when I2C mode is in use. Set 0 1 0 in bits 2, 1, 0 of the UARTi transmission/reception mode register. Disable the RTS/CTS function. Choose the MSB First function. Note 2: Follow the steps given below to switch from a factor to another. 1. Disable the interrupt of the corresponding number. 2. Switch from a factor to another. 3. Reset the interrupt request flag of the corresponding number. 4. Set an interrupt level of the corresponding number. Note 3: Set an initial value of SDA transmission output when IIC mode (IIC mode select bit = "1") is valid and serial I/O is invalid. Rev.1.00 Aug. 02, 2005 Page 155 REJ09B0187-0100 of 329 M16C/80 Group 20. UARTi Special Mode Register (i = 2 to 4) UARTi special mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol UiSMR (i=2 to 4) Address 033716, 032716, 02F716 When reset 0016 Bit symbol IICM ABC BBS LSYN ABSCS Bit name I 2C mode select bit Arbitration lost detecting flag control bit Bus busy flag SCLL sync output enable bit Bus collision detect sampling clock select bit Auto clear function select bit of transmit enable bit Transmit start condition select bit Function (During clock synchronous serial I/O mode) 0 : Normal mode 1 : I2 C mode 0 : Update per bit 1 : Update per byte 0 : STOP condition detected 1 : START condition detected Function (During UART mode) Set to "0" Set to "0" Set to "0" RW (Note 1) 0 : Disabled 1 : Enabled Set to "0" Set to "0" 0 : Rising edge of transfer clock (Note 2) 1 : Underflow signal of timer Ai 0 : No auto clear function 1 : Auto clear at occurrence of bus collision 0 : Ordinary 1 : Falling edge of RxDi ACSE Set to "0" SSS Set to "0" Nothing is assigned. When write, set "0". When read, the content is "0". Note 1: Nothing but "0" may be written. Note 2: UART2 : timer A0 underflow signal, UART3 : timer A3 underflow signal, UART4 : timer A4 underflow signal. UARTi special mode register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol UiSMR2 (i=2 to 4) Address 033616, 032616, 02F616 When reset 0016 Bit symbol IICM2 CSC SWC Bit name IIC mode select bit 2 Clock synchronous bit SCL wait output bit Refer to Table 20.2 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : UARTi clock 1 : 0 output Function RW ALS SDA output stop flag STC SWC2 UARTi initialize bit SCL wait output bit 2 SDHI SHTC SDA output inhibit bit Start/stop condition control bit 0 : Enabled 1 : Disabled (high impedance) Set to "1" in selecting IIC mode. Figure 20.1 UART2 special mode register Rev.1.00 Aug. 02, 2005 Page 156 of 329 REJ09B0187-0100 M16C/80 Group 20. UARTi Special Mode Register (i = 2 to 4) P70/TXD2/SDA Timer Selector I/O UART2 IICM=1 delay IICM=0 SDHI ALS D Q T To DMAi UART2 transmission/NACK interrupt request IICM=0 or IICM2=1 Transmission register UART2 IICM=1 and IICM2=0 Arbitration IICM=1 Reception register IICM=0 UART2 IICM=1 and IICM2=0 IICM=0 or IICM2=1 To DMAi UART2 reception/ACK interrupt request DMAi request Noize Filter Start condition detection S R Q Bus busy Stop condition detection L-synchronous output enabling bit R DQ T DQ T NACK Falling edge detection P71/RXD2/SCL I/0 Selector UART2 IICM=1 Noize Filter Noize Filter Data register Internal clock SWC2 External clock CLK control ACK IICM=1 Bus collision/start, stop condition detection interrupt request 9th pulse IICM=1 Bus collision detection UART2 IICM=0 IICM=0 R S Falling edge of 9th pulse SWC Port reading P72/CLK2 Serector UART2 IICM=0 I/0 Timer * With IICM set to 1, the port terminal is to be readable even if 1 is assigned to P71 of the direction register. Figure 20.2 Functional block diagram for I2C mode Figure 20.2 is a block diagram of the IIC bus interface. To explain the control bit of the IIC bus interface, UART2 is used as an example. UART2 Special Mode Register (Address 033716) Bit 0 is the IIC mode select bit. When set to "1", ports P70, P71 and P72 operate respectively as the SDA2 data transmission-reception pin, SCL2 clock I/O pin and port P72. A delay circuit is added to SDA2 transmission output, therefore after SCL2 is sufficiently L level, SDA2 output changes. Port P71 (SCL2) is designed to read pin level regardless of the content of the port direction register. SDA2 transmission output is initially set to port P70 in this mode. Furthermore, interrupt factors for the bus collision detection interrupt, UART2 transmission interrupt and UART2 reception interrupt change respectively to the start/stop condition detection interrupts, acknowledge non-detection interrupt and acknowledge detection interrupt. Rev.1.00 Aug. 02, 2005 Page 157 REJ09B0187-0100 of 329 M16C/80 Group 20. UARTi Special Mode Register (i = 2 to 4) The start condition detection interrupt is generated when the fall at the SDA2 pin (P70) is detected while the SCL2 pin (P71) is in the H state. The stop condition detection interrupt is generated when the rise at the SDA2 pin (P70) is detected while the SCL2 pin (P71) is in the H state. The acknowledge non-detection interrupt is generated when the H level at the SDA2 pin is detected at the 9th rise of the transmission clock. The acknowledge detection interrupt is generated when the L level at the SDA2 pin is detected at the 9th rise of the transmission clock. Also, DMA transfer can be started when the acknowledge is detected if UART2 transmission is selected as the DMAi request factor. Bit 2 is the bus busy flag. It is set to "1" when the start condition is detected, and reset to "0" when the stop condition is detected. Bit 1 is the arbitration lost detection flag control bit. Arbitration detects a conflict between data transmitted at SCL2 rise and data at the SDA2 pin. This detection flag is allocated to bit 11 in UART2 transmission buffer register (address 033E16). It is set to "1" when a conflict is detected. With the arbitration lost detection flag control bit, it can be selected to update the flag in units of bits or bytes. When this bit is set to "1", update is set to units of byte. If a conflict is then detected, the arbitration lost detection flag control bit will be set to "1" at the 9th rise of the clock. When updating in units of byte, always clear ("0" interrupt) the arbitration lost detection flag control bit after the 1st byte has been acknowledged but before the next byte starts transmitting. Bit 3 is the SCL2 L synchronization output enable bit. When this bit is set to "1", the P71 data register is set to "0" in sync with the L level at the SCL2 pin. Bit 4 is the bus collision detection sampling clock select bit. The bus collision detection interrupt is generated when RxDi and TxDi level do not conflict with one another. When this bit is "0", a conflict is detected in sync with the rise of the transfer clock. When this bit is "1", detection is made when timer Ai (timer A0 with UART2, timer A3 with UART3 and timer A4 with UART4) underflows. Operation is shown in Figure 20.3. Bit 5 is the transmission enable bit automatic clear select bit. By setting this bit to "1", the transmission bit is automatically reset to "0" when the bus collision detection interrupt factor bit is "1" (when a conflict is detected). Bit 6 is the transmission start condition select bit. By setting this bit to "1", TxDi transmission starts in sync with the falling at the RxDi pin. Rev.1.00 Aug. 02, 2005 Page 158 of 329 REJ09B0187-0100 M16C/80 Group 20. UARTi Special Mode Register (i = 2 to 4) 1. Bus collision detect sampling clock select bit (Bit 4 of the UARTi special mode register) 0: Rising edges of the transfer clock CLKi TxDi/RxDi 1: Timer A0 underflow Timer Ai 2. Auto clear function select bit of transmit enable bit (Bit 5 of the UARTi special mode register) CLKi TxDi/RxDi Bus collision detect interrupt request bit Transmit enable bit 3. Transmit start condition select bit (Bit 6 of the UARTi special mode register) 0: In normal state CLKi TxDi Enabling transmission With "1: falling edge of RxDi" selected CLKi TxDi RxDi Figure 20.3 Some other functions added Rev.1.00 Aug. 02, 2005 Page 159 REJ09B0187-0100 of 329 M16C/80 Group 20. UARTi Special Mode Register (i = 2 to 4) UARTi Special Mode Register 2(i=2 to 4) (Address 033616,032616,02F616) Bit 0 is the IIC mode select bit 2. Table 20.2 gives control changes by bit when the IIC mode select bit is "1". Start and stop condition detection timing characteristics are shown in Figure 20.4. Always set bit 7 (start/stop condition control bit) to "1". Bit 1 is the clock synchronization bit. When this bit is set to "1", if the rise edge is detected at pin SCLi while the internal SCL is H level, the internal SCL is changed to L level, the UARTi bit rate generator value is reloaded and the L sector count starts. Also, while the SCLi pin is L level, if the internal SCL changes from L level to H, the count stops. If the SCLi pin is H level, counting restarts. Because of this function, the UARTi transmission-reception clock takes the AND condition for the internal SCL and SCLi pin signals. This function operates from the clock half period before the 1st rise of the UARTi clock to the 9th rise. To use this function, select the internal clock as the transfer clock. Bit 2 is the SCL wait output bit. When this bit is set to "1", output from the SCLi pin is fixed to L level at the clock's 9th rise. When set to "0", the L output lock is released. Bit 3 is the SDA output stop bit. When this bit is set to "1", an arbitration lost is generated. If the arbitration lost detection flag is "1", the SDAi pin simultaneously becomes high impedance. Bit 4 is the UARTi initialize bit. While this bit is set to "1", the following operations are performed when the start condition is detected. 1. The transmission shift register is initialized and the content of the transmission register is transmitted to the transmission shift register. As such, transmission starts with the 1st bit of the next input clock. However, the UARTi output value remains the same as when the start condition was detected, without changing from when the clock is input to when the 1st bit of data is output. 2. The reception shift register is initialized and reception starts with the 1st bit of the next input clock. 3. The SCL wait output bit is set to "1". As such, the SCLi pin becomes L level at the rise of the 9th bit of the clock. When UART transmission-reception has been started using this function, the content of the transmission buffer available flag does not change. Also, to use this function, select an external clock as the transfer clock. Bit 5 is SCL wait output bit 2. When this bit is set to "1" and serial I/O has been selected, an L level can be forcefully output from the SCLi pin even during UART operation. When this bit is set to "0', the L output from the SCLi pin is canceled and the UARTi clock is input and output. Bit 6 is the SDA output disable bit. When this bit is set to "1", the SDAi pin is forcefully made high impedance. To overwrite this bit, do so at the rise of the UARTi transfer clock. The arbitration lost detection flag may be set. Rev.1.00 Aug. 02, 2005 Page 160 of 329 REJ09B0187-0100 M16C/80 Group 20. UARTi Special Mode Register (i = 2 to 4) Table 20.2 Functions changed by I2C mode select bit 2 IICM2 = 0 Function Acknowrege not detect (NACK) Interrupt no. 33, 35, 37 factor Acknowrege detect (ACK) Interrupt no. 34, 36, 38 factor Acknowrege detect (ACK) DMA factor Data transfer timing from UARTi (i Rising edge of the last bit of re= 2 to 4) receive shift register to re- ceive clock ceive buffer UARTi(i = 2 to 4) receive / ACK interrupt request generation timing Rising edge of the last bit of receive clock IICM2 = 1 UART2 transfer (rising edge of ) Acknowrege detect (ACK) Acknowrege detect (ACK) Rising edge of the last bit of receive clock Rising edge of the last bit of receive clock 3 to 6 cycles < set up time (Note) 3 to 6 cycles < hold time (Note) Note : Cycle number shows main clock input oscillation frequency f(XIN) cycle number. Set up time SCL SDA (Start condition) Hold time SDA (Stop condition) Figure 20.4 Start/stop condition detect timing characteristics UARTi Special Mode Register 3(i=2 to 4 )(Address 033516,032516,02F516) Bits 5 to 7 are the SDAi digital delay setting bits. By setting these bits, it is possible to turn the SDAi delay OFF or set the f(XIN) delay to 2 to 8 cycles. Rev.1.00 Aug. 02, 2005 Page 161 REJ09B0187-0100 of 329 M16C/80 Group 20. UARTi Special Mode Register (i = 2 to 4) (2) Serial Interface Special Function _____ UART 3 and UART4 can control communications on the serial bus using the SSi input pins (Figure 20.5). The master outputting the transfer clock transfers data to the slave inputting the transfer clock. In this case, in order to prevent a data collision on the bus, the master floats the output pin of other slaves/ _____ masters using the SSi input pins. Figure 20.6 shows the structure of UARTi special mode register 3 (addresses 032516 and 02F516 [i = 3 or 4]) which controls this mode. _____ SSi input pins function between the master and slave are as follows. IC1 P13 P12 P93(SS3) P90(CLK3) P91(RxD3) P92(TxD3) M16C/80 (M) IC2 P93(SS3) P90(CLK3) P91(STxD3) P92(SRxD3) M16C/80 (S) IC3 P93(SS3) P90(CLK3) M :Master S :Slave P91(STxD3) P92(SRxD3) M16C/80 (S) Figure 20.5 Serial bus communication control example using the SSi input pins < Slave Mode (STxDi and SRxDi are selected, DINC = 1) > _____ When an H level signal is input to an SSi input pin, the STxDi and SRxDi pins both become high impedance, hence clock input is ignored. When an "L" level signal is input to an SSi input pin, clock input becomes effective and serial communications are enabled. (i = 3 or 4) < Master Mode (TxDi and RxDi are selected, DINC = 0) > _____ _____ The SSi input pins are used with a multiple master system. When an SSi input pin is H level, transmis_____ sion has priority and serial communications are enabled. When an L signal is input to an SSi input pin, another master exists, and the TxDi, RxDi and CLKi pins all become high impedance. Moreover, the trouble error interrupt request bit becomes "1". Communications do not stop even when a trouble error is generated during communications. To stop communications, set bits 0, 1 and 2 of the UARTi transmission-reception mode register (address 032816 and 02F816 [i = 3 or 4]) to "0". The trouble error interrupt is used by both the bus collision interrupt and start/stop condition detection interrupts, but the trouble error interrupt itself can be selected by setting bit 0 of UARTi special mode register 3 (address 032516 and 02F516 [i = 3 or 4]) to "1". When the trouble error flag is set to "0", output is restored to the clock output and data output pins. In _____ _____ the master mode, if an SSi input pin is H level, "0" can be written for the trouble error flag. When an SSi input pin is L level, "0" cannot be written for the trouble error flag. In the slave mode, the "0" can be _____ written for the trouble error flag regardless of the input to the SSi input pins. Rev.1.00 Aug. 02, 2005 Page 162 of 329 REJ09B0187-0100 M16C/80 Group 20. UARTi Special Mode Register (i = 2 to 4) UARTi special mode register 3 (i=3,4) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U3SMR3 U4SMR3 Bit symbol Address 032516 02F516 When reset 000000002 000000002 Bit name Function RW SSE CKPH DINC SS port function enable bit 0: SS function disable (Note 3) 1: SS function enable Clock phase set bit Serial input port set bit 0: Without clock delay 1: With clock delay 0: Select TxDi and RxDi (master mode) (Note 5) 1: Select STxDi and SRxDi (slave mode) (Note 6) 0: CLKi is CMOS output 1: CLKi is N-channel open drain output 0: Without fault error 1: With fault error b7 b6 b5 NODC ERR Clock output select bit Fault error flag SDAi(TxD2) digital delay time set bit (Note 1,2) (Note 4) DL0 DL1 DL2 000 :Without delay 001 :1 to 2 cycles of 1/f(XIN) 010 :2 to 3 cycles of 1/f(XIN) 011 :3 to 4 cycles of 1/f(XIN) 100 :4 to 5 cycles of 1/f(XIN) 101 :5 to 6 cycles of 1/f(XIN) 110 :6 to 7 cycles of 1/f(XIN) 111 :7 to 8 cycles of 1/f(XIN) Note 1: These bits are used for SDAi(TxDi) output digital delay when using UARTi for IIC interface. Otherwise, must set to "000". Note 2: When external clock is selected, delay is increased approx. 100ns. Note 3: Set SS function after setting CTS/RTS disable bit (bit 4 of UARTi transfer/receive control register 0) to "1". Note 4: Nothing but "0" may be written. Note 5: Set CLKi and TxDi both for output using the CLKi and TxDi function select register A. Set the RxDi function select register A for input/output port and the port direction register to "0". Note 6: Set STxDi for output using the STxDi function select registers A and B. Set the CLKi and SRxDi function select register A for input/output port and the port direction register to "0". Figure 20.6 UARTi special mode register 3 (i=3,4) Rev.1.00 Aug. 02, 2005 Page 163 REJ09B0187-0100 of 329 M16C/80 Group 20. UARTi Special Mode Register (i = 2 to 4) Clock Phase Setting With bit 1 of UARTi special mode register 3 (addresses 032516 and 02F516 [i = 3 or 4]) and bit 6 of UARTi transmission-reception control register 0 (addresses 032C16 and 02FC16 [i = 3 or 4]), four combinations of transfer clock phase and polarity can be selected. Bit 6 of UARTi transmission-reception control register 0 (addresses 032C16 and 02FC16 [i = 3 or 4]) sets transfer clock polarity, whereas bit 1 of UARTi special mode register 3 (addresses 032516 and 02F516 [i = 3 or 4]) sets transfer clock phase. Transfer clock phase and polarity must be the same between the master and slave involved in the transfer. < Master (Internal Clock) (DINC = 0) > Figure 20.7 shows the transmission and reception timing. < Slave (External Clock) (DINC = 1) > * With "0" for bit 1 (CKPH) of UARTi special mode register 3 (addresses 032516 and 02F516 [i = 3 or 4]), when an SSi input pin is H level, output data is high impedance. When an SSi input pin is L level, the serial transmission start condition is satisfied, though output is indeterminate. After that, serial transmission is synchronized with the clock. Figure 20.8 shows the timing. * With "1" for bit 1 (CKPH) of UARTi special mode register 3 (addresses 032516 and 02F516 [i = 3 or 4]), when an SSi input pin is H level, output data is high impedance. When an SSi input pin is L level, the first data is output. After that, serial transmission is synchronized with the clock. Figure 20.9 shows the timing. "H" Master SS input "L" "H" Clock output (CKPOL=0, CKPH=0) "L" "H" Clock output (CKPOL=1, CKPH=0) "L" Clock output "H" (CKPOL=0, CKPH=1) "L" "H" Clock output (CKPOL=1, CKPH=1) "L" Data output timing "H" "L" D0 D1 D2 D3 D4 D5 D6 D7 Data input timing Figure 20.7 The transmission and reception timing in master mode (internal clock) Rev.1.00 Aug. 02, 2005 Page 164 of 329 REJ09B0187-0100 M16C/80 Group 20. UARTi Special Mode Register (i = 2 to 4) "H" SS input "L" "H" Clock input (CKPOL=0, CKPH=0) "L" "H" Clock input (CKPOL=1, CKPH=0) "L" Data output timing "H" "L" Highinpedance D0 D1 D2 D3 D4 D5 D6 D7 Highinpedance Data input timing Indeterminate Figure 20.8 The transmission and reception timing (CKPH=0) in slave mode (external clock) "H" SS input "L" "H" Clock input (CKPOL=0, CKPH=0) "L" "H" Clock input (CKPOL=1, CKPH=0) "L" Data output timing "H" "L" Highinpedance D0 D1 D2 D3 D4 D5 D6 D7 Highinpedance Data input timing Figure 20.9 The transmission and reception timing (CKPH=1) in slave mode (external clock) Rev.1.00 Aug. 02, 2005 Page 165 REJ09B0187-0100 of 329 M16C/80 Group 21. A/D Converter 21. A/D Converter The A/D converter consists of one 10-bit successive approximation A/D converter circuit with a capacitive coupling amplifier. Pins P100 to P107, P95, and P96 also function as the analog signal input pins. The direction registers of these pins for A/D conversion must therefore be set to input. The Vref connect bit (bit 5 at address 039716) can be used to isolate the resistance ladder of the A/D converter from the reference voltage input pin (VREF) when the A/D converter is not used. Doing so stops any current flowing into the resistance ladder from VREF, reducing the power dissipation. When using the A/D converter, start A/D conversion only after setting bit 5 of 039716 to connect VREF. The result of A/D conversion is stored in the A/D registers of the selected pins. When set to 10-bit precision, the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit precision, the low 8 bits are stored in the even addresses. Table 21.1 shows the performance of the A/D converter. Figure 21.1 shows the block diagram of the A/D converter, and Figures 21.2 and 21.3 show the A/D converter-related registers. Table 21.1 Performance of A/D converter Item Performance Method of A/D conversion Successive approximation (capacitive coupling amplifier) Analog input voltage (Note 1) 0V to AVCC (VCC) Operating clock fAD (Note 2) VCC = 5V fAD, fAD/2, fAD/4 fAD=f(XIN) VCC = 3V fAD/2, fAD/4 fAD=f(XIN) Resolution 8-bit or 10-bit (selectable) Absolute precision VCC = 5V * 8-bit resolution 2LSB * 10-bit resolution 3LSB However, when using AN0 to AN7 in the mode which external operation amp is connected : 7LSB VCC = 3V * Without sample and hold function (8-bit resolution) 2LSB Operating modes One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, and repeat sweep mode 1 Analog input pins 8 pins (AN0 to AN7) + 2 pins (ANEX0 and ANEX1) A/D conversion start condition * Software trigger A/D conversion starts when the A/D conversion start flag changes to "1" * External trigger (can be retriggered) A/D conversion starts when the A/D conversion start flag is "1" and the ___________ ADTRG/P97 input changes from "H" to "L" Conversion speed per pin * Without sample and hold function 8-bit resolution: 49 fAD cycles, 10-bit resolution: 59 fAD cycles * With sample and hold function 8-bit resolution: 28 fAD cycles, 10-bit resolution: 33 fAD cycles Note 1: Does not depend on use of sample and hold function. Note 2: When f(XIN) is over 10 MHz, the fAD frequency must be under 10 MHz by dividing. Without sample and hold function, set the fAD frequency to 250kHz min. With the sample and hold function, set the fAD frequency to 1MHz min. Rev.1.00 Aug. 02, 2005 Page 166 of 329 REJ09B0187-0100 M16C/80 Group 21. A/D Converter CKS1=1 fAD 1/2 1/2 CKS0=1 CKS1=0 AD A/D conversion rate selection CKS0=0 VREF VCUT=0 Resistance ladder AVSS VCUT=1 Successive conversion register A/D control register 1 (address 039716) A/D control register 0 (address 039616) Addresses (038116, 038016) (038316, 038216) (038516, 038416) (038716, 038616) (038916, 038816) (038B16, 038A16) (038D16, 038C16) (038F16, 038E16) A/D register 0(16) A/D register 1(16) A/D register 2(16) A/D register 3(16) A/D register 4(16) A/D register 5(16) A/D register 6(16) A/D register 7(16) VIN Comparator Vref Decoder Data bus high-order Data bus low-order AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 CH2,CH1,CH0=000 CH2,CH1,CH0=001 CH2,CH1,CH0=010 CH2,CH1,CH0=011 CH2,CH1,CH0=100 CH2,CH1,CH0=101 CH2,CH1,CH0=110 CH2,CH1,CH0=111 OPA1, OPA0 OPA1,OPA0=0,0 OPA1,OPA0=1,1 OPA0=1 0 0 1 1 0 : Normal operation 1 : ANEX0 0 : ANEX1 1 : External op-amp mode ANEX0 OPA1,OPA0=0,1 ANEX1 OPA1=1 Figure 21.1 Block diagram of A/D converter Rev.1.00 Aug. 02, 2005 Page 167 REJ09B0187-0100 of 329 M16C/80 Group 21. A/D Converter A/D control register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol ADCON0 Bit symbol CH0 Address 039616 Bit name When reset 00000XXX2 Function b2 b1 b0 RW Analog input pin select bit CH1 CH2 MD0 MD1 TRG ADST CKS0 0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected b4 b3 (Note 2) A/D operation mode select 0 0 : One-shot mode bit 0 0 1 : Repeat mode 1 0 : Single sweep mode 1 1 : Repeat sweep mode 0 Repeat sweep mode 1 Trigger select bit A/D conversion start flag Frequency select bit 0 0 : Software trigger 1 : ADTRG trigger 0 : A/D conversion disabled 1 : A/D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected (Note 2) Note 1: If the A/D control register is rewritten during A/D conversion, the conversion result is indeterminate. Note 2: When changing A/D operation mode, set analog input pin again. A/D control register 1 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol ADCON1 Bit symbol SCAN0 Address 039716 Bit name When reset 0016 Function When single sweep and repeat sweep mode 0 are selected b1 b0 RW A/D sweep pin select bit SCAN1 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) When repeat sweep mode 1 is selected b1 b0 0 0 : AN0 (1 pin) 0 1 : AN0, AN1 (2 pins) 1 0 : AN0 to AN2 (3 pins) 1 1 : AN0 to AN3 (4 pins) MD2 BITS CKS1 VCUT OPA0 OPA1 A/D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 (Note 2) Vref connect bit External op-amp connection mode bit 0 : Any mode other than repeat sweep mode 1 1 : Repeat sweep mode 1 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 0 : Vref not connected 1 : Vref connected b7 b6 0 0 : ANEX0 and ANEX1 are not used(Note 3) 0 1 : ANEX0 input is A/D converted(Note 4) 1 0 : ANEX1 input is A/D converted(Note 5) 1 1 : External op-amp connection mode(Note 6) Note 1: If the A/D control register is rewritten during A/D conversion, the conversion result is indeterminate. Note 2: When f(XIN) is over 10 MHz, the fAD frequency must be under 10 MHz by dividing. Note 3: Set "0" to PSL3_5 and PSL3_6 of the function select register B3. Note 4: Set "1" to PSL3_5 of the function select register B3. Note 5: Set "1" to PSL3_6 of the function select register B3. Note 6: Set "1" to PSL3_5 and PSL3_6 of the function select register B3. Figure 21.2 A/D converter-related registers (1) Rev.1.00 Aug. 02, 2005 Page 168 of 329 REJ09B0187-0100 M16C/80 Group 21. A/D Converter A/D control register 2 (Note) b7 b6 b5 b4 b3 b2 b1 b0 Symbol ADCON2 Address 039416 When reset XXXXXXX02 000 Bit symbol SMP Reserved bit Bit name A/D conversion method select bit Function 0 : Without sample and hold 1 : With sample and hold Must always set to "0" RW Nothing is assigned. When write, set "0". When read, their content is "0". Note: If the A/D control register is rewritten during A/D conversion, the conversion result is indeterminate. A/D register i (b15) b7 (b8) b0 b7 Symbol ADi(i=0 to 7) Address When reset 038016 to 038F16 Indeterminate b0 Function Eight low-order bits of A/D conversion result * During 10-bit mode Two high-order bits of A/D conversion result * During 8-bit mode When read, the content is indeterminate Nothing is assigned. When write, set "0". When read, their content is "0". RW Figure 21.3 A/D converter-related registers (2) Rev.1.00 Aug. 02, 2005 Page 169 REJ09B0187-0100 of 329 M16C/80 Group 21. A/D Converter (1) One-shot mode In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A/D conversion. Table 21.2 shows the specifications of one-shot mode. Figure 21.4 shows the A/D control register in one-shot mode. Table 21.2 One-shot mode specifications Item Specification Function The pin selected by the analog input pin select bit is used for one A/D conversion Start condition Writing "1" to A/D conversion start flag Stop condition * End of A/D conversion (A/D conversion start flag changes to "0", except when external trigger is selected) * Writing "0" to A/D conversion start flag Interrupt request generation timing End of A/D conversion Input pin One of AN0 to AN7, as selected Reading of result of A/D converter Read A/D register corresponding to selected pin A/D control register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 0 0 Symbol ADCON0 Bit symbol CH0 Address 039616 Bit name When reset 00000XXX2 Function b2 b1 b0 RW Analog input pin select bit CH1 CH2 MD0 MD1 TRG ADST CKS0 A/D operation mode select bit 0 Trigger select bit A/D conversion start flag Frequency select bit 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 : : : : : : : : AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 is is is is is is is is selected selected selected selected selected selected selected selected (Note 2) (Note 2) b4 b3 0 0 : One-shot mode 0 : Software trigger 1 : ADTRG trigger 0 : A/D conversion disabled 1 : A/D conversion started 0: fAD/4 is selected 1: fAD/2 is selected Note 1: If the A/D control register is rewritten during A/D conversion, the conversion result is indeterminate. Note 2: When changing A/D operation mode, set analog input pin again. A/D control register 1 (Note) b7 b6 b5 b4 b3 b2 b1 b0 1 0 Symbol ADCON1 Bit symbol SCAN0 SCAN1 MD2 BITS CKS1 VCUT OPA0 OPA1 Address 039716 Bit name When reset 0016 Function Invalid in one-shot mode RW A/D sweep pin select bit A/D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 (Note 2) Vref connect bit External op-amp connection mode bit 0 : Any mode other than repeat sweep mode 1 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 1 : Vref connected b7 b6 0 0 1 1 0 1 0 1 : : : : ANEX0 and ANEX1 are not used(Note 3) ANEX0 input is A/D converted(Note 4) ANEX1 input is A/D converted(Note 5) External op-amp connection mode(Note 6) Note Note Note Note Note Note 1: 2: 3: 4: 5: 6: If the A/D control register is rewritten during A/D conversion, the conversion result is indeterminate. When f(XIN) is over 10 MHz, the fAD frequency must be under 10 MHz by dividing. Set "0" to PSL3_5 and PSL3_6 of the function select register B3. Set "1" to PSL3_5 of the function select register B3. Set "1" to PSL3_6 of the function select register B3. Set "1" to PSL3_5 and PSL3_6 of the function select register B3. Figure 21.4 A/D conversion register in one-shot mode Rev.1.00 Aug. 02, 2005 Page 170 of 329 REJ09B0187-0100 M16C/80 Group 21. A/D Converter (2) Repeat mode In repeat mode, the pin selected using the analog input pin select bit is used for repeated A/D conversion. Table 21.3 shows the specifications of repeat mode. Figure 21.5 shows the A/D control register in repeat mode. Table 21.3 Repeat mode specifications Specification Function The pin selected by the analog input pin select bit is used for repeated A/D conversion Star condition Writing "1" to A/D conversion start flag Stop condition Writing "0" to A/D conversion start flag Interrupt request generation timing None generated Input pin One of AN0 to AN7, as selected Reading of result of A/D converter Read A/D register corresponding to selected pin (at any time) A/D control register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Item 0 1 Symbol ADCON0 Bit symbol CH0 CH1 Address 039616 Bit name When reset 00000XXX2 Function b2 b1 b0 RW Analog input pin select bit CH2 MD0 MD1 TRG ADST CKS0 A/D operation mode select bit 0 Trigger select bit A/D conversion start flag Frequency select bit 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 : : : : : : : : AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 is is is is is is is is selected selected selected selected selected selected selected selected (Note 2) (Note 2) b4 b3 0 1 : Repeat mode 0 1 0 1 : : : : Software trigger ADTRG trigger A/D conversion disabled A/D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected Note 1: If the A/D control register is rewritten during A/D conversion, the conversion result is indeterminate. Note 2: When changing A/D operation mode, set analog input pin again. A/D control register 1 (Note) b7 b6 b5 b4 b3 b2 b1 b0 1 0 Symbol ADCON1 Bit symbol SCAN0 SCAN1 MD2 BITS CKS1 VCUT OPA0 OPA1 Address 039716 Bit name When reset 0016 Function Invalid in repeat mode RW A/D sweep pin select bit A/D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 (Note 2) Vref connect bit External op-amp connection mode bit 0 : Any mode other than repeat sweep mode 1 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 1 : Vref connected b7 b6 0 0 1 1 0 1 0 1 : : : : ANEX0 and ANEX1 are not used(Note 3) ANEX0 input is A/D converted(Note 4) ANEX1 input is A/D converted(Note 5) External op-amp connection mode(Note 6) Note Note Note Note Note Note 1: 2: 3: 4: 5: 6: If the A/D control register is rewritten during A/D conversion, the conversion result is indeterminate. When f(XIN) is over 10 MHz, the fAD frequency must be under 10 MHz by dividing. Set "0" to PSL3_5 and PSL3_6 of the function select register B3. Set "1" to PSL3_5 of the function select register B3. Set "1" to PSL3_6 of the function select register B3. Set "1" to PSL3_5 and PSL3_6 of the function select register B3. Figure 21.5 A/D conversion register in repeat mode Rev.1.00 Aug. 02, 2005 Page 171 REJ09B0187-0100 of 329 M16C/80 Group 21. A/D Converter (3) Single sweep mode In single sweep mode, the pins selected using the A/D sweep pin select bit are used for one-by-one A/D conversion. Table 21.4 shows the specifications of single sweep mode. Figure 21.6 shows the A/D control register in single sweep mode. Table 21.4 Single sweep mode specifications Item Specification Function The pins selected by the A/D sweep pin select bit are used for one-by-one A/D conversion Start condition Writing "1" to A/D converter start flag Stop condition * End of A/D conversion (A/D conversion start flag changes to "0", except when external trigger is selected) * Writing "0" to A/D conversion start flag Interrupt request generation timing End of A/D conversion Input pin AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins) Reading of result of A/D converter Read A/D register corresponding to selected pin A/D control register 0 (Note) b7 b6 b5 b4 b3 b2 b1 b0 10 Symbol ADCON0 Bit symbol CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0 Address 039616 Bit name When reset 00000XXX2 Function Invalid in single sweep mode RW Analog input pin select bit A/D operation mode select bit 0 Trigger select bit A/D conversion start flag Frequency select bit 0 b4 b3 1 0 : Single sweep mode 0 : Software trigger 1 : ADTRG trigger 0 : A/D conversion disabled 1 : A/D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected Note: If the A/D control register is rewritten during A/D conversion, the conversion result is indeterminate. A/D control register 1 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 1 0 Symbol ADCON1 Bit symbol SCAN0 Address 039716 Bit name When reset 0016 Function When single sweep and repeat sweep mode 0 are selected b1 b0 RW A/D sweep pin select bit SCAN1 A/D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 (Note 3) Vref connect bit External op-amp connection mode bit (Note 2) 0 0 1 1 0 1 0 1 : : : : AN0, AN1 (2 pins) AN0 to AN3 (4 pins) AN0 to AN5 (6 pins) AN0 to AN7 (8 pins) MD2 BITS CKS1 VCUT OPA0 OPA1 Note Note Note Note Note Note Note 1: 2: 3: 4: 5: 6: 7: 0 : Any mode other than repeat sweep mode 1 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 1 : Vref connected b7 b6 0 0 1 1 0 1 0 1 : : : : ANEX0 and ANEX1 are not used(Note 4) ANEX0 input is A/D converted(Note 5) ANEX1 input is A/D converted(Note 6) External op-amp connection mode(Note 7) If the A/D control register is rewritten during A/D conversion, the conversion result is indeterminate. Neither `01' nor `10' can be selected with the external op-amp connection mode bit. When f(XIN) is over 10 MHz, the fAD frequency must be under 10 MHz by dividing. Set "0" to PSL3_5 and PSL3_6 of the function select register B3. Set "1" to PSL3_5 of the function select register B3. Set "1" to PSL3_6 of the function select register B3. Set "1" to PSL3_5 and PSL3_6 of the function select register B3. Figure 21.6 A/D conversion register in single sweep mode Rev.1.00 Aug. 02, 2005 Page 172 of 329 REJ09B0187-0100 M16C/80 Group 21. A/D Converter (4) Repeat sweep mode 0 In repeat sweep mode 0, the pins selected using the A/D sweep pin select bit are used for repeat sweep A/D conversion. Table 21.5 shows the specifications of repeat sweep mode 0. Figure 21.7 shows the A/ D control register in repeat sweep mode 0. Table 21.5 Repeat sweep mode 0 specifications Item Specification Function The pins selected by the A/D sweep pin select bit are used for repeat sweep A/D conversion Start condition Writing "1" to A/D conversion start flag Stop condition Writing "0" to A/D conversion start flag Interrupt request generation timing None generated Input pin AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins) Reading of result of A/D converter Read A/D register corresponding to selected pin (at any time) A/D control register 0 (Note) b7 b6 b5 b4 b3 b2 b1 b0 1 1 Symbol ADCON0 Bit symbol CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0 Address 039616 Bit name When reset 00000XXX2 Function Invalid in repeat sweep mode 0 RW Analog input pin select bit A/D operation mode select bit 0 Trigger select bit A/D conversion start flag Frequency select bit 0 b4 b3 1 1 : Repeat sweep mode 0 0 : Software trigger 1 : ADTRG trigger 0 : A/D conversion disabled 1 : A/D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected Note: If the A/D control register is rewritten during A/D conversion, the conversion result is indeterminate. A/D control register 1 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 1 0 Symbol ADCON1 Bit symbol SCAN0 Address 039716 Bit name When reset 0016 Function When single sweep and repeat sweep mode 0 are selected b1 b0 RW A/D sweep pin select bit SCAN1 A/D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 (Note 3) Vref connect bit External op-amp connection mode bit (Note 2) 0 0 1 1 0 1 0 1 : : : : AN0, AN1 (2 pins) AN0 to AN3 (4 pins) AN0 to AN5 (6 pins) AN0 to AN7 (8 pins) MD2 BITS CKS1 VCUT OPA0 OPA1 Note Note Note Note Note Note Note 1: 2: 3: 4: 5: 6: 7: 0 : Any mode other than repeat sweep mode 1 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 1 : Vref connected b7 b6 0 0 1 1 0 1 0 1 : : : : ANEX0 and ANEX1 are not used(Note 4) ANEX0 input is A/D converted(Note 5) ANEX1 input is A/D converted(Note 6) External op-amp connection mode(Note 7) If the A/D control register is rewritten during A/D conversion, the conversion result is indeterminate. Neither `01' nor `10' can be selected with the external op-amp connection mode bit. When f(XIN) is over 10 MHz, the fAD frequency must be under 10 MHz by dividing. Set "0" to PSL3_5 and PSL3_6 of the function select register B3. Set "1" to PSL3_5 of the function select register B3. Set "1" to PSL3_6 of the function select register B3. Set "1" to PSL3_5 and PSL3_6 of the function select register B3. Figure 21.7 A/D conversion register in repeat sweep mode 0 Rev.1.00 Aug. 02, 2005 Page 173 REJ09B0187-0100 of 329 M16C/80 Group 21. A/D Converter (5) Repeat sweep mode 1 In repeat sweep mode 1, all pins are used for A/D conversion with emphasis on the pin or pins selected using the A/D sweep pin select bit. Table 21.6 shows the specifications of repeat sweep mode 1. Figure 21.8 shows the A/D control register in repeat sweep mode 1. Table 21.6 Repeat sweep mode 1 specifications Item Specification Function All pins perform repeat sweep A/D conversion, with emphasis on the pin or pins selected by the A/D sweep pin select bit Example : AN0 selected AN0 AN1 AN0 AN2 AN0 AN3, etc Start condition Writing "1" to A/D conversion start flag Stop condition Writing "0" to A/D conversion start flag Interrupt request generation timing None generated Input pin AN0 to AN7 With emphasis on the pin AN0 (1 pin), AN0 and AN1 (2 pins), AN0 to AN2 (3 pins), AN0 to AN3 (4 pins) Reading of result of A/D converter Read A/D register corresponding to selected pin (at any time) A/D control register 0 (Note) b7 b6 b5 b4 b3 b2 b1 b0 1 1 Symbol ADCON0 Bit symbol CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0 Address 039616 Bit name When reset 00000XXX2 Function Invalid in repeat sweep mode 1 RW Analog input pin select bit A/D operation mode select bit 0 Trigger select bit A/D conversion start flag Frequency select bit 0 b4 b3 1 1 : Repeat sweep mode 1 0 : Software trigger 1 : ADTRG trigger 0 : A/D conversion disabled 1 : A/D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected Note: If the A/D control register is rewritten during A/D conversion, the conversion result is indeterminate. A/D control register 1 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 1 1 Symbol ADCON1 Bit symbol SCAN0 Address 039716 Bit name When reset 0016 Function When repeat sweep mode 1 is selected b1 b0 RW A/D sweep pin select bit SCAN1 A/D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 (Note 3) Vref connect bit External op-amp connection mode bit (Note 2) 0 0 1 1 0 1 0 1 : : : : AN0 (1 pin) AN0, AN1 (2 pins) AN0 to AN2 (3 pins) AN0 to AN3 (4 pins) MD2 BITS CKS1 VCUT OPA0 OPA1 Note Note Note Note Note Note Note 1: 2: 3: 4: 5: 6: 7: 1 : Repeat sweep mode 1 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 1 : Vref connected b7 b6 0 0 1 1 0 1 0 1 : : : : ANEX0 and ANEX1 are not used(Note 4) ANEX0 input is A/D converted(Note 5) ANEX1 input is A/D converted(Note 6) External op-amp connection mode(Note 7) If the A/D control register is rewritten during A/D conversion, the conversion result is indeterminate. Neither `01' nor `10' can be selected with the external op-amp connection mode bit. When f(XIN) is over 10 MHz, the fAD frequency must be under 10 MHz by dividing. Set "0" to PSL3_5 and PSL3_6 of the function select register B3. Set "1" to PSL3_5 of the function select register B3. Set "1" to PSL3_6 of the function select register B3. Set "1" to PSL3_5 and PSL3_6 of the function select register B3. Figure 21.8 A/D conversion register in repeat sweep mode 1 Rev.1.00 Aug. 02, 2005 Page 174 of 329 REJ09B0187-0100 M16C/80 Group 21. A/D Converter (a) Sample and hold Sample and hold is selected by setting bit 0 of the A/D control register 2 (address 039416) to "1". When sample and hold is selected, the rate of conversion of each pin increases. As a result, a 28 fAD cycle is achieved with 8-bit resolution and 33 fAD with 10-bit resolution. Sample and hold can be selected in all modes. However, in all modes, be sure to specify before starting A/D conversion whether sample and hold is to be used. (b) Extended analog input pins In one-shot mode and repeat mode, the input via the extended analog input pins ANEX0 and ANEX1 can also be converted from analog to digital. When bit 6 of the A/D control register 1 (address 039716) is "1" and bit 7 is "0", input via ANEX0 is converted from analog to digital. The result of conversion is stored in A/D register 0. When bit 6 of the A/D control register 1 (address 039716) is "0" and bit 7 is "1", input via ANEX1 is converted from analog to digital. The result of conversion is stored in A/D register 1. Set the related input peripheral function of the function select register B3 to disabled. (c) External operation amp connection mode In this mode, multiple external analog inputs via the extended analog input pins, ANEX0 and ANEX1, can be amplified together by just one operation amp and used as the input for A/D conversion. When bit 6 of the A/D control register 1 (address 039716) is "1" and bit 7 is "1", input via AN0 to AN7 is output from ANEX0. The input from ANEX1 is converted from analog to digital and the result stored in the corresponding A/D register. The speed of A/D conversion depends on the response of the external operation amp. Do not connect the ANEX0 and ANEX1 pins directly. Figure 21.9 is an example of how to connect the pins in external operation amp mode. Set the related input peripheral function of the function select register B3 to disabled. Resistance ladder Successive conversion register Analog input AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ANEX0 ANEX1 Comparator External op-amp Figure 21.9 Example of external op-amp connection mode Rev.1.00 Aug. 02, 2005 Page 175 REJ09B0187-0100 of 329 M16C/80 Group 22. D/A Converter 22. D/A Converter This is an 8-bit, R-2R type D/A converter. The microcomputer contains two independent D/A converters of this type. D/A conversion is performed when a value is written to the corresponding D/A register. Bits 0 and 1 (D/A output enable bits) of the D/A control register decide if the result of conversion is to be output. Set the function select register A3 to I/O port, the related input peripheral function of the function select register B3 to disabled and the direction register to input mode. When the D/A output is enabled, the pull-up function of the corresponding port is automatically disabled. Output analog voltage (V) is determined by a set value (n : decimal) in the D/A register. V = VREF X n/ 256 (n = 0 to 255) VREF : reference voltage Table 22.1 lists the performance of the D/A converter. Figure 22.1 shows the block diagram of the D/A converter. Figure 22.2 shows the D/A control register. Table 22.1 Performance of D/A converter Item Conversion method Resolution Analog output pin R-2R method 8 bits 2 channels Performance Data bus low-order bits D/A register i (8) (i = 0, 1) (Address 039816, 039A16) D/Ai output enable bit (i = 0, 1) R-2R resistance ladder P93 / DA0 P94 / DA1 Figure 22.1 Block diagram of D/A converter Rev.1.00 Aug. 02, 2005 Page 176 of 329 REJ09B0187-0100 M16C/80 Group 22. D/A Converter D/A control register b7 b6 b5 b4 b3 b2 b1 b0 Symbol DACON Bit symbol DA0E DA1E Address 039C16 Bit name D/A0 output enable bit D/A1 output enable bit When reset 0016 Function 0 : Output disabled 1 : Output enabled 0 : Output disabled 1 : Output enabled RW Nothing is assigned. When write, set "0". When read, the value of these bits is "0". D/A register i b7 b0 Symbol DAi (i = 0,1) Address 039816, 039A16 When reset Indeterminate Function Output value of D/A conversion RW RW Figure 22.2 D/A control register D/A0 output enable bit "0" R DA0 "1" 2R MSB D/A register 0 AVSS VREF "0" "1" 2R R R R R R R 2R 2R 2R 2R 2R 2R 2R LSB Note 1: In the above figure, the D/A register value is "2A16". Note 2: This circuit is the same in D/A1. Note 3: To save power when not using the D/A converter, set the D/A output enable bit to "0" and the D/A register to "0016", and prevent current flowing to the R-2R resistance. Figure 22.3 D/A converter equivalent circuit Rev.1.00 Aug. 02, 2005 Page 177 REJ09B0187-0100 of 329 M16C/80 Group 23. CRC Calculation Circuit 23. CRC Calculation Circuit The Cyclic Redundancy Check (CRC) calculation circuit detects an error in data blocks. The microcomputer uses a generator polynomial of CRC_CCITT (X16 + X12 + X5 + 1) to generate CRC code. The CRC code is a 16-bit code generated for a block of a given data length in multiples of 8 bits. The CRC code is set in a CRC data register each time one byte of data is transferred to a CRC input register after writing an initial value into the CRC data register. Generation of CRC code for one byte of data is completed in two machine cycles. Figure 23.1 shows the block diagram of the CRC circuit. Figure 23.2 shows the CRC-related registers. Data bus high-order bits Data bus low-order bits Eight low-order bits CRC data register (16) Eight high-order bits (Addresses 037D16, 037C16) CRC code generating circuit x16 + x12 + x5 + 1 CRC input register (8) (Address 037E16) Figure 23.1 Block diagram of CRC circuit CRC data register (b15) b7 (b8) b0 b7 b0 Symbol CRCD Address 037D16, 037C16 When reset Indeterminate Values that can be set 000016 to FFFF16 Function CRC calculation result output register RW CRC input register b7 b0 Symbo CRCIN Function Data input register Address 037E16 When reset Indeterminate Values that can be set 0016 to FF16 RW Figure 23.2 CRC-related registers Rev.1.00 Aug. 02, 2005 Page 178 of 329 REJ09B0187-0100 M16C/80 Group 23. CRC Calculation Circuit b15 b0 (1) Setting 000016 CRC data register CRCD [037D16, 037C16] b7 b0 (2) Setting 0116 CRC input register CRCIN [037E16] 2 cycles After CRC calculation is complete b15 b0 118916 CRC data register CRCD [037D16, 037C16] Stores CRC code The code resulting from sending 0116 in LSB first mode is (1000 0000). Thus the CRC code in the generating polynomial, (X16 + X12 + X5 + 1), becomes the remainder resulting from dividing (1000 0000) X16 by (1 0001 0000 0010 0001) in conformity with the modulo-2 operation. LSB 1000 1000 1 0001 0000 0010 0001 1000 0000 0000 1000 1000 0001 1000 0001 1000 1000 1001 LSB 9 8 1 0000 0000 0000 0001 0001 1 0000 1 1000 0000 1000 0000 0 1 1000 MSB MSB Modulo-2 operation is operation that complies with the law given below. 0+0=0 0+1=1 1+0=1 1+1=0 -1 = 1 Thus the CRC code becomes (1001 0001 1000 1000). Since the operation is in LSB first mode, the (1001 0001 1000 1000) corresponds to 118916 in hexadecimal notation. If the CRC operation in MSB first mode is necessary in the CRC operation circuit built in the M16C, switch between the LSB side and the MSB side of the input-holding bits, and carry out the CRC operation. Also switch between the MSB and LSB of the result as stored in CRC data. b7 b0 (3) Setting 2316 CRC input register CRCIN [037E16] After CRC calculation is complete b15 b0 0A4116 CRC data register CRCD [037D16, 037C16] Stores CRC code Figure 23.3 CRC example Rev.1.00 Aug. 02, 2005 Page 179 REJ09B0187-0100 of 329 M16C/80 Group 24. XY Converter 24. XY Converter XY conversion rotates the 16 x 16 matrix data by 90 degrees. It can also be used to invert the top and bottom of the 16-bit data. Figure 24.1 shows the XY control register. The Xi and the Yi registers are 16-bit registers. There are 16 of each (where i= 0 to 15). The Xi and Yi registers are mapped to the same address. The Xi register is a write-only register, while the Yi register is a read-only register. Be sure to access the Xi and Yi registers in 16-bit units from an even address. Operation cannot be guaranteed if you attempt to access these registers in 8-bit units. XY control register b7 b6 b5 b4 b3 b2 b1 b0 Symbol XYC Bit symbol XYC0 XYC1 Address 02E016 Bit name Read-mode set bit Write-mode set bit When reset XXXXXX002 Function 0 : Data conversion 1 : No data conversion 0 : No bit mapping conversion 1 : Bit mapping conversion RW Nothing is assigned. When write, set "0". When read, the value of these bits is indeterminate. Figure 24.1 XY control register Rev.1.00 Aug. 02, 2005 Page 180 of 329 REJ09B0187-0100 M16C/80 Group 24. XY Converter The reading of the Yi register is controlled by the read-mode set bit (bit 0 at address 02E016). When the read-mode set bit (bit 0 at address 02E016) is "0", specific bits in the Xi register can be read at the same time as the Yi register is read. For example, when you read the Y0 register, bit 0 is read as bit 0 of the X0 register, bit 1 is read as bit 0 of the X1 register, ..., bit 14 is read as bit 0 of the X14 register, bit 15 as bit 0 of the X15 register. Similarly, when you read the Y15 register, bit 0 is bit 15 of the X0 register, bit 1 is bit 15 of the X1 register, ..., bit 14 is bit 15 of the X14 register, bit 15 is bit 15 of the X15 register. Figure 24.2 shows the conversion table when the read mode set bit = "0". Figure 24.3 shows the XY conversion example. Read address Y15 register (0002DE16) Y14 register (0002DC16) Y13 register (0002DA16) Y12 register (0002D816) Y11 register (0002D616) Y10 register (0002D416) Y9 register (0002D216) Y8 register (0002D016) Y7 register (0002CE16) Y6 register (0002CC16) Y5 register (0002CA16) Y4 register (0002C816) Y3 register (0002C616) Y2 register (0002C416) Y1 register (0002C216) Y0 register (0002C016) Write address b15 Bit of Xi register b0 Figure 24.2 Conversion table when the read mode set bit = "0" b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 X0-Reg X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 Y0-Reg Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Figure 24.3 XY conversion example Rev.1.00 Aug. 02, 2005 Page 181 REJ09B0187-0100 of 329 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 (X register) (Y register) b0 X15 register (0002DE16) X14 register (0002DC16) X13 register (0002DA16) X12 register (0002D816) X11 register (0002D616) X10 register (0002D416) X9 register (0002D216) X8 register (0002D016) X7 register (0002CE16) X6 register (0002CC16) X5 register (0002CA16) X4 register (0002C816) X3 register (0002C616) X2 register (0002C416) X1 register (0002C216) X0 register (0002C016) b15 Bit of Yi register M16C/80 Group 24. XY Converter When the read-mode set bit (bit 0 at address 02E016) is "1", you can read the value written to the Xi register by reading the Yi register. Figure 24.4 shows the conversion table when the read mode set bit = "1". Write address Read address X15,Y15 register (0002DE16) X14,Y14 register (0002DC16) X13,Y13 register (0002DA16) X12,Y12 register (0002D816) X11,Y11 register (0002D616) X10,Y10 register (0002D416) X9,Y9 register (0002D216) X8,Y8 register (0002D016) X7,Y7 register (0002CE16) X6,Y6 register (0002CC16) X5,Y5 register (0002CA16) X4,Y4 register (0002C816) X3,Y3 register (0002C616) X2,Y2 register (0002C416) X1,Y1 register (0002C216) X0,Y0 register (0002C016) b15 Bit of Xi register Bit of Yi register b0 Figure 24.4 Conversion table when the read mode set bit = "1" The value written to the Xi register is controlled by the write mode set bit (bit 1 at address 02E016). When the write mode set bit (bit 1 at address 02E016) is "0" and data is written to the Xi register, the bit stream is written directly. When the write mode set bit (bit 1 at address 02E016) is "1" and data is written to the Xi register, the bit sequence is reversed so that the high becomes low and vice versa. Figure 24.5 shows the conversion table when the write mode set bit = "1". b15 b0 Write address b15 b0 Bit of Xi register Figure 24.5 Conversion table when the write mode set bit = "1" Rev.1.00 Aug. 02, 2005 Page 182 of 329 REJ09B0187-0100 M16C/80 Group 25. DRAM Controller 25. DRAM Controller There is a built in DRAM controller to which it is possible to connect between 512 Kbytes and 8 Mbytes of DRAM. Table 25.1 shows the functions of the DRAM controller. Table 25.1 DRAM Controller Functions DRAM space 512KB, 1MB, 2MB, 4MB, 8MB Bus control Refresh Function modes Waits 2CAS/1W ________ ________ CAS before RAS refresh Self refresh-compatible EDO-compatible, fast page mode-compatible 1 wait or 2 waits, programmable To use the DRAM controller, use the DRAM space select bit of the DRAM control register (address 004016) to specify the DRAM size. Figure 25.1 shows the DRAM control register. The DRAM controller cannot be used in external memory mode 3 (bits 1 and 2 at address 000516 are "112"). Always use the DRAM controller in external memory modes 0, 1, or 2. When the data bus width is 16-bit in DRAM area, set "1" to R/W mode select bit (bit 2 at address 000416). Set wait time between after DRAM power ON and before memory processing, and processing necessary for dummy cycle to refresh DRAM by software. DRAM control register b7 b6 b5 b4 b3 b2 b1 b0 Symbol DRAMCONT Bit symbol WT AR0 Address 0004016 Bit name When reset Indeterminate (Note 4) Function 0 : Two wait 1 : One wait b3 b2 b1 RW Wait select bit (Note 1) AR1 DRAM space select bit AR2 0 0 0 : DRAM ignored 0 0 1 : Inhibit 0 1 0 : 0.5MB 0 1 1 : 1MB 1 0 0 : 2MB 1 0 1 : 4MB 1 1 0 : 8MB 1 1 1 : Inhibit Nothing is assigned. When write, set "0". When read, the value of these bits is indeterminate. SREF Self-refresh mode bit (Note 2) 0: Self-refresh OFF 1: Self-refresh ON Note 1: The number of cycles with 2 waits is 3-2-2. With 1 wait, it is 2-1-1. Note 2: When you set "1", both RAS and CAS change to "L". When you set "0", RAS and CAS change to "H" and then normal operation (read/write, refresh) is resumed. In Stop mode, there is no control. Note 3: Set the bus width using the external data bus width control register (address 000B16). When selecting 8-bit bus width, CASH is indeterminate. Note 4: After reset, the content of this register is indeterminate. DRAM controller starts the operation after writing to this register. Figure 25.1 DRAM control register Rev.1.00 Aug. 02, 2005 Page 183 REJ09B0187-0100 of 329 M16C/80 Group 25. DRAM Controller * DRAM Controller Multiplex Address Output The DRAM controller outputs the row addresses and column addresses as a multiplexed signal to the address bus A8 to A20. Figure 25.2 shows the output format for multiplexed addresses. 8-bit bus mode Pin function Row address Column address MA12 MA11 (A20) (A19) MA10 MA9 (A18) (A17) MA8 (A16) MA7 (A15) MA6 (A14) MA5 (A13) MA4 (A12) MA3 (A11) MA2 (A10) MA1 (A9) MA0 (A8) (A20) (A19) A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 - (A22) (A22) A19 A8 A7 A6 A5 A4 A3 A2 A1 A0 - 512KB, 1MB Row address Column address (A20) A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 - (A22) A21 A20 A8 A7 A6 A5 A4 A3 A2 A1 A0 - 2MB, 4MB Row address Column address A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 - (A22) A22 A21 A8 A7 A6 A5 A4 A3 A2 A1 A0 - 8MB 16-bit bus mode Pin function Row address Column address MA12 MA11 MA10 (A20) (A19) (A18) (A20) (A19) A18 MA9 (A17) A17 MA8 (A16) A16 MA7 (A15) MA6 (A14) A14 MA5 (A13) A13 MA4 (A12) A12 MA3 (A11) A11 MA2 (A10) A10 MA1 (A9) (A9) MA0 (A8) - A15 (A22) (A20) A9 A8 A7 A6 A5 A4 A3 A2 A1 (A0) - 512KB Row address Column address (A20) A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 (A9) - (A22) A20 A9 A8 A7 A6 A5 A4 A3 A2 A1 (A0) - 1MB, 2MB Row address Column address A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 (A9) - A22 A21 A9 A8 A7 A6 A5 A4 A3 A2 A1 (A0) - 4MB, 8MB (Note 2) Note 1: ( ) invalid bit: bits that change according to selected mode (8-bit/16-bit bus mode, DRAM space). Note 2: The figure is for 4Mx1 or 4Mx4 memory configuration. If you are using a 4Mx16 configuration, use combinations of the following: For row addresses, MA0 to MA12; for column addresses MA2 to MA8, MA11, and MA12. Or for row addresses MA1 to MA12; for column addresses MA2 to MA9, MA11, MA12. Note 3: "-" is indeterminate. Figure 25.2 Output format for multiplexed addresses Rev.1.00 Aug. 02, 2005 Page 184 of 329 REJ09B0187-0100 M16C/80 Group 25. DRAM Controller * Refresh _______ _______ The refresh method is CAS before RAS. The refresh interval is set by the DRAM refresh interval set register (address 004116). The refresh signal is not output in HOLD state. Figure 25.3 shows the DRAM refresh interval set register. Use the following formula to determine the value to set in the refresh interval set register. Refresh interval set register value (0 to 255) = refresh interval time / (BCLK frequency X 32) - 1 DRAM refresh interval set register b7 b6 b5 b4 b3 b2 b1 b0 Symbol REFCNT Bit symbol REFCNT0 REFCNT1 REFCNT2 REFCNT3 REFCNT4 REFCNT5 REFCNT6 REFCNT7 Address 0004116 Bit name When reset Indeterminate Function b7 b6 b5 b4 b3 b2 b1 b0 RW Refresh interval set bit 0 0 0 0 0 0 0 0 : 1.6 s 0 0 0 0 0 0 0 1 : 3.2 s 0 0 0 0 0 0 1 0 : 4.8 s * * * 1 1 1 1 1 1 1 1 : 409.6 s (Note) Note: Refresh interval at 20 MHz operating (no division) Refresh interval = BCLK frequency X (refresh interval set bit + 1) X 32 Figure 25.3 DRAM refresh interval set register Rev.1.00 Aug. 02, 2005 Page 185 REJ09B0187-0100 of 329 M16C/80 Group 25. DRAM Controller The DRAM self-refresh operates in STOP mode, etc. When shifting to self-refresh, select DRAM ignored by the DRAM space select bit. In the next instruction, simultaneously set the DRAM space select bit and self-refresh ON by self-refresh mode bit. Also, insert two NOPs after the instruction that sets the self-refresh mode bit to "1". Do not access external memory while operating in self-refresh. (All external memory space access is inhibited. ) When disabling self-refresh, simultaneously select DRAM ignored by the DRAM space select bit and selfrefresh OFF by self-refresh mode bit. In the next instruction, set the DRAM space select bit. Do not access the DRAM space immediately after setting the DRAM space select bit. Example) One wait is selected by the wait select bit and 4MB is selected by the DRAM space select bit Shifting to self-refresh *** mov.b #00000001b,DRAMCONT ;DRAM ignored, one wait is selected mov.b #10001011b,DRAMCONT ;Set self-refresh, select 4MB and one wait nop ;Two nops are needed nop ; *** Disable self-refresh *** mov.b #00000001b,DRAMCONT mov.b nop nop *** #00001011b,DRAMCONT ;Disable self-refresh, DRAM ignored, one wait is ;selected ;Select 4MB and one wait ;Inhibit instruction to access DRAM area Figures 25.4 to 25.6 show the bus timing during DRAM access. Rev.1.00 Aug. 02, 2005 Page 186 of 329 REJ09B0187-0100 M16C/80 Group 25. DRAM Controller < Read cycle (wait control bit = 0) > BCLK MA0 to MA12 Row address Column address 1 Column address 2 Column address 3 RAS CASH CASL 'H' DW D0 to D15 (EDO mode) Note : Only CASL is operating in 8-bit data bus width. < Write cycle (wait control bit = 0) > BCLK MA0 to MA12 Row address Column address 1 Column address 2 Column address 3 RAS CASH CASL DW D0 to D15 Note : Only CASL is operating in 8-bit data bus width. Figure 25.4 The bus timing during DRAM access (1) Rev.1.00 Aug. 02, 2005 Page 187 REJ09B0187-0100 of 329 M16C/80 Group 25. DRAM Controller < Read cycle (wait control bit = 1) > BCLK MA0 to MA12 Row address Column address 1 Column address 2 Column address 3 Column address 4 RAS CASH CASL 'H' DW D0 to D15 (EDO mode) Note : Only CASL is operating in 8-bit data bus width. < Write cycle (wait control bit = 1) > BCLK MA0 to MA12 Row address Column address 1 Column address 2 Column address 3 Column address 4 RAS CASH CASL DW D0 to D15 Note : Only CASL is operating in 8-bit data bus width. Figure 25.5 The bus timing during DRAM access (2) Rev.1.00 Aug. 02, 2005 Page 188 of 329 REJ09B0187-0100 M16C/80 Group 25. DRAM Controller BCLK RAS CASH CASL "H" DW < CAS before RAS refresh cycle > Note : Only CASL is operating in 8-bit data bus width. BCLK RAS CASH CASL "H" DW < Self refresh cycle > Note : Only CASL is operating in 8-bit data bus width. Figure 25.6 The bus timing during DRAM access (3) Rev.1.00 Aug. 02, 2005 Page 189 REJ09B0187-0100 of 329 M16C/80 Group 26. Programmable I/O Ports 26. Programmable I/O Ports There are 87 programmable I/O ports for 100-pin version: P0 to P10 (excluding P85). There are 123 programmable I/O ports for 144-pin version: P0 to P15 (excluding P85). Each port can be set independently for input or output using the direction register. A pull-up resistance for each block of 4 ports can be set. P85 is an input-only port and has no built-in pull-up resistance. Figures 26.1 to 26.3 show the programmable I/O ports. Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices. To use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input mode. When the pins are used as the outputs for the built-in peripheral devices (other than the D/A converter), set the corresponding function select registers A, B and C. When pins are to be used as the outputs for the D/A converter, set the function select register of each pin to I/O port, and set the direction registers to input mode. Table 26.1 lists each port and peripheral function. See the descriptions of the respective functions for how to set up the built-in peripheral devices. (1) Direction registers Figures 26.4 and 26.5 show the direction registers. These registers are used to choose the direction of the programmable I/O ports. Each bit in these registers corresponds one for one to each I/O pin. In memory expansion and microprocessor mode, the contents of corresponding direction register of _____ _______ _______ _______ _____ _________ _______ _______ _______ _____ _____ pins A0 to A22, A23, D0 to D15, MA0 to MA12, CS0 to CS 3, WRL/WR/CASL, WRH/BHE/CASH, RD/DW, _________ _________ _______ _______ BCLK/ALE/CLKOUT, HLDA/ALE, HOLD, ALE/RAS, and RDY are not changed. Note: There is no direction register bit for P85. (2) Port registers Figures 26.6 and 26.7 show the port registers. These registers are used to write and read data for input and output to and from an external device. A port register consists of a port latch to hold output data and a circuit to read the status of a pin. Each bit in port registers corresponds one for one to each I/O pin. In memory expansion and microprocessor mode, the contents of corresponding port register of pins A0 to ______ _______ _______ _______ _____ _________ _______ _______ _______ _____ _____ A22, A23, D0 to D15, MA0 to MA12, CS0 to CS 3, WRL/WR/CASL, WRH/BHE/CASH, RD/DW, BCLK/ALE/ _________ _________ _______ _______ CLKOUT, HLDA/ALE, HOLD, ALE/RAS, and RDY are not changed. (3) Function select register A Figures 26.8 and 26.9 show the function select registers A. The register is used to select port output and peripheral function output when the port functions for both port output and peripheral function output. Each bit of this register corresponds to each pin that functions for both port output and peripheral function output. Rev.1.00 Aug. 02, 2005 Page 190 of 329 REJ09B0187-0100 M16C/80 Group 26. Programmable I/O Ports (4) Function select register B Figures 26.10 and 26.11 show the function select registers B. This register selects the 1st peripheral function output and second peripheral function output when multiple peripheral function outputs are assigned to a pin. For pins with a third peripheral function, this register selects whether to enable the function select register C, or output the second peripheral function. Each bit of this register corresponds to each pin that has multiple peripheral function outputs assigned to it. This register is enabled when the bits of the corresponding function select register A are set for peripheral functions. The bit 3 to bit 6 of function select register B3 is ignored bit for input peripheral function. When using DA0/ DA1 and ANEX0/ANEX1, set related bit to "1". When not using DA0/DA1 or ANEX0/ANEX1, set related bit to "0". (5) Function select register C Figure 26.12 shows the function select register C. This register is used to select the first peripheral function output and the third peripheral function output when three peripheral function outputs are assigned to a pin. This register is effective when the bits of the function select register A of the counterpart pin have selected a peripheral function and when the function select register B has made effective the function select register C. The bit 7 (PSC_7) is assigned the key-in interrupt inhibit bit. Setting 1 in the key-in interrupt inhibit bit causes no key-in interrupts regardless of the settings in the interrupt control register even if L is entered in pins KI0 to KI3. With 1 set in the key-in interrupt inhibit bit, input from a port pin cannot be effected even if the port direction register is set to input mode. (6) Pull-up control registers Figures 26.13 and 26.14 show the pull-up control registers. The pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. When ports are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is set for input. Since P0 to P5 operate as the bus in memory expansion mode and microprocessor mode, do not set the pull-up control register. However, it is possible to select pull-up resistance presence to the usable port as I/O port by setting. (7) Port control register Figure 26.15 shows the port control register. This register is used to choose whether to make port P1 a CMOS port or an Nch open drain. In the Nch open drain, the port P1 has no function that a complete open drain but keeps the CMOS port's Pch always turned off. Thus the absolute maximum rating of the input voltage falls within the range from - 0.3 V to Vcc + 0.3 V. The port control register functions similarly to the above also in the case in which port P1 can be used as a port when the bus width in the full external areas comprises 8 bits in either microprocessor mode or in memory expansion mode. Rev.1.00 Aug. 02, 2005 Page 191 REJ09B0187-0100 of 329 M16C/80 Group 26. Programmable I/O Ports Pull-up selection Direction register P00 to P07, P20 to P27, P30 to P37, P40 to P47, P50 to P52, P54 to P57, P110 to P114, P120 to P127, P130 to P137, P140 to P146, P150 to P157 Note: Port P11 to P15 exist in 144-pin version. (Note) Data bus Port latch Pull-up selection P10 to P14 Direction register Port P1 control register bit 0 Data bus Port latch Pull-up selection P15 to P17 Direction register Port P1 control register bit 0 Data bus Port latch Input to respective peripheral functions Pull-up selection Direction register P62, P66, P77, P87 Data bus Port latch Input to respective peripheral functions Figure 26.1 Programmable I/O ports (1) Rev.1.00 Aug. 02, 2005 Page 192 of 329 REJ09B0187-0100 M16C/80 Group 26. Programmable I/O Ports Pull-up selection P82 to P84 Direction register Data bus Port latch Input to respective peripheral functions Note P60, P61, P64, P65, P72, P73 P74, P75, P76, P80, P81, P90, P91 P92, P97 (inside dotted-line included) P53, P63, P67, P86 (inside dotted-line not included) Output from respective peripheral functions Function select register A Pull-up selection Direction register Data bus Port latch Input to respective peripheral functions Note : P53 is connected to clock output function select bit. P85 Data bus NMI interrupt input P70, P71 Function select register A Direction register Output from respective peripheral functions Data bus Port latch Input to respective peripheral functions Figure 26.2 Programmable I/O ports (2) Rev.1.00 Aug. 02, 2005 Page 193 REJ09B0187-0100 of 329 M16C/80 Group 26. Programmable I/O Ports P100 to P103 Pull-up selection Direction register Data bus Port latch Analog input P104 to P107 Pull-up selection Direction register Data bus Port latch Input to respective peripheral functions Analog input P93, P94 Function select register A Pull-up selection Direction register Output from respective peripheral functions Data bus Port latch Input to respective peripheral functions Analog input D/A output enabled P95 (inside dotted-line included) P96 (inside dotted-line not included) Function select register A Pull-up selection Direction register Output from respective peripheral functions Data bus Port latch Analog input Input to respective peripheral functions Figure 26.3 Programmable I/O ports (3) Rev.1.00 Aug. 02, 2005 Page 194 of 329 REJ09B0187-0100 M16C/80 Group 26. Programmable I/O Ports Port Pi direction register (Note 1,2, 3) Symbol PDi (i = 0 to 15, except 8, 11 and 14) Address When reset 03E216, 03E316, 03E616, 03E716, 0016 03EA16, 03EB16, 03C216, 03C316, 03C716, 03CA16, 03CE16, 03CF16, 03D316 Function 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) (i = 0 to 15 except 8, 11 and 14) RW b7 b6 b5 b4 b3 b2 b1 b0 Bit symbol PDi_0 PDi_1 PDi_2 PDi_3 PDi_4 PDi_5 PDi_6 PDi_7 Bit name Port Pi0 direction register Port Pi1 direction register Port Pi2 direction register Port Pi3 direction register Port Pi4 direction register Port Pi5 direction register Port Pi6 direction register Port Pi7 direction register Note 1: Set bit 2 of protect register (address 000A16) to "1" before rewriting to the port P9 direction register. Note 2: In memory expansion and microprocessor mode, the contents of corresponding port direction register of pins A0 to A22, A23, D0 to D15, MA0 to MA12, CS0 to CS 3, WRL/WR/CASL, WRH/BHE/CASH, RD/DW, BCLK/ALE/ CLKOUT, HLDA/ALE, HOLD, ALE/RAS, and RDY are not changed. Note 3: Port P12, P13 and P15 direction registers exist in 144-pin version. Port P8 direction register b7 b6 b5 b4 b3 b2 b1 b0 Symbol PD8 Bit symbol PD8_0 PD8_1 PD8_2 PD8_3 PD8_4 Address 03C616 Bit name Port P80 direction register Port P81 direction register Port P82 direction register Port P83 direction register Port P84 direction register Function When reset 00X000002 RW 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) Nothing is assigned. When write, set "0". When read, its content is indeterminate. PD8_6 PD8_7 Port P86 direction register Port P87 direction register 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) Figure 26.4 Direction register (1) Rev.1.00 Aug. 02, 2005 Page 195 REJ09B0187-0100 of 329 M16C/80 Group 26. Programmable I/O Ports Port P11 direction register (Note) b7 b6 b5 b4 b3 b2 b1 b0 Symbol PD11 Address 03CB16, When reset XXX000002 Bit symbol PD11_0 PD11_1 PD11_2 PD11_3 PD11_4 Bit name Port P110 direction register Port P111 direction register Port P112 direction register Port P113 direction register Port P114 direction register Function 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) RW Nothing is assigned. When write, set "0". When read, its content is indeterminate. Note: This register exists in 144-pin version. Port P14 direction register (Note) b7 b6 b5 b4 b3 b2 b1 b0 Symbol PD14 Bit symbol PD14_0 PD14_1 PD14_2 PD14_3 PD14_4 PD14_5 PD14_6 Address 03D216 Bit name Port P140 direction register Port P141 direction register Port P142 direction register Port P143 direction register Port P144 direction register Port P145 direction register Port P146 direction register Function When reset X00000002 RW 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) Nothing is assigned. When write, set "0". When read, its content is indeterminate. Note: This register exists in 144-pin version. Figure 26.5 Direction register (2) Rev.1.00 Aug. 02, 2005 Page 196 of 329 REJ09B0187-0100 M16C/80 Group 26. Programmable I/O Ports Port Pi register (Note 1, 3) Symbol Pi (i = 0 to 15, except 8, 11 and 14) Address 03E016, 03E116, 03E416, 03E516, 03E816, 03E916, 03C016, 03C116, 03C516, 03C816, 03CC16, 03CD16, 03D116 Function Data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : "L" level data 1 : "H" level data (Note 2) (i = 0 to 15 except 8, 11 and 14) When reset Indeterminate b7 b6 b5 b4 b3 b2 b1 b0 Bit symbol PDi_0 PDi_1 PDi_2 PDi_3 PDi_4 PDi_5 PDi_6 PDi_7 Bit name Port Pi0 register Port Pi1 register Port Pi2 register Port Pi3 register Port Pi4 register Port Pi5 register Port Pi6 register Port Pi7 register RW Note 1: In memory expansion and microprocessor mode, the contents of corresponding port Pi direction register of pins A0 to A22, A23, D0 to D15, MA0 to MA12, CS0 to CS 3, WRL/WR/CASL, WRH/BHE/CASH, RD/DW, BCLK/ ALE/CLKOUT, HLDA/ALE, HOLD, ALE/RAS, and RDY are not changed. Note 2: P70 and P71 are N-channel open drain ports and high inpedance outputs. Note 3: Port P12, P13 and P15 registers exist in 144-pin version. Port P8 register b7 b6 b5 b4 b3 b2 b1 b0 Symbol P8 Bit symbol PD8_0 PD8_1 PD8_2 PD8_3 PD8_4 PD8_5 PD8_6 PD8_7 Address 03C416 Bit name Port P80 register Port P81 register Port P82 register Port P83 register Port P84 register Port P85 register Port P86 register Port P87 register When reset Indeterminate Function Data is input and output to and from each pin by reading and writing to and from each corresponding bit (except for P85) 0 : "L" level data 1 : "H" level data RW Figure 26.6 Port register (1) Rev.1.00 Aug. 02, 2005 Page 197 REJ09B0187-0100 of 329 M16C/80 Group 26. Programmable I/O Ports Port P11 register (Note) b7 b6 b5 b4 b3 b2 b1 b0 Symbol P11 Address 03C916 When reset Indeterminate Bit symbol P11_0 P11_1 P11_2 P11_3 P11_4 Bit name Port P110 register Port P111 register Port P112 register Port P113 register Port P114 register Function Data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : "L" level data 1 : "H" level data RW Nothing is assigned. When write, set "0". When read, its content is indeterminate. Note: This register exists in 144-pin version. Port P14 register (Note) b7 b6 b5 b4 b3 b2 b1 b0 Symbol P14 Address 03D016 Bit name Port P140 register Port P141 register Port P142 register Port P143 register Port P144 register Port P145 register Port P146 register Function When reset Indeterminate RW Bit symbol P14_0 P14_1 P14_2 P14_3 P14_4 P14_5 P14_6 Data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : "L" level data 1 : "H" level data Nothing is assigned. When set, write "0". When read, its content is indeterminate. Note: This register exists in 144-pin version. Figure 26.7 Port register (2) Rev.1.00 Aug. 02, 2005 Page 198 of 329 REJ09B0187-0100 M16C/80 Group 26. Programmable I/O Ports Table 26.1 Each port and peripheral output function (Note 1) Port P60 P61 P62 P63 P64 P65 P66 P67 P70(Note 2) P71(Note 2) P72 P73 P74 P75 P76 P77 P80 P81 P82 P83 P84 P85 P86 P87 P90 P91 P92 P93 P94 P95 P96 P97 CLK3 output SCL3 output TXD3(SDA3) output RTS3 output RTS4 output CLK4 output TXD4(SDA4) output SCL3 output STXD4 output STXD3 output TA4OUT output U phase output U phase output TXD1 output TXD2(SDA2) output SCL2 output CLK2 output RTS2 output TA2OUT output W phase output TA3OUT output TA1OUT output V phase output W phase output V phase output TA0OUT output TXD0 output RTS1 output CLK1 output CLKS1 output Periphral output function 1 RTS0 output CLK0 output Periphraloutput function 2 Periphral output function 3 Note 1: When using peripheral input function, set the corresponding function select register A to "0" (I/O port). Note 2: N-channel open drain output. Rev.1.00 Aug. 02, 2005 Page 199 REJ09B0187-0100 of 329 M16C/80 Group 26. Programmable I/O Ports Function select register A0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol PS0 Address 03B016 Bit name When reset 0X000X002 Function 0 : I/O port 1 : RTS0 output 0 : I/O port 1 : CLK0 output RW Bit symbol PS0_0 PS0_1 Port P60 function select bit Port P61 function select bit Nothing is assigned. When write, set "0". When read, the content is indeterminate. PS0_3 PS0_4 Port P63 function select bit Port P64 function select bit 0 : I/O port 1 : TXD0 output 0 : I/O port 1 : Peripheral function output (PSL0_4 enabled) 0 : I/O port 1 : CLK1 output PS0_5 Port P65 function select bit Nothing is assigned. When write, set "0". When read, the content is indeterminate. PS0_7 Port P67 function select bit 0 : I/O port 1 : TXD1 output Function select register A1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol PS1 Address 03B116 When reset X00000002 RW Bit symbol PS1_0 Bit name Port P70 function select bit (Note) Port P71 function select bit (Note) Port P72 function select bit Function 0 : I/O port 1 : Peripheral function output (PSL1_0 enabled) 0 : I/O port 1 : SCL2 output 0 : I/O port 1 : Peripheral function output (PSL1_2, PSC_0 enabled) 0 : I/O port 1 : Peripheral function output (PSL1_3 enabled) 0 : I/O port 1 : Peripheral function output (PSL1_4 enabled) 0 : I/O port 1 : W phase output 0 : I/O port 1 : TA3OUT output PS1_1 PS1_2 PS1_3 Port P73 function select bit PS1_4 Port P74 function select bit PS1_5 PS1_6 Port P75 function select bit Port P76 function select bit Nothing is assigned. When write, set "0". When read, the content is indeterminate. Note: This port is N-channel open drain output. Figure 26.8 Function select register A (1) Rev.1.00 Aug. 02, 2005 Page 200 of 329 REJ09B0187-0100 M16C/80 Group 26. Programmable I/O Ports Function select register A2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol PS2 Address 03B416 Bit name When reset XXXXXX002 Function 0 : I/O port 1 : Peripheral function output (PSL2_0 enabled) 0 : I/O port 1 : U phase output RW Bit symbol PS2_0 Port P80 function select bit PS2_1 Port P81 function select bit Nothing is assigned. When write, set "0". When read, the content is indeterminate. Function select register A3 (Note) b7 b6 b5 b4 b3 b2 b1 b0 Symbol PS3 Address 03B516 When reset 0016 RW Bit symbol PS3_0 PS3_1 Bit name Port P90 function select bit Port P91 function select bit Function 0 : I/O port 1 : CLK3 output 0 : I/O port 1 : Peripheral function output (PSL3_1 enabled) 0 : I/O port 1 : TxD3(SDA3) output 0 : I/O port 1 : RTS3 output 0 : I/O port 1 : RTS4 output 0 : I/O port 1 : CLK4 output 0 : I/O port 1 : TxD4(SDA4) output 0 : I/O port 1 : Peripheral function output (PSL3_7 enabled) PS3_2 PS3_3 PS3_4 PS3_5 PS3_6 PS3_7 Port P92 function select bit Port P93 function select bit Port P94 function select bit Port P95 function select bit Port P96 function select bit Port P97 function select bit Note: Set bit 2 of protect register (address 000A16) to "1" before rewriting to this register. Figure 26.9 Function select register A (2) Rev.1.00 Aug. 02, 2005 Page 201 REJ09B0187-0100 of 329 M16C/80 Group 26. Programmable I/O Ports Function select register B0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol PSL0 Address 03B216 When reset XXX0XXXX2 RW Bit name Function Bit symbol Nothing is assigned. When write, set "0". When read, the content is indeterminate. PSL0_4 Port P64 peripheral function select bit (Enabled when PS0_4 = 1) 0 : RTS1 output 1 : CLKS1 output Nothing is assigned. When write, set "0". When read, the content is indeterminate. Function select register B1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol PSL1 Address 03B316 When reset XXX000X02 RW Bit symbol PSL1_0 Bit name Port P70 peripheral function select bit (Enabled when PS1_0 = 1) (Note 2) Function 0 : TxD2(SDA2) port 1 : TA0OUT output Nothing is assigned. When write, set "0". When read, the content is indeterminate. PSL1_2 Port P72 peripheral function select bit (Enabled when PS1_2 = 1) Port P73 peripheral function select bit (Enabled when PS1_3 = 1) Port P74 peripheral function select bit (Enabled when PS1_4 = 1) 0 : Port P72 peripheral subfunction select bit (PSC_0) is enabled 1 : TA1OUT output (Note 1) 0 : RTS2 port 1 : V phase output 0 : TA2OUT port 1 : W phase output PSL1_3 PSL1_4 Nothing is assigned. When write, set "0". When read, the content is indeterminate. Note 1: Set PSC_0 to "1". Note 2: This port is N-channel open drain output. Function select register B2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol PSL2 Bit symbol PSL2_0 Address 03B616 Bit name When reset XXXXXXX02 Function 0 : TA4OUT output 1 : U phase output RW Port P80 peripheral function select bit (Enabled when PS2_0 = 1) Nothing is assigned. When write, set "0". When read, the content is indeterminate. Figure 26.10 Function select register B (1) Rev.1.00 Aug. 02, 2005 Page 202 of 329 REJ09B0187-0100 M16C/80 Group 26. Programmable I/O Ports Function select register B3 b7 b6 b5 b4 b3 b2 b1 b0 Symbol PSL3 Bit symbol Address 03B716 Bit name When reset 00000X0X2 Function RW Nothing is assigned. When write, set "0". When read, the content is indeterminate. PSL3_1 Port P91 peripheral function select bit 0 : SCL3 output 1 : STxD3 output Nothing is assigned. When write, set "0". When read, the content is indeterminate. PSL3_3 Port P93 peripheral function 0 : Input peripheral function enabled (Except DA0 output) (Note) 1 : Input peripheral function disabled (DA0 output) 0 : Input peripheral function enabled (Except DA1 output) (Note) 1 : Input peripheral function disabled (DA1 output) 0 : Input peripheral function enabled (Except ANEX0 use) (Note) 1 : Input peripheral function disabled (ANEX0 use) 0 : Input peripheral function enabled (Except ANEX1 use) (Note) 1 : Input peripheral function disabled (ANEX1 use) 0 : SCL4 output 1 : STxD4 output PSL3_4 Port P94 peripheral function PSL3_5 Port P95 peripheral function PSL3_6 Port P96 peripheral function PSL3_7 Port P97 peripheral function select bit Note: Although DA0, DA1 output and ANEX0, ANEX1 can be used when "0" is set in these bits, the power supply may be increased. Figure 26.11 Function select register B (2) Function select register C b7 b6 b5 b4 b3 b2 b1 b0 Symbol PSC Address 03AF16 When reset 0XXXXXX02 RW Bit symbol PSC_0 (Note 1) Bit name Port P72 peripheral subfunction select bit (Enabled when PS1_2 = 1 and PSL1_2 = 0) Function 0 : CLK2 output 1 : V phase output Nothing is assigned. When write, set "0". When read, the content is indeterminate. PSC_7 (Note 2) Key input interrupt disable bit 0 : Enabled 1 : Disabled Note 1: Set this bit to "0" when PSL1_2 = "1". Note 2: When this bit is "1", key input interrupt for interrupt controller is disabled regardless of port input and setting of interrupt control register. When changing this bit, set key input interrupt disabled by key input interrupt control register. Figure 26.12 Function select register C Rev.1.00 Aug. 02, 2005 Page 203 REJ09B0187-0100 of 329 M16C/80 Group 26. Programmable I/O Ports Pull-up control register 0 (Note) b7 b6 b5 b4 b3 b2 b1 b0 Symbol PUR0 Bit symbol PU00 PU01 PU02 PU03 PU04 PU05 PU06 PU07 Address 03F016 Bit name P00 to P03 pull-up P04 to P07 pull-up P10 to P13 pull-up P14 to P17 pull-up P20 to P23 pull-up P24 to P27 pull-up P30 to P33 pull-up P34 to P37 pull-up When reset 0016 Function The corresponding port is pulled high with a pull-up resistance 0 : Not pulled high 1 : Pulled high RW Note: Since P0 to P5 operate as the bus in memory expansion mode and microprocessor mode, do not set the pull-up control register. However, it is possible to select pullup resistance presence to the usable port as I/O port by setting. Pull-up control register 1 (Note) b7 b6 b5 b4 b3 b2 b1 b0 Symbol PUR1 Bit symbol PU10 PU11 PU12 PU13 Address 03F116 Bit name P40 to P43 pull-up P44 to P47 pull-up P50 to P53 pull-up P54 to P57 pull-up When reset X016 Function The corresponding port is pulled high with a pull-up resistance 0 : Not pulled high 1 : Pulled high RW Nothing is assigned. When write, set "0". When read, their contents are indeterminate. Note: Since P0 to P5 operate as the bus in memory expansion mode and microprocessor mode, do not set the pull-up control register. However, it is possible to select pullup resistance presence to the usable port as I/O port by setting. Pull-up control register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol PUR2 Bit symbol PU20 PU21 PU22 PU23 PU24 PU25 PU26 PU27 Address 03DA16 Bit name P60 to P63 pull-up When reset 0016 Function RW The corresponding port is pulled high with a pull-up resistance P64 to P67 pull-up 0 : Not pulled high P70 to P73 pull-up (Note 1) 1 : Pulled high P74 to P77 pull-up P80 to P83 pull-up P84 to P87 pull-up (Note 2) P90 to P93 pull-up P94 to P97 pull-up Note 1: Since P70 and P71 are N-channel open drain ports, pull-up is not available for them. Note 2: Except port P85. Figure 26.13 Pull-up control register (1) Rev.1.00 Aug. 02, 2005 Page 204 of 329 REJ09B0187-0100 M16C/80 Group 26. Programmable I/O Ports 100-pin version Pull-up control register 3 b7 b6 b5 b4 b3 b2 b1 b0 000000 Symbol PUR3 Bit symbol PU30 PU31 Reserved bit Address 03DB16 Bit name P100 to P103 pull-up P104 to P107 pull-up When reset 0016 Function The corresponding port is pulled high with a pull-up resistance 0 : Not pulled high 1 : Pulled high Must always be set to "0" RW 144-pin version Pull-up control register 3 b7 b6 b5 b4 b3 b2 b1 b0 Symbol PUR3 Bit symbol PU30 PU31 PU32 PU33 PU34 PU35 PU36 PU37 Address 03DB16 Bit name P100 to P103 pull-up P104 to P107 pull-up P110 to P113 pull-up P114 pull-up P120 to P123 pull-up P124 to P127 pull-up P130 to P133 pull-up P134 to P137 pull-up When reset 0016 Function The corresponding port is pulled high with a pull-up resistance 0 : Not pulled high 1 : Pulled high RW Pull-up control register 4 (Note) b7 b6 b5 b4 b3 b2 b1 b0 Symbol PUR4 Bit symbol PU40 PU41 PU42 PU43 Address 03DC16 Bit name P140 to P143 pull-up P144 to P146 pull-up P150 to P153 pull-up P154 to P157 pull-up When reset XXXX00002 Function The corresponding port is pulled high with a pull-up resistance 0 : Not pulled high 1 : Pulled high RW Nothing is assigned. When write, set "0". When read, their contents are "0". Note: This register exists in 144-pin version. Figure 26.14 Pull-up control register (2) Rev.1.00 Aug. 02, 2005 Page 205 REJ09B0187-0100 of 329 M16C/80 Group 26. Programmable I/O Ports Port control register (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbpl PCR Bit symbol PCR0 Address 03FF16 Bit name Port P1 control register When reset XXXXXXX02 Function 0 : Function as common CMOS port 1 : Function as N-ch open drain port (Note 2) RW Nothing is assigned. When write, set "0". When read, their contents are indeterminate. Note 1: Since P1 operates as the data bus in memory expansion mode and microprocessor mode, do not set the port control register. However, it is possible to select the CMOS port or N-channel open drain to the usable port as I/O port by setting. Note 2: This function is designed to permanently turn OFF the Pch of the CMOS port. It does not make port 1 a full open drain. Therefore, the absolute maximum input voltage rating is [-3 to Vcc + 0.3V]. Figure 26.15 Port control register Rev.1.00 Aug. 02, 2005 Page 206 of 329 REJ09B0187-0100 M16C/80 Group 26. Programmable I/O Ports Table 26.2 Example connection of unused pins in single-chip mode Pin name Connection Ports P0 to P15 (excluding P85) ( After setting for input mode, connect every pin to VSS via a resistance (pull-down); or after setting for output mode, leave these pins open. Note 1) XOUT (Note 2) NMI AVCC AVSS, VREF, BYTE Open Connect via resistance to VCC (pull-up) Connect to VCC Connect to VSS Note 1: Port P11 to P15 exist in 144-pin version. Note 2: With external clock input to XIN pin. Table 26.3 Example connection of unused pins in memory expansion mode and microprocessor mode Pin name Connection Ports P6 to P15(excluding P85) ( After setting for input mode, connect every pin to VSS via a resistance (pull-down); or after setting for output mode, leave these pins open. Note 1) Open BHE, ALE, HLDA, XOUT(Note 2), BCLK HOLD, RDY, NMI AVCC AVSS, VREF Connect via resistance to VCC (pull-up) Connect to VCC Connect to VSS Note 1: Port P11 to P15 exist in 144-pin version. Note 2: With external clock input to XIN pin. Microcomputer Port P0 to P15 (except for P85) (Note) (Input mode) * * * (Input mode) (Output mode) Microcomputer Port P6 to P15 (except for P85) (Note) (Input mode) * * * (Input mode) (Output mode) * * * * * * Open Open NMI XOUT Open VCC AVCC BYTE AVSS VREF VSS NMI BHE HLDA ALE XOUT BCLK HOLD RDY AVCC AVSS VREF Open VCC VSS In single-chip mode Note: Port P11 to P15 exist in 144-pin version. In memory expansion mode or in microprocessor mode Figure 26.16 Example connection of unused pins Rev.1.00 Aug. 02, 2005 Page 207 REJ09B0187-0100 of 329 M16C/80 Group 27. Usage Precaution 27. Usage Precaution SFR (100-pin version) (1) Addresses 03C916, 03CB16 to 03D316 , 03DC16 area is for future plan. Must set "FF16" to address 03CB16, 03CE16, 03CF16, 03D216, 03D316 and "0016" to address 03DC16 at initial setting. Timer (1) A timer Ai register and a timer Bi register are unstable after MCU resetting. Please start a count after setting a value as the timer Ai register or timer Bi register to be used, when using a timer. Timer A (timer mode) (1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer Ai register with the reload timing gets "FFFF16". Reading the timer Ai register after setting a value in the timer Ai register with a count halted but before the counter starts counting gets a proper value. Timer A (event counter mode) (1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer Ai register with the reload timing gets "FFFF16" by underflow or "000016" by overflow. Reading the timer Ai register after setting a value in the timer Ai register with a count halted but before the counter starts counting gets a proper value. (2) When stop counting in free run type, set timer again. (3) In the case of using as "Free-Run type", the timer register contents may be unknown when counting begins. If the timer register is set before counting has started, then the starting value will be unknown. * In the case where the up/down count will not be changed. Enable the "Reload" function and write to the timer register before counting begins. Rewrite the value to the timer register immediately after counting has started. If counting up, rewrite "000016" to the timer register. If counting down, rewrite "FFFF16" to the timer register. This will cause the same operation as "Free-Run type" mode. * In the case where the up/down count has changed. First set to "Reload type" operation. Once the first counting pulse has occurred, the timer may be changed to "Free-Run type". Rev.1.00 Aug. 02, 2005 Page 208 of 329 REJ09B0187-0100 M16C/80 Group 27. Usage Precaution Timer A (one-shot timer mode) (1) Setting the count start flag to "0" while a count is in progress causes as follows: * The counter stops counting and a content of reload register is reloaded. * The TAiOUT pin outputs "L" level. * The interrupt request generated and the timer Ai interrupt request bit goes to "1". (2) The output from the one-shot timer synchronizes with the count source generated internally. Therefore, when an external trigger has been selected, a delay of one cycle of count source as maximum occurs between the trigger input to the TAiIN pin and the one-shot timer output. (3) The timer Ai interrupt request bit goes to "1" if the timer's operation mode is set using any of the following procedures: * Selecting one-shot timer mode after reset. * Changing operation mode from timer mode to one-shot timer mode. * Changing operation mode from event counter mode to one-shot timer mode. Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to "0" after the above listed changes have been made. (4) If a trigger occurs while a count is in progress, after the counter performs one down count following the reoccurrence of a trigger, the reload register contents are reloaded, and the count continues. To generate a trigger while a count is in progress, generate the second trigger after an elapse longer than one cycle of the timer's count source after the previous trigger occurred. (5) If an external trigger input is used to start counting, the next external trigger input must be avoided within 300ns before the timer A reaches "0000h". Timer A (pulse width modulation mode) (1) The timer Ai interrupt request bit becomes "1" if setting operation mode of the timer in compliance with any of the following procedures: * Selecting PWM mode after reset. * Changing operation mode from timer mode to PWM mode. * Changing operation mode from event counter mode to PWM mode. Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to "0" after the above listed changes have been made. (2) Setting the count start flag to "0" while PWM pulses are being output causes the counter to stop counting. If the TAiOUT pin is outputting an "H" level in this instance, the output level goes to "L", and the timer Ai interrupt request bit goes to "1". If the TAiOUT pin is outputting an "L" level in this instance, the level does not change, and the timer Ai interrupt request bit does not becomes "1". Rev.1.00 Aug. 02, 2005 Page 209 REJ09B0187-0100 of 329 M16C/80 Group 27. Usage Precaution Timer B (timer mode, event counter mode) (1) The TBi (i=0 to 5) register indicates the countervalue during counting at any given time. However, the counter is "FFFF16" when reloading. The setting value can be read after setting the TBi register while the counter stops and before the counter starts counting. Timer B (pulse period/pulse width measurement mode) (1) If the measurement mode select bit setting is changed after counting is started, the timer Bi interrupt request bit is set to "1". (2) Indeterminate values are transferred to the reload register during the first valid edge input after counting is started. The timer Bi interrupt request is not generated at this time. (3) The counter value is indeterminate when counting is started. Therefore, the timer Bi overflow flag setting may change to "1" and causes the timer Bi interrupt requests to be generated until a valid edge is input after counting is started. (4) The timer Bi overflow flag is set to "0" by writting to the timer Bi mode register at or after counting timing of the next count source, after the count start flag is set to "1" and the timer Bi overflow flag is set to "1". Stop Mode and Wait Mode (1) To exit stop mode by hardware reset, provide an "L" signal input to the RESET pin until main clock oscillation is stable. (2) When entering wait mode, the instruction queue reads ahead to instructions following the WAIT instruction, and the program stops. Write at least 4 NOP instructions after the WAIT instruction. (3) When entering stop mode, the instruction lined in the instruction queue is executed before the interrupt for recovery is done. Write the JMP.B instruction, as follows, after the instruction setting the all clock stop control bit to "1". bset 0,prcr ; protection removed bset 0,cm1 ; all clocks stopped (entering stop mode) jmp.b LABEL_001 ; JMP.B instruction executed (Jump to the next instruction soon LABEL_001: ; with no instruction between JMP.B and LABEL.) nop ; nop(1) nop ; nop(2) nop ; nop(3) nop ; nop(4) mov.b #0,prcr ; protection set Rev.1.00 Aug. 02, 2005 Page 210 of 329 REJ09B0187-0100 M16C/80 Group 27. Usage Precaution (4) Use the following procedure to enter stop mode. * Initial Setting Set each interrupt priority level after setting the interrupt priority level required to exit stop mode, controlled by the RLVL2 to RLVL0 bits in the RLVL register, to "7". * Before Entering Stop Mode [1] Set the interrupt priority level of the interrupt being used to exit stop mode [2] Set the interrupt priority levels of the interrupts, not being used to exit stop mode, to "0". [3] Set the IPL in the FLG register. Then set the exit priority level to the same level as the IPL. (Interrupt priority level of the interrupt used to exit stop mode > exit priority level interrupt priority level of the interrupts not used to exit stop mode) [4] Set the I flag to "1" [5] Set the CM10 bit in the CM1 register to "1" (all clocks stop) after setting the PRC0 bit in the PRCR register to "1" (write enabled) * After Exiting Stop Mode Set the exit priority level to "7" as soon as exiting stop mode. (5) When microcomputer enters stop mode again after exiting from stop mode using the NMI interrupt, use the following procedure to set the CM10 bit to "1". [1] Exit stop mode using the NMI interrupt [2] Generate a dummy interrupt [3] Set the CM10 bit to "1" Example: INT BSET #63 CM1 ; Dummy interrupt ; All clocks stopped (in stop mode) ; /*for dummy interrupt* / DUMMY: REIT (6) Use the following procedure to enter wait mode. * Initial Setting Set each interrupt priority level after setting the interrupt priority level required to exit wait mode, controlled by the RLVL2 to RLVL0 bits in the RLVL register, to "7". * Before Entering Wait Mode [1] Set the interrupt priority level of the interrupt being used to exit wait mode [2] Set the interrupt priority levels of the interrupts, not being used to exit wait mode, to "0". [3] Set the IPL in the FLG register. Then set the exit priority level to the same level as the IPL. (Interrupt priority level of the interrupt used to exit wait mode > exit priority level interrupt priority level of the interrupts not used to exit wait mode) [4] Set the I flag to "1" [5] Execute the WAIT instruction * After Exiting Wait Mode Set the exit priority level to "7" as soon as exiting wait mode. Rev.1.00 Aug. 02, 2005 Page 211 REJ09B0187-0100 of 329 M16C/80 Group 27. Usage Precaution A/D Converter (1) Write to each bit (except bit 6) of A/D control register 0, to each bit of A/D control register 1, and to bit 0 of A/D control register 2 when A/D conversion is stopped (before a trigger occurs). In particular, when the Vref connection bit is changed from "0" to "1", start A/D conversion after an elapse of 1 s or longer. (2) When changing A/D operation mode, select analog input pin again. (3) Using one-shot mode or single sweep mode Read the correspondence A/D register after confirming A/D conversion is finished. (It is known by A/ D conversion interrupt request bit.) Use the undivided main clock as the internal CPU clock. (4) Using repeat mode, repeat sweep mode 0 or repeat sweep mode 1 (5) When f(XIN) is faster than 10 MHz, make the frequency 10 MHz or less by dividing. (6) If A/D conversion is stopped by program while in progress of A/D conversion, the conversion result of A/D converter becomes indeterminate. The contents of A/D registers irrelevant to A/D conversion may become indeterminate. If A/D conversion is stopped by program while in progress of A/D conversion, ignore the values of all A/D registers. (7) Output impedance of sensor at A/D conversion (Reference value) To carry out A/D conversion properly, charging the internal capacitor C shown in Figure 27.1 has to be completed within a specified period of time T. Let output impedance of sensor equivalent circuit be R0, microcomputer's internal resistance be R, precision (error) of the A/D converter be X, and the A/ D converter's resolution be Y (Y is 1024 in the 10-bit mode, and 256 in the 8-bit mode). Vc is generally VC = VIN {1 - e - And when t = T, VC=VIN - t C (R0 + R) } X VIN=VIN(1 - X ) Y Y = X Y X Y e- - Hence, R0 = - T C (R0 + R) T =ln C (R0 +R) T -R X Y C * ln Rev.1.00 Aug. 02, 2005 Page 212 of 329 REJ09B0187-0100 M16C/80 Group 27. Usage Precaution With the model shown in Figure 27.1 as an example, when the difference between VIN and VC becomes 0.1LSB, we find impedance R0 when voltage between pins VC changes from 0 to VIN-(0.1/1024) VIN in time T. (0.1/1024) means that A/D precision drop due to insufficient capacitor charge is held to 0.1LSB at time of A/D conversion in the 10-bit mode. Actual error however is the value of absolute precision added to 0.1LSB. When f(XIN) = 10 MHz, T = 0.3 us in the A/D conversion mode with sample & hold. Output impedance R0 for sufficiently charging capacitor C within time T is determined as follows. T = 0.3 s, R = 7.8 k, C = 3 pF, X = 0.1, and Y = 1024 . Hence, R0 = - 0.3 X 10-6 3.0 X 10 -12 * ln 0.1 1024 -7.8 X103 3.0 X 103 Thus, the allowable output impedance of the sensor circuit capable of thoroughly driving the A/D converter turns out to be approximately 3.0 k. Tables 27.1 and 27.2 show output impedance values based on the LSB values. Microcomputer Sensor Equivalent Circuit R0 VIN R (7.8k ) C (3.0pF) VC Figure 27.1 Anolog Input Pin and External Sensor Equivalent Circuit Rev.1.00 Aug. 02, 2005 Page 213 REJ09B0187-0100 of 329 M16C/80 Group 27. Usage Precaution Tables 27.1 Output impedance values based on the LSB values (10-bit mode) Reference value f(XIN) (MHz) 10 Cycle (s) 0.1 Sampling time (s) 0.3 (3 X cycle, Sample & hold bit is enabled) R (Kohm) 7.8 C (pF) 3.0 Resolution (LSB) 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 R0max (Kohm) 3.0 4.5 5.3 5.9 6.4 6.8 7.2 7.5 7.8 8.1 0.4 0.9 1.3 1.7 2.0 2.2 2.4 2.6 2.8 10 0.1 0.2 (2 X cycle, Sample & hold bit is enabled) 7.8 3.0 Tables 27.2 Output impedance values based on the LSB values (8-bit mode) Reference value f(XIN) (MHz) 10 Cycle (s) 0.1 Sampling time (s) 0.3 (3 X cycle, Sample & hold bit is enabled) R (Kohm) 7.8 C (pF) 3.0 Resolution (LSB) 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 R0max (Kohm) 4.9 7.0 8.2 9.1 9.9 10.5 11.1 11.7 12.1 12.6 0.7 2.1 2.9 3.5 4.0 4.4 4.8 5.2 5.5 5.8 10 0.1 0.2 (2 X cycle, Sample & hold bit is enabled) 7.8 3.0 Rev.1.00 Aug. 02, 2005 Page 214 of 329 REJ09B0187-0100 M16C/80 Group 27. Usage Precaution Interrupts (1) Setting the stack pointer * The value of the stack pointer is initialized to 00000016 immediately after reset. Accepting an interrupt before setting a value in the stack pointer may cause runaway. Be sure to set a value in the stack pointer before accepting an interrupt. _______ When using the NMI interrupt, initialize the stack pointer at the beginning of a program. Regard_______ ing the first instruction immediately after reset, generating any interrupts including the NMI interrupt is prohibited. Set an even address to the stack pointer so that operating efficiency is increased. _______ (2) The NMI interrupt _______ * As for the NMI interrupt pin, an interrupt cannot be prohibited. Connect it to the VCC pin via a resistance (pulled-up) if unused. _______ * The NMI pin also serves as P85, which is exclusively input. Reading the contents of the P8 register allows reading the pin value. Use the reading of this pin only for establishing the pin level _______ at the time when the NMI interrupt is input. _______ * Signals input to NMI pin require "L" level and "H" level of 2 clock + 300ns or more, from the operation clock of CPU. (3) Address match interrupt * Do not set the following addresses to the address match interrupt register. 1. The address of the starting instruction in an interrupt routine. 2. Any of the next 7 instructions addresses immediately after an instruction to clear an interrupt request bit of an interrupt control register or an instruction to rewrite an interrupt priority level to a smaller value. 3. Any of the next 3 instructions addresses immediately after an instruction to set the interrupt enable flag (I flag). 4. Any of the next 3 instructions addresses immediately after an instruction to rewrite a processor interrupt priority level (IPL) to a smaller value. Example 1) Interrupt_A: ; Interrupt A routine pushm R0,R1,R2,R3,A0,A1 ; <---- Do not set address match interrupt to the start address of an interrupt instruction **** ; Example 2) mov.b #0,TA0IC ;Change TA0 interrupt priority level to a smaller value nop ; 1st instruction nop ; 2nd instruction nop ; 3rd instruction Do not set address match interrupt nop ; 4th instruction during this period nop ; 5th instruction nop ; 6th instruction nop ; 7th instruction Example 3) fset I ; Set I flag ( interrupt enabled) nop ; 1st instruction Do not set address match interrupt nop ; 2nd instruction during this period nop ; 3rd instruction Rev.1.00 Aug. 02, 2005 Page 215 REJ09B0187-0100 of 329 M16C/80 Group 27. Usage Precaution Example 4) ldipl #0 nop nop nop ; Rewrite IPL to a smaller value ; 1st instruction Do not set address match interrupt ; 2nd instruction during this period ; 3rd instruction * To return from an interrupt to the address set in an address match interrupt register using return instruction (reit or freit) To rewrite the interrupt control register within the interrupt routine, add the below processing to the end of the routine (immediately before the reit or freit instruction). Also, if multiple interrupts are enabled with other interrupts, add the below processing to the end of the interrupt that enables the multiple interrupts. If the interrupt control register is being rewritten within the non-maskable interrupt routine, add the below processing to the end of all interrupts. Additional process fclr U pushm R0 mov.w 6[SP],R0 ldc R0,FLG popm R0 nop reit ; Execute after the register reset instruction (popm instruction) ; Select ISP (Unnecessary if the ISP has been selected) ; Store R0 register ; Read FLG on stack (use "stc SVF,R0" when high-speed ; interrupt) ; Set in FLG ; Restore R0 register ; Dummy ; Interrupt completed (use freit when high-speed interrupt) Example 5) If rewriting the interrupt control register for interrupt B with the interrupt A routine and enabling multiple interrupts with interrupt C, the above processing is required at the end of the interrupt A and interrupt C routines. Interrupt A routine Interrupt_A: pushm R0,R1,R2,R3,A0,A1 **** bclr 3,TA0IC **** popm R0,R1,R2,R3,A0,A1 fclr U pushm R0 mov.w 6[SP],R0 ldc R0,FLG popm R0 nop reit ; Store registers ; Rewrite interrupt control register of interrupt B ; Restore registers ; Select ISP (Unnecessary if the ISP has been selected) ; Store R0 register ; Read FLG on stack ; Set in FLG ; Restore R0 register ; Dummy ; Interrupt completed Rev.1.00 Aug. 02, 2005 Page 216 of 329 REJ09B0187-0100 M16C/80 Group 27. Usage Precaution Interrupt C routine Interrupt_C: pushm R0,R1,R2,R3,A0,A1 fset I **** **** popm R0,R1,R2,R3,A0,A1 fclr U pushm R0 mov.w 6[SP],R0 ldc R0,FLG popm R0 nop reit (4) External interrupt ; Store registers ; Multiple interrupt enabled ;Restore registers ; Select ISP (Unnecessary if the ISP has been selected) ; Store R0 register ; Read FLG on stack ; Set in FLG ; Restore R0 register ; Dummy ; Interrupt completed * Edge sense Either an "L" level or an "H" level of at least 250 ns width is necessary for the signal input to pins INT0 to INT5 regardless of the CPU operation clock. * Level sense Either an "L" level or an "H" level of 1 cycle of BCLK + at least 200 ns width is necessary for the signal input to pins INT0 to INT5 regardless of the CPU operation clock. (When XIN=20MHz and no division mode, at least 250 ns width is necessary.) * When the polarity of the INT0 to INT5 pins is changed, the interrupt request bit is sometimes set to "1". After changing the polarity, set the interrupt request bit to "0". Figure 27.2 shows the procedure for ______ changing the INT interrupt generate factor. Set the interrupt priority level to level 0 (Disable INT interrupt) Set the polarity select bit Clear the interrupt request bit to "0" Set the interrupt priority level to level 1 to 7 (Enable the accepting of INT interrupt request) ______ Figure 27.2 Switching condition of INT interrupt request Rev.1.00 Aug. 02, 2005 Page 217 REJ09B0187-0100 of 329 M16C/80 Group 27. Usage Precaution (5) Rewrite the interrupt control register * When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been generated. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : AND, OR, BCLR, BSET * When attempting to clear the interrupt request bit of an interrupt control register, the interrupt request bit is not cleared sometimes. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : MOV DMAC (1) Do not clear the DMA request bit of the DMAi request cause select register. In M16C/80, when a DMA request is generated while the channel is disabled (Note), the DMA transfer is not executed and the DMA request bit is cleared automatically. Note :The DMA is disabled or the transfer count register is "0". (2) When DMA transfer is done by a software trigger, set DSR and DRQ of the DMAi request cause select register to "1" simultaneously using the OR instruction. e.g.) OR.B #0A0h, DMiSL ; DMiSL is DMAi request cause select register (3) When changing the DMAi request cause select bit of the DMAi request cause select register, set "1" to the DMA request bit, simultaneously. In this case, set the corresponding DMA channel to disabled before changing the DMAi request cause select bit. At least 26 cycles are needed from the instruction to write to the DMAi request cause select register to enable DMA. Example) When DMA request cause is changed to timer A0 and using DMA0 in single transfer after DMA initial setting push.w R0 ; Store R0 register stc DMD0, R0 ; Read DMA mode register 0 and.b #11111100b, R0L ; Clear DMA0 transfer mode select bit to "00" ldc R0, DMD0 ; DMA0 disabled mov.b #10000011b, DM0SL ; Select timer A0 ; (Write "1" to DMA request bit simultaneously) push.w R0 ; Sotre R0 register mov.w #6,R0 ; At least 26 cycles are dummy_loop: needed until DMA sbjnz.w #1,R0,dummy_loop ; Dummy cycle enabled. pop.w R0 ; Restore R0 register or.b #00000001b, R0L ; Set DMA0 single transfer ldc R0, DMD0 ; DMA0 enabled pop.w R0 ; Restore R0 register Rev.1.00 Aug. 02, 2005 Page 218 of 329 REJ09B0187-0100 M16C/80 Group 27. Usage Precaution (4) Recommended procedure for starting DMA transfer *When writing to the DMAi request cause register including overwriting the same value to the DMAi request cause register; 1. Disable the corresponding channel i DMA in DMA mode registers 0 and 1. 2. Set up the peripheral used as the source of the DMA transfer. However, the peripheral should remain disabled at this time. For example, when using UART0 transmit, disable UART0 transmit. 3. Set the DMAi request cause select register. At this time, write a '1' to the DMA request bit (bit 7) 4. Set the following SFR registers: *DMAiSFR address register *DMAI memory address reload register *DMAi memory address register *DMAi transfer count reload register *DMAi transfer count register 5. At this point, if the number of elapsed cycles are less than 26, add code (NOP's or other processing) to make up some time. 6. Enable the corresponding channel i DMA in the DMA mode registers 0 and 1. 7. Enable the peripheral used as the source of the DMA transfer. For example, when using UART0 transmit, enable UART0 transmit. *When not writing to the DMAi request cause register; 1. Disable the corresponding channel i DMA in the DMA mode registers 0 and 1. 2. Set up the peripheral used as the source of the DMA transfer. However, the peripheral should remain disabled at this time. For example, when using UART0 transmit, disable UART0 transmit. 3. Set up the following SFR registers: *DMAiSFR address register *DMAI memory address reload register *DMAi memory address register *DMAi transfer count reload register *DMAi transfer count register 4. Enable the corresponding channel i DMA in the DMA mode registers 0 and 1. 5. Enable the peripheral used as the source of the DMA transfer. For example, when using UART0 transmit, enable UART0 transmit. (5) Recommended procedure after completing DMA transfer *Disable the peripheral used as source of the DMA transfer to prevent generating a DMA request. *Disable the corresponding channel i DMA in the DMA mode registers 0 and 1. Rev.1.00 Aug. 02, 2005 Page 219 REJ09B0187-0100 of 329 M16C/80 Group 27. Usage Precaution Noise (1) A bypass capacitor should be inserted between Vcc-Vss line for reducing noise and latch-up Connect a bypass capacitor (approx. 0.1F) between the Vcc and Vss pins using short wiring and thicker circuit traces. Precautions for using CLKOUT pin When using the Clock Output function of P53/CLKOUT pin (f8, f32 or fc output) in single chip mode, use port P57 as an input only port (port P57 direction register is "0"). Although port P57 may be set as an output port, it will become high impedance and will not output "H" or "L" levels. __________ HOLD signal When P40 to P47 and P50 to P52 are set to output port (the direction register is "1") in single-chip mode, then the MCU is changed to microprocessor mode or memory expansion mode. __________ _______ _______ _______ Although the HOLD pin may be held "L", P40 to P47 (A16 to A23, CS0 to CS3, MA8 to MA12) _____ _____ _______ _____ _______ _______ _________ _________ _____ and P50 to P52 (RD/WR/BHE, RD/WRL/WRH, CASL/CASH/DW) will not become high-impedance ports. __________ When using the HOLD input while P40 to P47 and P50 to P52 are set as output ports in single-chip mode, you must first set all pins for P40 to P47 and P50 to P52 as input ports, then shift to microprocessor mode or memory expansion mode. Rev.1.00 Aug. 02, 2005 Page 220 of 329 REJ09B0187-0100 M16C/80 Group 27. Usage Precaution Reducing power consumption (1) When A/D conversion is not performed, select the Vref not connected with the Vref connect bit of A/D control register 1. When A/D conversion is performed, start the A/D conversion at least 1 s or longer after connecting Vref. (2) When using AN4 (P104) to AN7 (P107), select the input disable of the key input interrupt signal with the key input interrupt disable bit of the function select register C . When selecting the input disable of the key input interrupt signal, the key input interrupt cannot be used. Also, the port cannot be input even if the direction register of P104 to P107 is set to input (the input result becomes undefined). When the input disable of the key input interrupt signal is selected, use all AN4 to AN7 as A/D inputs. (3) When ANEX0 and ANEX1 are used, select the input peripheral function disable with port P95 and P96 input peripheral function select bit of the function select register B3. When the input peripheral function disable is selected, the port cannot be input even if the port direction register is set to input (the input result becomes undefined). Also, it is not possible to input a peripheral function except ANEX0 and ANEX1. (4) When D/A converter is not used, set output disabled with the D/A output enable bit of D/A control register and set the D/A register to "0016". (5) When D/A conversion is used, select the input peripheral function disabled with port P93 and P94 input peripheral function select bit of the function select register B3. When the input peripheral function disabled is selected, the port cannot be input even if the port direction register is set to input (the input result becomes undefined). Also, it is not possible to input a peripheral function. DRAM controller When shifting to self-refresh, select DRAM ignored by the DRAM space select bit. In the next instruction, simultaneously set the DRAM space select bit and self-refresh ON by self-refresh mode bit. Also, insert two NOPs after the instruction that sets the self-refresh mode bit to "1". Do not access external memory while operating in self-refresh. (All external memory space access is inhibited. ) When disabling self-refresh, simultaneously select DRAM ignored by the DRAM space select bit and selfrefresh OFF by self-refresh mode bit. In the next instruction, set the DRAM space select bit. Do not access the DRAM space immediately after setting the DRAM space select bit. Example) One wait is selected by the wait select bit and 4MB is selected by the DRAM space select bit Shifting to self-refresh *** mov.b #00000001b,DRAMCONT ;DRAM ignored, one wait is selected mov.b #10001011b,DRAMCONT ;Set self-refresh, select 4MB and one wait nop ;Two nops are needed nop ; *** Disable self-refresh *** mov.b #00000001b,DRAMCONT mov.b nop nop *** #00001011b,DRAMCONT ;Disable self-refresh, DRAM ignored, one wait is ;selected ;Select 4MB and one wait ;Inhibit instruction to access DRAM area Rev.1.00 Aug. 02, 2005 Page 221 REJ09B0187-0100 of 329 M16C/80 Group 27. Usage Precaution Setting the registers The registers shown in Table 27.3 include indeterminate bit when read. Set immidiate to these registers. Store the content of the frequently used register to RAM, change the content of RAM, then transfer to the register. Table 27.3 The object registers Register name UART4 bit rate generator UART4 transfer buffer register Dead time timer Timer B2 interrupt occurrence frequency set counter UART3 bit rate generator UART3 transfer buffer register UART2 bit rate generator UART2 transfer buffer register Up-down flag Timer A0 register (Note) Timer A1 register (Note) Timer A2 register (Note) Timer A3 register (Note) Timer A4 register (Note) UART0 bit rate generator UART0 transfer buffer register UART1 bit rate generator UART1 transfer buffer register Symbol U4BRG U4TB DTT ICTB2 U3BRG U3TB U2BRG U2TB UDF TA0 TA1 TA2 TA3 TA4 U0BRG U0TB U1BRG U1TB Address 02F916 02FB16, 02FA16 030C16 030D16 032916 032B16, 032A16 033916 033B16, 033A16 034416 034716, 034616 034916, 034816 034B16, 034A16 034D16, 034C16 034F16, 034E16 036116 036316, 036216 036916 036B16, 036A16 Note: In one-shot timer mode and pulse widt modulation mode. External ROM version (144-pin version) The external ROM version is operated only in microprocessor mode, so be sure to perform the following: * Connect CNVss pin to Vcc. Notes on CNVSS pin reset at "H" level When the CNVSS pin is reset at "H" level, the contents of internal ROM cannot be read out. Rev.1.00 Aug. 02, 2005 Page 222 of 329 REJ09B0187-0100 M16C/80 Group 27. Usage Precaution Microprocesser mode or Memory expansion mode When the MCU enters wait mode while operating in memory expansion mode or microprocessor mode, a pin functioning as part of the address or data bus retains it's state on the bus before wait mode is entered. Shift to single-chip mode and output an arbitrary value in order to reduce current consumption. By shifting to single-chip mode, a pin which was functioning as part of the bus becomes a generalpurpose port and can output an arbitrary value. Set the port registers and direction registers after shifting _____ _____ _____ to single-chip mode (this implies that any control pins (CS,WR,RD,etc.. ) being used for access of an external device be changed as well). If the port registers and direction registers are set while in memory expansion mode or microprocessor mode, the operation will be ignored. This is similar when entering stop mode. Setting procedure is following. Operate in memory expansion mode or microprocessor mode Shift to single-chip mode Set the port register Note Set the direction register Enter the wait mode or stop mode Note . This program does not work in external area. Transfer a program to internal RAM and work on internal RAM. Figure 27.3 Setting procedure of the port register and direction register. Microprocessor If the software reset is executed when the CNVss pin is connected to Vcc to start up in microprocessor mode, write at least three NOP instructions following the writing instruction to the PM0 Register. example: mov.b #02H,PRCR bset 3,PM0 ; or "mov.b #8BH,PM0" (instruction to execute software reset) nop ; write at least three NOP instructions nop nop nop Rev.1.00 Aug. 02, 2005 Page 223 REJ09B0187-0100 of 329 M16C/80 Group 27. Usage Precaution Flash memory version Bit 7 and bit 6 of the processor mode register 1 (address 000516) must be set to "112" and this setting should be done when the main clock is divided by 8. Rewrite program of external ROM version with built-in boot loader * Do not use interrupts in rewrite program. * Do not use absolute address jump instructions (JMP.A, JMPI.A) and absolute address subroutine call instructions (JSR.A, JSRI.A) in rewrite program. Rev.1.00 Aug. 02, 2005 Page 224 of 329 REJ09B0187-0100 M16C/80 Group 28. Electrical characteristics 28. Electrical characteristics Table 28.1 Absolute maximum ratings Symbol Parameter Vcc AVcc Supply voltage Analog supply voltage Input voltage VI RESET, (maskROM : CNVSS, BYTE), P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P72-P77, P80-P87, P90-P97, P100-P107, P110-P114, P120-P127, P130-P137, P140-P146, P150-P157, VREF, XIN (Note 1) P70, P71 P00-P07, P10-P17, P20-P27, P30-P37,P40-P47, P50-P57, P60-P67,P72-P77, P80-P84, P86, P87, P90-P97, P100-P107, P110-P114, P120-P127, P130-P137, P140-P146, P150-P157, XOUT (Note 1) P70, P71 Pd Topr Tstg Power dissipation Operating ambient temperature Storage temperature Topr=25 C Condition VCC=AVCC VCC=AVCC Rated value -0.3 to 6.5 -0.3 to 6.5 Unit V V -0.3 to Vcc+0.3 V -0.3 to 6.5 V Output voltage VO -0.3 to Vcc+0.3 V -0.3 to 6.5 500 -20 to 85 / -40 to 85 (Note 2) -65 to 150 V mW C C Note 1: Port P11 to P15 exist in 144-pin version. Note 2: Specify a product of -40 to 85C to use it. Rev.1.00 Aug. 02, 2005 Page 225 REJ09B0187-0100 of 329 M16C/80 Group 28. Electrical characteristics Table 28.2 Recommended operating conditions (referenced to VCC = 2.7V to 5.5V at Topr = - 20 to 85oC / - 40 to 85oC(Note3) unless otherwise specified) Standard Symbol Parameter Unit Typ. Min Max. Vcc AVcc Vss AVss Supply voltage Analog supply voltage Supply voltage Analog supply voltage HIGH input P40-P47, P50-P57, P60-P67, P72-P77, P80-P87, P90-P97, P100-P107, voltage P110-P114, P120-P127,P130-P137, P140-P146, P150-P157 (Note 5), XIN, RESET, CNVSS, BYTE 2.7 5.0 Vcc 0 0 5.5 V V V V 0.8Vcc Vcc V VIH P70 , P71 P00-P07, P10-P17, P20-P27, P30-P37 (during single-chip mode) 0.8Vcc 0.8Vcc 0.5Vcc 6.5 Vcc Vcc V V V P00-P07, P10-P17, P20-P27, P30-P37 (data input function during memory expansion and microprocessor modes) LOW input voltage P40-P47, P50-P57, P60-P67, P70-P77, P80-P87, P90-P97, P100-P107, P110-P114, P120-P127,P130-P137, P140-P146, P150-P157 (Note 5), XIN, RESET, CNVSS, BYTE P00-P07, P10-P17, P20-P27, P30-P37 (during single-chip mode) 0 0.2Vcc V VIL 0 0 0.2Vcc 0.16Vcc V V P00-P07, P10-P17, P20-P27, P30-P37 (data input function during memory expansion and microprocessor modes) HIGH peak output I OH (peak) current I OH (avg) I OL (peak) I OL (avg) P00-P07, P10-P17, P20-P27, P30-P37 P40-P47, P50-P57, P60-P67, P72-P77, P80-P84, P86, P87, P90-P97, P100-P107, P110-P114, P120-P127,P130-P137, P140-P146, P150-P157 (Note 5) HIGH average output P00-P07, P10-P17, P20-P27, P30-P37 current P40-P47, P50-P57, P60-P67, P72-P77, P80-P84, P86, P87, P90-P97, P100-P107, P110-P114, P120-P127,P130-P137, P140-P146, P150-P157 (Note 5) P00-P07, P10-P17, P20-P27, P30-P37 LOW peak output P40-P47, P50-P57, P60-P67, P70-P77, current P80-P84, P86, P87, P90-P97, P100-P107, P110-P114, P120-P127,P130-P137, P140-P146, P150-P157 (Note 5) P00-P07, P10-P17, P20-P27, P30-P37 LOW average P40-P47, P50-P57, P60-P67, P70-P77, output current P80-P84, P86, P87, P90-P97, P100-P107, P110-P114, P120-P127,P130-P137, P140-P146, P150-P157 (Note 5) -10.0 mA -5.0 mA 10.0 mA 5.0 mA Main clock input oscillation frequency f (XIN) No wait Vcc=4.2V to 5.5V Vcc=2.7V to 4.2V 0 0 32.768 20 10 50 MHz MHz kHz f (XcIN) Subclock oscillation frequency Note 1: The mean output current is the mean value within 100ms. Note 2: The total IOL (peak) for ports P0, P1, P2, P86, P87, P9, P10, P11, P14 and P15 must be 80mA max. The total IOH (peak) for ports P0, P1, P2, P86, P87, P9, P10, P11, P14 and P15 must be -80mA max. The total IOL (peak) for ports P3, P4, P5, P6, P7,P80 to P84, P12 and P13 must be 80mA max. The total IOH (peak) for ports P3, P4, P5, P6, P72 to P77, P80 to P84, P12 and P13 must be -80mA max. Note 3: Specify a product of -40 to 85C to use it. Note 4: The specification of VIH and VIL of P87 is not when using as XCIN but when using programmable input port. Note 5: Port P11 to P15 exist in 144-pin version. Rev.1.00 Aug. 02, 2005 Page 226 of 329 REJ09B0187-0100 M16C/80 Group 28. Electrical characteristics Table 28.3 A/D conversion characteristics (referenced to VCC = AVCC = VREF = 5V, Vss = AVSS = 0V at Topr = 25oC, f(XIN)=20MHZ unless otherwise specified) Symbol Resolution Absolute accuracy (10 bits) Parameter Measurement Condition VREF=VCC AN0 to AN7 input VREF=VCC ANEX0, ANEX1 input =5V External op-amp connection mode VREF=VCC=5V Standard Min. Typ. Max. 10 3 7 2 2 10 3.3 2.8 9.8 0.3 VREF=VCC=4.2 to 5.5V VREF=VCC=2.7 to 5.5V 2.0 2.7 0 VREF 40 Bits LSB LSB LSB LSB k s s s s V V V Unit - Absolute accuracy (8 bits) Absolute accuracy (8 bits) RLADDER tCONV tCONV tCONV tSAMP VREF VIA Ladder tesistance Conversion time (10 bits) Conversion time (8 bits) Conversion time (8 bits) Sampling time Reference voltage Analog input voltage Sample & hold function available Sample & hold function available Sample & hold V function not available REF=VCC=3V, AD=fAD/2 VREF=VCC VREF=VCC=5V, AD=10MHz VREF=VCC=5V, AD=10MHz Sample & hold V function not available REF=VCC=3V, AD=fAD/2=5MHz Note 1: DO f(XIN) in range of main clock input oscillation frequency prescribed with recommended operating conditions of table 28.2. Divide the fAD if f(XIN) exceeds 10 MHz, and make AD operation clock frequency (OAD) equal to or lower than 10 MHz. And divide the fAD if VCC is less than 4.2V, and make AD operation clock frequency (OAD) equal to or lower than fAD/2. Note 2 :A case without sample & hold function turn AD operation clock frequency (OAD) into 250 kHz or more in addition to a limit of Note 1. Note 3 :Connect AVCC pin to VCC pin and apply the same electric potential. Table 28.4 D/A conversion characteristics (referenced to VCC = VREF = 5V, Vss = AVSS = 0V at Topr = 25oC, f(XIN)=20MHZ unless otherwise specified) Symbol Parameter Resolution Absolute accuracy Setup time Output resistance Reference power supply input current VREF = VCC = 5V(Note 1) VREF = VCC = 3V(Note 1) Measuring condition Min. Standard Typ. Max. 8 1.0 3 20 1.5 1.0 Unit Bits % s k mA mA tsu RO IVREF 4 10 Note 1: This applies when using one D/A converter, with the D/A register for the unused D/A converter set to "0016". The A/D converter's ladder resistance is not included. Also, when D/A register contents are not "0016" the current IVREF always flows even though Vref may have been set to be unconnected by the A/D control register. Rev.1.00 Aug. 02, 2005 Page 227 REJ09B0187-0100 of 329 M16C/80 Group 28. Electrical characteristics Table 28.5 Electrical characteristics (referenced to VCC=5V, VSS=0V at Topr=25oC, f(XIN)=20MHZ unless otherwise specified) Symbol Parameter Measuring condition Min Standard Typ. Max. VCC = 5V Unit VOH HIGH output P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, voltage P50-P57, P60-P67, P72-P77, P80-P84, P86, P87, IOH= - 5mA, VCC=5.0V P90-P97, P100-P107, P110-P114, P120-P127, P130-P137, P140-P146, P150-P157 (Note 1) HIGH output P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P72-P77, P80-P84, P86, P87, voltage IOH= - 200A, VCC=5.0V P90-P97, P100-P107, P110-P114, P120-P127, P130-P137, P140-P146, P150-P157 (Note 1) HIGH output voltage HIGH output voltage XOUT XCOUT HIGHPOWER LOWPOWER HIGHPOWER LOWPOWER 3.0 V VOH 4.7 3.0 3.0 3.0 1.6 V IOH= - 1mA, VCC=5.0V IOH= - 0.5mA, VCC=5.0V With no load applied, VCC=5.0V With no load applied, VCC=5.0V V V VOH VOL LOW output P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-P77, P80-P84, P86, P87, voltage P90-P97, P100-P107, P110-P114, P120-P127, IOL=5mA, VCC=5.0V P130-P137, P140-P146, P150-P157 (Note 1) LOW output P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-P77, P80-P84, P86, P87, voltage IOL=200A, VCC=5.0V P90-P97, P100-P107, P110-P114, P120-P127, P130-P137, P140-P146, P150-P157 (Note 1) LOW output voltage LOW output voltage XOUT XCOUT HIGHPOWER LOWPOWER HIGHPOWER LOWPOWER 2.0 V VOL 0.45 2.0 2.0 0 0 V VOL IOL=1mA, VCC=5.0V IOL=0.5mA, VCC=5.0V With no load applied, VCC=5.0V With no load applied, VCC=5.0V VCC=5.0V V V VT+-VT- Hysteresis HOLD, RDY, TA0IN-TA4IN, TB0IN-TB5IN, INT0-INT5, ADTRG, CTS0-CTS4, CLK0-CLK4, TA0OUT-TA4OUT,NMI, KI0-KI3,RxD0-RxD4, SCL2-SCL4, SDA2-SDA4 RESET 0.2 1.0 V VT+-VT- Hysteresis VCC=5.0V 0.2 1.8 V IIH I IL RPULLUP RfXIN R fXCIN V RAM HIGH input P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87, current VI=5V, VCC=5.0V P90-P97,P100-P107, P110-P114, P120-P127,P130-P137, P140-P146, P150-P157, (Note 1) XIN, RESET, CNVss, BYTE LOW input P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87, current P90-P97,P100-P107, P110-P114, VI=0V, VCC=5.0V P120-P127,P130-P137, P140-P146, P150-P157, (Note 1) XIN, RESET, CNVss, BYTE Pull-up P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, resistance P50-P57, P60-P67, P72-P77, P80-P84, P86, P87, VI=0V, VCC=5.0V P90-P97,P100-P107, P110-P114, P120-P127, P130-P137, P140-P146, P150-P157 (Note 1) Feedback resistance XIN Feedback resistance XCIN RAM retention voltage f(XIN)=20MHz When clock is stopped 5.0 A - 5.0 A 30.0 50.0 1.0 6.0 167.0 k M M V 2.0 45.0 50.0 50.0 90.0 100.0 7.0 4.0 1.0 2.0 1.0 20.0 72.0 80.0 80.0 Icc Measuring condition: Square wave, no division Mask ROM 128 KB version ROMless RAM 10 KB version(Note 2) In single-chip Mask ROM 256 KB version mode, the output ROMless RAM 24 KB version (Note 2) pins are open and Flash memory version Power supply other pins are VSS current Mask ROM 128 KB version f(XCIN)=32kHz ROMless RAM 10 KB version(Note 2) Square wave mA A Mask ROM 256 KB version ROMless RAM 24 KB version (Note 2) Flash memory version Mask ROM 128 KB version ROMless RAM 10KB version (Note 2) Mask ROM 256 KB version ROMless RAM 24KB version (Note 2) Flash memory version mA A A f(XCIN)=32kHz When a WAIT instruction is executed Topr=25C when clock is stopped Topr=85C when clock is stopped Note 1: Port P11 to P15 exist in 144-pin version. Note 2: ROMless version exists in 144-pin version. Rev.1.00 Aug. 02, 2005 Page 228 of 329 REJ09B0187-0100 M16C/80 Group 28. Electrical characteristics VCC = 5V Timing requirements (referenced to VCC = 5V, VSS = 0V at Topr = 25oC unless otherwise specified) Table 28.6 External clock input Symbol tc tw(H) tw(L) tr tf Parameter External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock rise time External clock fall time Standard Min. Max. 50 22 22 5 5 Unit ns ns ns ns ns Table 28.7 Memory expansion and microprocessor modes Symbol tac1(RD-DB) tac1(AD-DB) tac2(RD-DB) tac2(AD-DB) tac3(RD-DB) tac3(AD-DB) tac4(RAS-DB) tac4(CAS-DB) tac4(CAD-DB) tsu(DB-BCLK) tsu(RDY-BCLK ) tsu(HOLD-BCLK ) th(RD-DB) th(CAS -DB) th(BCLK -RDY) th(BCLK-HOLD ) td(BCLK-HLDA ) Parameter Data input access time (RD standard, no wait) Data input access time (AD standard, CS standard, no wait) Data input access time (RD standard, with wait) Data input access time (AD standard, CS standard, with wait) Data input access time (RD standard, when accessing multiplex bus area) Data input access time (AD standard, CS standard, when accessing multiplex bus area) Standard Unit Min. Max. (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) 26 26 30 0 0 0 0 25 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Data input access time (RAS standard, DRAM access) Data input access time (CAS standard, DRAM access) Data input access time (CAD standard, DRAM access) Data input setup time RDY input setup time HOLD input setup time Data input hold time Data input hold time RDY input hold time HOLD input hold time HLDA output delay time Note: Calculated according to the BCLK frequency as follows: Note that inserting wait or using lower operation frequency f(BCLK) is needed when calculated value is negative. tac1(RD - DB) = tac1(AD - DB) = 10 9 - 35 f(BCLK) X 2 10 9 f(BCLK) 9 [ns] [ns] - 35 tac2(RD - DB) = tac2(AD - DB) = tac3(RD - DB) = tac3(AD - DB) = tac4(RAS - DB) = tac4(CAS - DB) = tac4(CAD - DB) = 10 X m - 35 f(BCLK) X 2 10 X n f(BCLK) 9 9 [ns] (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively) [ns] (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively) [ns] (m=3 and 5 when 2 wait and 3 wait, respectively) [ns] (n=5 and 7 when 2 wait and 3 wait, respectively) [ns] (m=3 and 5 when 1 wait and 2 wait, respectively) [ns] (n=1 and 3 when 1 wait and 2 wait, respectively) [ns] (l=1 and 2 when 1 wait and 2 wait, respectively) - 35 10 X m - 35 f(BCLK) X 2 10 X n - 35 f(BCLK) X 2 10 X m f(BCLK) X 2 10 X n f(BCLK) X 2 10 X l f(BCLK) 9 9 9 9 - 35 - 35 - 35 Rev.1.00 Aug. 02, 2005 Page 229 REJ09B0187-0100 of 329 M16C/80 Group 28. Electrical characteristics VCC = 5V Timing requirements (referenced to VCC = 5V, VSS = 0V at Topr = 25oC unless otherwise specified) Table 28.8 Timer A input (counter input in event counter mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. Max. 100 40 40 Unit ns ns ns Table 28.9 Timer A input (gating input in timer mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. Max. 400 200 200 Unit ns ns ns Table 28.10 Timer A input (external trigger input in one-shot timer mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Max. Min. 200 100 100 Unit ns ns ns Table 28.11 Timer A input (external trigger input in pulse width modulation mode) Symbol tw(TAH) tw(TAL) Parameter TAiIN input HIGH pulse width TAiIN input LOW pulse width Standard Min. Max. 100 100 Unit ns ns Table 28.12 Timer A input (up/down input in event counter mode) Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) Parameter TAiOUT input cycle time TAiOUT input HIGH pulse width TAiOUT input LOW pulse width TAiOUT input setup time TAiOUT input hold time Standard Min. Max. 2000 1000 1000 400 400 Unit ns ns ns ns ns Rev.1.00 Aug. 02, 2005 Page 230 of 329 REJ09B0187-0100 M16C/80 Group 28. Electrical characteristics VCC = 5V Timing requirements (referenced to VCC = 5V, VSS = 0V at Topr = 25oC unless otherwise specified) Table 28.13 Timer B input (counter input in event counter mode) Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Parameter TBiIN input cycle time (counted on one edge) TBiIN input HIGH pulse width (counted on one edge) TBiIN input LOW pulse width (counted on one edge) TBiIN input cycle time (counted on both edges) TBiIN input HIGH pulse width (counted on both edges) TBiIN input LOW pulse width (counted on both edges) Standard Min. Max. 100 40 40 200 80 80 Unit ns ns ns ns ns ns Table 28.14 Timer B input (pulse period measurement mode) Symbol tc(TB) tw(TBH) tw(TBL) Parameter TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width Standard Min. Max. 400 200 200 Unit ns ns ns Table 28.15 Timer B input (pulse width measurement mode) Symbol tc(TB) tw(TBH) tw(TBL) Parameter TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width Standard Max. Min. 400 200 200 Unit ns ns ns Table 28.16 A/D trigger input Symbol tc(AD) tw(ADL) Parameter ADTRG input cycle time (trigger able minimum) ADTRG input LOW pulse width Standard Max. Min. 1000 125 Unit ns ns Table 28.17 Serial I/O Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) Parameter CLKi input cycle time CLKi input HIGH pulse width CLKi input LOW pulse width TxDi output delay time TxDi hold time RxDi input setup time RxDi input hold time _______ Standard Min. Max. 200 100 100 80 0 30 90 Unit ns ns ns ns ns ns ns Table 28.18 External interrupt INTi inputs Symbol tw(INH) tw(INL) INTi input HIGH pulse width INTi input LOW pulse width Parameter Standard Min. 250 250 Max. Unit ns ns Rev.1.00 Aug. 02, 2005 Page 231 REJ09B0187-0100 of 329 M16C/80 Group 28. Electrical characteristics VCC = 5V Switching characteristics (referenced to VCC = 5V, VSS = 0V at Topr = 25oC unless otherwise specified) Table 28.19 Memory expansion mode and microprocessor mode (no wait) Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(DB-WR) th(WR-DB) tw(WR) Parameter Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard) Address output hold time (WR standard) Chip select output delay time Chip select output hold time (BCLK standard) Chip select output hold time (RD standard) Chip select output hold time (WR standard) ALE signal output delay time ALE signal output hold time RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (WR standard) Data output hold time (WR standard) WR signal width Measuring condition Figure 28.1 Standard Min. Max. 18 -3 0 (Note 1) 18 -3 0 (Note 1) 18 -2 10 -5 18 -3 (Note 1) (Note 1) (Note 1) Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 1: Calculated according to the BCLK frequency as follows: td(DB - WR) = th(WR - DB) = th(WR - AD) = th(WR - CS) = tw(WR) = 10 9 f(BCLK) 9 - 20 [ns] [ns] [ns] [ns] [ns] 10 f(BCLK) X 2 10 9 f(BCLK) X 2 10 f(BCLK) X 2 10 f(BCLK) X 2 9 9 - 10 - 10 - 10 - 15 Rev.1.00 Aug. 02, 2005 Page 232 of 329 REJ09B0187-0100 M16C/80 Group 28. Electrical characteristics VCC = 5V Switching characteristics (referenced to VCC = 5V, VSS = 0V at Topr = 25oC unless otherwise specified) Table 28.20 Memory expansion mode and microprocessor mode (with wait, accessing external memory) Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(DB-WR) th(WR-DB) tw(WR) Parameter Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard) Address output hold time (WR standard) Chip select output delay time Chip select output hold time (BCLK standard) Chip select output hold time (RD standard) Chip select output hold time (WR standard) ALE signal output delay time ALE signal output hold time RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (WR standard) Data output hold time (WR standard) WR signal width Measuring condition Figure 28.1 Standard Min. Max. 18 -3 0 (Note 1) 18 -3 0 (Note 1) 18 -2 10 -5 18 -3 (Note 1) (Note 1) (Note 1) Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 1: Calculated according to the BCLK frequency as follows: td(DB - WR) = th(WR - DB) = th(WR - AD) = th(WR - CS) = 10 9 X n - 20 f(BCLK) [ns] (n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively) [ns] [ns] [ns] 10 9 - 10 f(BCLK) X 2 10 9 - 10 f(BCLK) X 2 10 9 - 10 f(BCLK) X 2 tw( WR) = 10 9 X n - 15 f(BCLK) X 2 [ns] (n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively) Rev.1.00 Aug. 02, 2005 Page 233 REJ09B0187-0100 of 329 M16C/80 Group 28. Electrical characteristics VCC = 5V Switching characteristics (referenced to VCC = 5V, VSS = 0V at Topr = 25oC unless otherwise specified) Table 28.21 Memory expansion mode and microprocessor mode (with wait, accessing external memory, multiplex bus area selected) Standard Measuring condition Symbol Parameter Min. Max. td(BCLK-AD) Address output delay time 18 -3 th(BCLK-AD) Address output hold time (BCLK standard) (Note 1) Address output hold time (RD standard) th(RD-AD) th(WR-AD) (Note 1) Address output hold time (WR standard) Chip select output delay time td(BCLK-CS) 18 th(BCLK-CS) Chip select output hold time (BCLK standard) -3 (Note 1) Chip select output hold time (RD standard) th(RD-CS) Chip select output hold time (WR standard) (Note 1) th(WR-CS) td(BCLK-RD) RD signal output delay time 18 Figure 28.1 -5 th(BCLK-RD) RD signal output hold time 18 td(BCLK-WR) WR signal output delay time -3 th(BCLK-WR) WR signal output hold time (Note 1) td(DB-WR) Data output delay time (WR standard) th(WR-DB) Data output hold time (WR standard) (Note 1) 18 td(BCLK-ALE) ALE signal output delay time (BCLK standard) th(BCLK-ALE) ALE signal output hold time (BCLK standard) -2 td(AD-ALE) ALE signal output delay time (address standard) (Note 1) th(ALE-AD) ALE signal output hold time (address standard) (Note 1) tdz(RD-AD) Address output flowting start time 8 th(BCLK-DB) Data output hold time (BCLK standard) -5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 1: Calculated according to the BCLK frequency as follows: th(RD - AD) = th(WR - AD) = th(RD - CS) = th(WR - CS) = 10 9 f(BCLK) X 2 10 f(BCLK) X 2 10 f(BCLK) X 2 10 9 f(BCLK) X 2 9 9 9 - 10 - 10 - 10 - 10 [ns] [ns] [ns] [ns] td(DB - WR) = 10 X m - 25 f(BCLK) X 2 10 9 f(BCLK) X 2 10 9 f(BCLK) X 2 10 9 f(BCLK) X 2 - 10 [ns] (m=3 and 5 when 2 wait and 3 wait, respectively) [ns] th(WR - DB) = td(AD - ALE) = - 23 [ns] th(ALE - AD) = - 10 [ns] Rev.1.00 Aug. 02, 2005 Page 234 of 329 REJ09B0187-0100 M16C/80 Group 28. Electrical characteristics VCC = 5V Switching characteristics (referenced to VCC = 5V, VSS = 0V at Topr = 25oC unless otherwise specified) Table 28.22 Memory expansion mode and microprocessor mode (with wait, accessing external memory, DRAM area selected) Symbol td(BCLK-RAD) th(BCLK-RAD) td(BCLK-CAD) th(BCLK-CAD) th(RAS-RAD) td(BCLK-RAS) th(BCLK-RAS) tRP Parameter Row address output delay time Row address output hold time (BCLK standard) String address output delay time String address output hold time (BCLK standard) Row address output hold time after RAS output RAS output delay time (BCLK standard) RAS output hold time (BCLK standard) RAS "H" hold time Measuring condition Figure 28.1 Standard Min. Max. 18 -3 18 -3 (Note 1) 18 -3 (Note 1) 18 -3 18 -5 (Note 1) -7 (Note 1) Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns td(BCLK-CAS) CAS output delay time (BCLK standard) th(BCLK-CAS) CAS output hold time (BCLK standard) td(BCLK-DW) Data output delay time (BCLK standard) th(BCLK-DW) Data output hold time (BCLK standard) CAS after DB output setup time tsu(DB-CAS) th(BCLK-DB) DB signal output hold time (BCLK standard) tsu(CAS-RAS) CAS before RAS setup time (refresh) Note 1: Calculated according to the BCLK frequency as follows: th(RAS - RAD) = 10 9 f(BCLK) X 2 10 9 X 3 f(BCLK) X 2 10 f(BCLK) 9 9 - 13 [ns] tRP = tsu(DB - CAS) = - 20 [ns] - 20 [ns] tsu(CAS - RAS) = 10 f(BCLK) X 2 - 13 [ns] Rev.1.00 Aug. 02, 2005 Page 235 REJ09B0187-0100 of 329 M16C/80 Group 28. Electrical characteristics P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 30pF (Note) Note: Port P11 to P15 exist in 144-pin version. Figure 28.1 Port P0 to P15 measurement circuit Rev.1.00 Aug. 02, 2005 Page 236 of 329 REJ09B0187-0100 M16C/80 Group 28. Electrical characteristics Vcc=5V Memory expansion Mode and Microprocessor Mode (without wait) Read Timing BCLK td(BCLK-ALE) 18ns.max th(BCLK-ALE) -2ns.min ALE td(BCLK-CS) 18ns.max *1 th(BCLK-CS) -3ns.min CSi tcyc th(RD-CS) 0ns.min td(BCLK-AD) ADi BHE 18ns.max*1 th(BCLK-AD) -3ns.min td(BCLK-RD) 10ns.max th(RD-AD) 0ns.min RD tac1(RD-DB)*2 tac1(AD-DB)*2 DB Hi-Z th(BCLK-RD) -5ns.min tsu(DB-BCLK) 26ns.min*1 th(RD-DB) 0ns.min *1:It is a guarantee value with being alone. 35ns.max garantees as td(BCLK-AD)+tsu(DB-BCLK). *2:It depends on operation frequency. tac1(RD-DB)=(tcyc/2-35)ns.max tac1(AD-DB)=(tcyc-35)ns.max Write Timing ( Written by 2 cycles in selecting no wait) BCLK 18ns.max td(BCLK-ALE) ALE th(BCLK-ALE) -2ns.min td(BCLK-CS) 18ns.max th(BCLK-CS) -3ns.min CSi tcyc th(WR-CS)*3 th(BCLK-AD) -3ns.min td(BCLK-AD) ADi BHE 18ns.max td(BCLK-WR) 18ns.max tw(WR)*3 th(WR-AD)*3 th(BCLK-WR) -3ns.min WR,WRL, WRH td(DB-WR)*3 DBi *3:It depends on operation frequency. td(DB-WR)=(tcyc-20)ns.min th(WR-DB)=(tcyc/2-10)ns.min th(WR-AD)=(tcyc/2-10)ns.min th(WR-CS)=(tcyc/2-10)ns.min tw(WR)=(tcyc/2-15)ns.min th(WR-DB)*3 Measuring conditions * VCC=5V10% * Input timing voltage :Determined with VIH=2.5V, VIL=0.8V * Output timing voltage :Determined with VOH=2.0V, VOL=0.8V Figure 28.2 VCC=5V timing diagram (1) Rev.1.00 Aug. 02, 2005 Page 237 REJ09B0187-0100 of 329 M16C/80 Group 28. Electrical characteristics Vcc=5V Memory expansion Mode and Microprocessor Mode (with 1 wait) Read Timing BCLK 18ns.max td(BCLK-ALE) th(BCLK-ALE) -2ns.min ALE td(BCLK-CS) 18ns.max*1 th(BCLK-CS) -3ns.min CSi tcyc th(RD-CS) 0ns.min td(BCLK-AD) 18ns.max*1 th(BCLK-AD) -3ns.min ADi BHE td(BCLK-RD) 10ns.max th(RD-AD) 0ns.min RD tac2(RD-DB)*2 tac2(AD-DB)*2 DB Hi-Z th(BCLK-RD) -5ns.min tsu(DB-BCLK) 26ns.min*1 th(RD-DB) 0ns.min *1:It is a guarantee value with being alone. 35ns.max garantees as td(BCLK-AD)+tsu(DB-BCLK). *2:It depends on operation frequency. tac2(RD-DB)=(tcyc/2 x m-35)ns.max (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively.) tac2(AD-DB)=(tcyc x n-35)ns.max (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively.) Write Timing BCLK 18ns.max td(BCLK-ALE) ALE th(BCLK-ALE) -2ns.min td(BCLK-CS) 18ns.max th(BCLK-CS) -3ns.min CSi tcyc th(WR-CS)*3 th(BCLK-AD) -3ns.min td(BCLK-AD) ADi BHE 18ns.max td(BCLK-WR) WR,WRL, WRH 18ns.max tw(WR)*3 th(WR-AD)*3 th(BCLK-WR) -3ns.min td(DB-WR)*3 DBi th(WR-DB)*3 *3:It depends on operation frequency. Measuring conditions td(DB-WR)=(tcyc x n-20)ns.min * VCC=5V10% (n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively.) * Input timing voltage th(WR-DB)=(tcyc/2-10)ns.min :Determined with VIH=2.5V, VIL=0.8V th(WR-AD)=(tcyc/2-10)ns.min * Output timing voltage th(WR-CS)=(tcyc/2-10)ns.min :Determined with VOH=2.0V, VOL=0.8V tw(WR)=(tcyc/2 x n-15)ns.min (n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively.) Figure 28.3 VCC=5V timing diagram (2) Rev.1.00 Aug. 02, 2005 Page 238 of 329 REJ09B0187-0100 M16C/80 Group 28. Electrical characteristics Memory expansion Mode and Microprocessor Mode (with 2 wait) Read Timing BCLK 18ns.max Vcc=5V td(BCLK-ALE) ALE th(BCLK-ALE) -2ns.min td(BCLK-CS) 18ns.max*1 th(BCLK-CS) -3ns.min CSi tcyc th(RD-CS) 0ns.min td(BCLK-AD) 18ns.max*1 th(BCLK-AD) -3ns.min ADi BHE td(BCLK-RD) 10ns.max th(RD-AD) 0ns.min RD tac2(RD-DB)*2 tac2(AD-DB)*2 DB Hi-Z th(BCLK-RD) -5ns.min tsu(DB-BCLK) 26ns.min*1 th(RD-DB) 0ns.min *1:It is a guarantee value with being alone. 35ns.max garantees as td(BCLK-AD)+tsu(DB-BCLK). *2:It depends on operation frequency. tac2(RD-DB)=(tcyc/2 x m-35)ns.max (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively.) tac2(AD-DB)=(tcyc x n-35)ns.max (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively.) Write Timing BCLK 18ns.max td(BCLK-ALE) ALE th(BCLK-ALE) -2ns.min td(BCLK-CS) 18ns.max th(BCLK-CS) -3ns.min CSi tcyc th(WR-CS)*3 th(BCLK-AD) -3ns.min td(BCLK-AD) ADi BHE 18ns.max td(BCLK-WR) WR,WRL, WRH 18ns.max tw(WR)*3 th(WR-AD)*3 th(BCLK-WR) -3ns.min td(DB-WR)*3 DBi th(WR-DB)*3 *3:It depends on operation frequency. Measuring conditions td(DB-WR)=(tcyc x n-20)ns.min * VCC=5V10% (n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively.) * Input timing voltage th(WR-DB)=(tcyc/2-10)ns.min :Determined with VIH=2.5V, VIL=0.8V th(WR-AD)=(tcyc/2-10)ns.min * Output timing voltage th(WR-CS)=(tcyc/2-10)ns.min :Determined with VOH=2.0V, VOL=0.8V tw(WR)=(tcyc/2 x n-15)ns.min (n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively.) Figure 28.4 VCC=5V timing diagram (3) Rev.1.00 Aug. 02, 2005 Page 239 REJ09B0187-0100 of 329 M16C/80 Group 28. Electrical characteristics Memory expansion Mode and Microprocessor Mode (with 3 wait) Read Timing BCLK 18ns.max Vcc=5V td(BCLK-ALE) ALE th(BCLK-ALE) -2ns.min td(BCLK-CS) 18ns.max *1 th(BCLK-CS) -3ns.min CSi tcyc th(RD-CS) 0ns.min td(BCLK-AD) ADi BHE 18ns.max *1 th(BCLK-AD) -3ns.min td(BCLK-RD) 10ns.max th(RD-AD) 0ns.min RD tac2(RD-DB)*2 tac2(AD-DB)*2 DB Hi-Z th(BCLK-RD) -5ns.min tsu(DB-BCLK) 26ns.min*1 th(RD-DB) 0ns.min *1:It is a guarantee value with being alone. 35ns.max garantees as td(BCLK-AD)+tsu(DB-BCLK). *2:It depends on operation frequency. tac2(RD-DB)=(tcyc/2 x m-35)ns.max (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively.) tac2(AD-DB)=(tcyc x n-35)ns.max (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively.) Write Timing BCLK 18ns.max td(BCLK-ALE) ALE th(BCLK-ALE) -2ns.min td(BCLK-CS) 18ns.max th(BCLK-CS) -3ns.min CSi tcyc th(WR-CS)*3 th(BCLK-AD) -3ns.min td(BCLK-AD) ADi BHE 18ns.max td(BCLK-WR) WR,WRL, WRH 18ns.max tw(WR)*3 th(WR-AD)*3 th(BCLK-WR) td(DB-WR)*3 DBi th(WR-DB)*3 -3ns.min *3:It depends on operation frequency. td(DB-WR)=(tcyc x n-20)ns.min (n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively.) th(WR-DB)=(tcyc/2-10)ns.min th(WR-AD)=(tcyc/2-10)ns.min th(WR-CS)=(tcyc/2-10)ns.min tw(WR)=(tcyc/2 x n-15)ns.min (n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively.) Measuring conditions * VCC=5V10% * Input timing voltage :Determined with VIH=2.5V, VIL=0.8V * Output timing voltage :Determined with VOH=2.0V, VOL=0.8V Figure 28.5 VCC=5V timing diagram (4) Rev.1.00 Aug. 02, 2005 Page 240 of 329 REJ09B0187-0100 M16C/80 Group 28. Electrical characteristics Memory expansion Mode and Microprocessor Mode (When accessing external memory area with 2 wait, and select multiplexed bus)) Vcc=5V Read Timing BCLK 18ns.max td(BCLK-ALE) ALE th(BCLK-ALE) -2ns.min tcyc td(BCLK-CS) 18ns.max th(BCLK-CS) -3ns.min CSi th(RD-CS) td(AD-ALE)*1 th(ALE-AD)*1 *1 ADi /DBi Address tdz(RD-AD) 8ns.max Data input Address th(RD-DB) tsu(DB-BCLK) *1 26ns.min 0ns.min td(BCLK-AD) ADi BHE 18ns.max th(BCLK-AD) -3ns.min tac3(RD-DB) tac3(AD-DB)*1 RD td(BCLK-RD) 18ns.max th(BCLK-RD) -5ns.min th(RD-AD)*1 *1:It depends on operation frequency. td(AD-ALE)=(tcyc/2-23)ns.min th(ALE-AD)=(tcyc/2-10)ns.min, th(RD-AD)=(tcyc/2-10)ns.min, th(RD-CS)=(tcyc/2-10)ns.min tac3(RD-DB)=(tcyc/2 x m-35)ns.max (m=3 and 5 when 2 wait and 3 wait, respectively.) tac3(AD-DB)=(tcyc/2 x n-35)ns.max (n=5 and 7 when 2 wait and 3 wait, respectively.) Write Timing BCLK 18ns.max td(BCLK-ALE) ALE th(BCLK-ALE) -2ns.min td(BCLK-CS) CSi 18ns.max tcyc th(BCLK-CS) th(WR-CS)*2 -3ns.min td(AD-ALE)*2 th(ALE-AD)*2 ADi /DBi Address Data output th(BCLK-DB) -5ns.min Address td(BCLK-AD) ADi BHE 18ns.max td(DB-WR)*2 th(WR-DB)*2 th(BCLK-AD) -3ns.min td(BCLK-WR) WR,WRL, WRH 18ns.max th(BCLK-WR) -3ns.min th(WR-AD)*2 *2:It depends on operation frequency. td(AD-ALE)=(tcyc/2-23)ns.min th(ALE-AD)=(tcyc/2-10)ns.min, th(WR-AD)=(tcyc/2-10)ns.min th(WR-CS)=(tcyc/2-10)ns.min, th(WR-DB)=(tcyc/2-10)ns.min td(DB-WR)=(tcyc/2 x m-25)ns.min (m=3 and 5 when 2 wait and 3 wait, respectively.) Measuring conditions * VCC=5V10% * Input timing voltage :Determined with VIH=2.5V, VIL=0.8V * Output timing voltage :Determined with VOH=2.0V, VOL=0.8V Figure 28.6 VCC=5V timing diagram (5) Rev.1.00 Aug. 02, 2005 Page 241 REJ09B0187-0100 of 329 M16C/80 Group 28. Electrical characteristics Memory expansion Mode and Microprocessor Mode (When accessing external memory area with 3 wait, and select multiplexed bus)) Vcc=5V Read Timing BCLK 18ns.max td(BCLK-ALE) ALE th(BCLK-ALE) -2ns.min td(BCLK-CS) 18ns.max tcyc th(BCLK-CS) -3ns.min CSi th(RD-CS)*1 td(AD-ALE)*1 th(ALE-AD)*1 ADi /DBi Address tdz(RD-AD) 8ns.max Data input Address th(RD-DB) tsu(DB-BCLK) tac3(RD-DB)*1 26ns.min 0ns.min td(BCLK-AD) ADi BHE 18ns.max th(BCLK-AD) -3ns.min tac3(AD-DB)*1 RD td(BCLK-RD) 18ns.max th(BCLK-RD) -5ns.min th(RD-AD)*1 *1:It depends on operation frequency. td(AD-ALE)=(tcyc/2-23)ns.min th(ALE-AD)=(tcyc/2-10)ns.min, th(RD-AD)=(tcyc/2-10)ns.min, th(RD-CS)=(tcyc/2-10)ns.min tac3(RD-DB)=(tcyc/2 x m-35)ns.max (m=3 and 5 when 2 wait and 3 wait, respectively.) tac3(AD-DB)=(tcyc/2 x n-35)ns.max (n=5 and 7 when 2 wait and 3 wait, respectively.) Write Timing BCLK 18ns.max td(BCLK-ALE) ALE th(BCLK-ALE) -2ns.min td(BCLK-CS) CSi 18ns.max tcyc th(BCLK-CS) th(WR-CS)*2 -3ns.min td(AD-ALE)*2 th(ALE-AD)*2 ADi /DBi Address Data output th(BCLK-DB) -5ns.min Address td(BCLK-AD) ADi BHE 18ns.max td(DB-WR)*2 th(WR-DB)*2 th(BCLK-AD) -3ns.min td(BCLK-WR) WR,WRL, WRH 18ns.max th(BCLK-WR) -3ns.min th(WR-AD)*2 *2:It depends on operation frequency. td(AD-ALE)=(tcyc/2-23)ns.min th(ALE-AD)=(tcyc/2-10)ns.min, th(WR-AD)=(tcyc/2-10)ns.min th(WR-CS)=(tcyc/2-10)ns.min, th(WR-DB)=(tcyc/2-10)ns.min td(DB-WR)=(tcyc/2 x m-25)ns.min (m=3 and 5 when 2 wait and 3 wait, respectively.) Measuring conditions * VCC=5V10% * Input timing voltage :Determined with VIH=2.5V, VIL=0.8V * Output timing voltage :Determined with VOH=2.0V, VOL=0.8V Figure 28.7 VCC=5V timing diagram (6) Rev.1.00 Aug. 02, 2005 Page 242 of 329 REJ09B0187-0100 M16C/80 Group 28. Electrical characteristics Vcc=5V Memory expansion Mode and Microprocessor Mode (When accessing DRAM area with 1 wait) Read Timing BCLK tcyc td(BCLK-RAD) th(BCLK-RAD) 18ns.max -3ns.min td(BCLK-CAD) 18ns.max*1 th(BCLK-CAD) -3ns.min MAi Row address String address th(RAS-RAD)*2 RAS tRP*2 th(BCLK-RAS) -3ns.min td(BCLK-RAS) td(BCLK-CAS) 18ns.max*1 CASL CASH 18ns.max*1 th(BCLK-CAS) -3ns.min DW tac4(CAS-DB)*2 tac4(CAD-DB)*2 tac4(RAS-DB)*2 Hi-Z DB tsu(DB-BCLK) 26ns.min*1 th(CAS-DB) 0ns.min *1:It is a guarantee value with being alone. 35ns.max garantees as follows: td(BCLK-RAS) + tsu(DB-BCLK) td(BCLK-CAS) + tsu(DB-BCLK) td(BCLK-CAD) + tsu(DB-BCLK) *2:It depends on operation frequency. tac4(RAS-DB)=(tcyc/2 x m-35)ns.max (m=3 and 5 when 1 wait and 2 wait, respectively.) tac4(CAS-DB)=(tcyc/2 x n-35)ns.max (n=1 and 3 when 1 wait and 2 wait, respectively.) tac4(CAD-DB)=(tcyc x l-35)ns.max (l=1 and 2 when 1 wait and 2 wait, respectively.) th(RAS-RAD)=(tcyc/2-13)ns.min tRP=(tcyc/2 x 3-20)ns.min Measuring conditions * VCC=5V10% * Input timing voltage :Determined with VIH=2.5V, VIL=0.8V * Output timing voltage :Determined with VOH=2.0V, VOL=0.8V Figure 28.8 VCC=5V timing diagram (7) Rev.1.00 Aug. 02, 2005 Page 243 REJ09B0187-0100 of 329 M16C/80 Group 28. Electrical characteristics Vcc=5V Memory expansion Mode and Microprocessor Mode (When accessing DRAM area with 1 wait) Write Timing BCLK tcyc td(BCLK-RAD) 18ns.max th(BCLK-RAD) -3ns.min td(BCLK-CAD) 18ns.max th(BCLK-CAD) -3ns.min MAi Row address String address th(RAS-RAD)*1 RAS tRP*1 td(BCLK-RAS) td(BCLK-CAS) 18ns.max 18ns.max th(BCLK-RAS) -3ns.min CASL CASH td(BCLK-DW) 18ns.max th(BCLK-CAS) -3ns.min DW th(BCLK-DW) tsu(DB-CAS)*1 DB Hi-Z -5ns.min th(BCLK-DB) -7ns.min *1:It depends on operation frequency. th(RAS-RAD)=(tcyc/2-13)ns.min tRP=(tcyc/2 x 3-20)ns.min tsu(DB-CAS)=(tcyc-20)ns.min Measuring conditions * VCC=5V10% * Input timing voltage :Determined with VIH=2.5V, VIL=0.8V * Output timing voltage :Determined with VOH=2.0V, VOL=0.8V Figure 28.9 VCC=5V timing diagram (8) Rev.1.00 Aug. 02, 2005 Page 244 of 329 REJ09B0187-0100 M16C/80 Group 28. Electrical characteristics Memory expansion Mode and Microprocessor Mode (When accessing DRAM area with 2 wait) Vcc=5V Read Timing BCLK tcyc td(BCLK-RAD) th(BCLK-RAD) 18ns.max -3ns.min td(BCLK-CAD) 18ns.max*1 th(BCLK-CAD) -3ns.min MAi Row address String address th(RAS-RAD)*2 RAS tRP*2 th(BCLK-RAS) -3ns.min td(BCLK-RAS) 18ns.max*1 td(BCLK-CAS) 18ns.max*1 CASL CASH th(BCLK-CAS) -3ns.min DW tac4(CAS-DB)*2 tac4(CAD-DB)*2 tac4(RAS-DB)*2 Hi-Z DB tsu(DB-BCLK) 26ns.min*1 th(CAS-DB) 0ns.min *1:It is a guarantee value with being alone. 35ns.max garantees as follows: td(BCLK-RAS) + tsu(DB-BCLK) td(BCLK-CAS) + tsu(DB-BCLK) td(BCLK-CAD) + tsu(DB-BCLK) *2:It depends on operation frequency. tac4(RAS-DB)=(tcyc/2 x m-35)ns.max (m=3 and 5 when 1 wait and 2 wait, respectively.) tac4(CAS-DB)=(tcyc/2 x n-35)ns.max (n=1 and 3 when 1 wait and 2 wait, respectively.) tac4(CAD-DB)=(tcyc x l-35)ns.max (l=1 and 2 when 1 wait and 2 wait, respectively.) th(RAS-RAD)=(tcyc/2-13)ns.min tRP=(tcyc/2 x 3-20)ns.min Measuring conditions * VCC=5V10% * Input timing voltage :Determined with VIH=2.5V, VIL=0.8V * Output timing voltage :Determined with VOH=2.0V, VOL=0.8V Figure 28.10 VCC=5V timing diagram (9) Rev.1.00 Aug. 02, 2005 Page 245 REJ09B0187-0100 of 329 M16C/80 Group 28. Electrical characteristics Memory expansion Mode and Microprocessor Mode (When accessing DRAM area with 2 wait) Vcc=5V Write Timing BCLK tcyc td(BCLK-RAD) 18ns.max th(BCLK-RAD) -3ns.min td(BCLK-CAD) 18ns.max th(BCLK-CAD) -3ns.min MAi Row address String address th(RAS-RAD)*1 RAS tRP*1 th(BCLK-RAS) -3ns.min td(BCLK-RAS) td(BCLK-CAS) 18ns.max 18ns.max CASL CASH td(BCLK-DW) 18ns.max th(BCLK-CAS) -3ns.min DW th(BCLK-DW) tsu(DB-CAS)*1 DB Hi-Z -5ns.min th(BCLK-DB) -7ns.min *1:It depends on operation frequency. th(RAS-RAD)=(tcyc/2-13)ns.min tRP=(tcyc/2 x 3-20)ns.min tsu(DB-CAS)=(tcyc-20)ns.min Measuring conditions * VCC=5V10% * Input timing voltage :Determined with VIH=2.5V, VIL=0.8V * Output timing voltage :Determined with VOH=2.0V, VOL=0.8V Figure 28.11 VCC=5V timing diagram (10) Rev.1.00 Aug. 02, 2005 Page 246 of 329 REJ09B0187-0100 M16C/80 Group 28. Electrical characteristics Memory expansion Mode and Microprocessor Mode Refresh Timing (CAS before RAS refresh) BCLK Vcc=5V td(BCLK-RAS) 18ns.max tcyc RAS tsu(CAS-RAS)*1 CASL CASH th(BCLK-RAS) -3ns.min td(BCLK-CAS) 18ns.max th(BCLK-CAS) -3ns.min DW *1:It depends on operation frequency. tsu(CAS-RAS)=(tcyc/2-13)ns.min Refresh Timing (Self-refresh) BCLK td(BCLK-RAS) 18ns.max tcyc RAS tsu(CAS-RAS)*1 CASL CASH th(BCLK-RAS) -3ns.min td(BCLK-CAS) 18ns.max th(BCLK-CAS) -3ns.min DW *1:It depends on operation frequency. tsu(CAS-RAS)=(tcyc/2-13)ns.min Measuring conditions * VCC=5V10% * Input timing voltage :Determined with VIH=2.5V, VIL=0.8V * Output timing voltage :Determined with VOH=2.0V, VOL=0.8V Figure 28.12 VCC=5V timing diagram (11) Rev.1.00 Aug. 02, 2005 Page 247 REJ09B0187-0100 of 329 M16C/80 Group 28. Electrical characteristics VCC = 5V tc(TA) tw(TAH) TAiIN input tw(TAL) tc(UP) tw(UPH) TAiOUT input tw(UPL) TAiOUT input (Up/down input) During event counter mode TAiIN input (When count on falling edge is selected) th(TIN-UP) tsu(UP-TIN) TAiIN input (When count on rising edge is selected) tc(TB) tw(TBH) TBiIN input tw(TBL) tc(AD) tw(ADL) ADTRG input tc(CK) tw(CKH) CLKi tw(CKL) TxDi td(C-Q) RxDi tw(INL) INTi input tw(INH) tsu(D-C) th(C-D) th(C-Q) Figure 28.13 VCC=5V timing diagram (12) Rev.1.00 Aug. 02, 2005 Page 248 of 329 REJ09B0187-0100 M16C/80 Group 28. Electrical characteristics Memory Expansion Mode and Microprocessor Mode (Valid only with wait) VCC = 5V BCLK RD (Separate bus) WR, WRL, WRH (Separate bus) RD (Multiplexed bus) WR, WRL, WRH (Multiplexed bus) RDY input tsu(RDY-BCLK) (Valid with or without wait) th(BCLK-RDY) BCLK tsu(HOLD-BCLK) HOLD input th(BCLK-HOLD) HLDA output P0, P1, P2, P3, P4, P50 to P52 td(BCLK-HLDA) Hi-Z td(BCLK-HLDA) Measuring conditions : * VCC=5V10% * Input timing voltage : Determined with VIL=1.0V, VIH=4.0V * Output timing voltage : Determined with VOL=2.5V, VOH=2.5V Figure 28.14 VCC=5V timing diagram (13) Rev.1.00 Aug. 02, 2005 Page 249 REJ09B0187-0100 of 329 M16C/80 Group 28. Electrical characteristics Electrical characteristics (Vcc = 3V) VCC = 3V Measuring condition Standard Typ. Max. Unit Table 28.23 Electrical characteristics (referenced to VCC = 3V, VSS = 0V at Topr = 25oC, f(XIN) = 10MHZ unless otherwise specified) Symbol Parameter HIGH output P00-P07,P10-P17,P20-P27, voltage P30-P37,P40-P47,P50-P57, P60-P67,P72-P77,P80-P84, P86,P87,P90-P97,P100-P107, P110-P114, P120-P127,P130-P137, P140-P146, P150-P157 (Note 1) HIGH output voltage HIGH output voltage LOW output voltage XOUT XCOUT HIGHPOWER LOWPOWER HIGHPOWER LOWPOWER Min 2.5 VOH IOH= - 1mA , VCC = 3.0V V IOH= - 0.1 mA , VCC = 3.0V IOH= - 50 A , VCC = 3.0V With no load applied , VCC = 3.0V With no load applied , VCC = 3.0V 2.5 2.5 3.0 1.6 V V VOH VOL P00-P07,P10-P17,P20-P27, P30-P37,P40-P47,P50-P57, P60-P67,P70-P77,P80-P84, P86,P87,P90-P97,P100-P107 P110-P114, P120-P127,P130-P137, P140-P146, P150-P157 (Note 1) XOUT XCOUT HIGHPOWER LOWPOWER HIGHPOWER LOWPOWER IOL=1mA , VCC = 3.0V 0.5 V VOL LOW output voltage LOW output voltage Hysteresis IOL=0.1mA , VCC = 3.0V IOL=50A , VCC = 3.0V With no load applied , VCC = 3.0V With no load applied , VCC = 3.0V 0 0 0.5 0.5 V V VT+-VT- HOLD, RDY, TA0IN-TA4IN, TB0IN-TB2IN, INT0-INT5, ADTRG, CTS0-CTS4,CLK0-CLK4,TA2OUT-TA4OUT, NMI, KI0-KI3, RxD0-RxD4, SCL2-SCL4, SDA2-SDA4 RESET P00-P07,P10-P17,P20-P27, P30-P37,P40-P47,P50-P57, P60-P67,P70-P77,P80-P87, P90-P97,P100-P107, P110-P114, P120-P127,P130-P137, P140-P146, P150-P157 (Note 1) XIN, RESET, CNVss, BYTE P00-P07,P10-P17,P20-P27, P30-P37,P40-P47,P50-P57, P60-P67,P70-P77,P80-P87, P90-P97,P100-P107, P110-P114, P120-P127,P130-P137, P140-P146, P150-P157 (Note 1) XIN, RESET, CNVss, BYTE P00-P07,P10-P17,P20-P27, P30-P37,P40-P47,P50-P57, P60-P67,P72-P77,P80-P84, P86,P87,P90-P97,P100-P107 P110-P114, P120-P127,P130-P137, P140-P146, P150-P157 (Note 1) XIN XCIN VCC = 3.0V 0.2 1.0 V VT+-VT- Hysteresis HIGH input current VCC = 3.0V 0.2 1.8 V IIH VI=3V , VCC = 3.0V 4.0 A LOW input current I IL VI=0V , VCC = 3.0V - 4.0 A RPULLUP Pull-up resistance VI=0V , VCC = 3.0V 66.0 120.0 500.0 k RfXIN R fXCIN V RAM Feedback resistance Feedback resistance RAM retention voltage 3.0 10.0 When clock is stopped f(XIN)=10MHz Square wave, no division M M V 20.0 23.0 23.0 A 2.0 12.0 14.0 14.0 45.0 60.0 3.5 3.0 1.5 In single-chip mode, the output pins are open and other pins are VSS Mask ROM 128 KB version ROMless RAM 10 KB version (Note 2) Mask ROM 256 KB version ROMless RAM 24 KB version (Note 2) Flash memory version mA Icc Power supply current f(XCIN)=32kHz Square wave Mask ROM 128 KB version ROMless RAM 10 KB version (Note 2) Mask ROM 256 KB version ROMless RAM 24 KB version (Note 2) Flash memory version mA A A f(XCIN)=32kHz When a WAIT instruction is executed. Oscillation drive capacity is High. f(XCIN)=32kHz When a WAIT instruction is executed. Oscillation drive capacity is Low. Topr=25C, when clock is stopped Mask ROM 128 KB version ROMless RAM 10 KB version (Note 2) Mask ROM 256 KB version ROMless RAM 24 KB version (Note 2) Flash memory version 1.0 1.0 1.0 20.0 A Topr=85C, when clock is stopped Note 1: Ports P11 to P15 exist in 144-pin version. Note 2: ROMless version exists in 144-pin version. Rev.1.00 Aug. 02, 2005 Page 250 of 329 REJ09B0187-0100 M16C/80 Group 28. Electrical characteristics VCC = 3V Timing requirements (referenced to VCC = 3V, VSS = 0V at Topr = Table 28.24 External clock input Symbol tc tw(H) tw(L) tr tf Parameter External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock rise time External clock fall time 25oC unless otherwise specified) Standard Min. Max. 100 40 40 18 18 Unit ns ns ns ns ns Table 28.25 Memory expansion and microprocessor modes Symbol tac1(RD-DB) tac1(AD-DB) tac2(RD-DB) tac2(AD-DB) tac3(RD-DB) tac3(AD-DB) tac4(RAS-DB) tac4(CAS-DB) tac4(CAD-DB) tsu(DB-BCLK) tsu(RDY-BCLK ) tsu(HOLD-BCLK ) th(RD-DB) th(CAS-DB) th(BCLK -RDY) th(BCLK-HOLD ) td(BCLK-HLDA ) Parameter Data input access time (RD standard, no wait) Data input access time (AD standard, CS standard, no wait) Data input access time (RD standard, with wait) Data input access time (AD standard, CS standard, with wait) Data input access time (RD standard, when accessing multiplex bus area) Data input access time (AD standard, CS standard, when accessing multiplex bus area) Standard Unit Min. Max. (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) 40 60 80 0 0 0 0 100 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Data input access time (RAS standard, DRAM access) Data input access time (CAS standard, DRAM access) Data input access time (CAD standard, DRAM access) Data input setup time RDY input setup time HOLD input setup time Data input hold time Data input hold time RDY input hold time HOLD input hold time HLDA output delay time Note: Calculated according to the BCLK frequency as follows: Note that inserting wait or using lower operation frequency f(BCLK) is needed when calculated value is negative. tac1(RD - DB) = tac1(AD - DB) = tac2(RD - DB) = tac2(AD - DB) = tac3(RD - DB) = tac3(AD - DB) = tac4(RAS - DB) = tac4(CAS - DB) = tac4(CAD - DB) = 10 f(BCLK) X 2 10 9 f(BCLK) 10 9X m f(BCLK) X 2 10 9 X n f(BCLK) 9 - 42 - 55 - 42 - 55 [ns] [ns] [ns] (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively) [ns] (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively) [ns] (m=3 and 5 when 2 wait and 3 wait, respectively) [ns] (n=5 and 7 when 2 wait and 3 wait, respectively) [ns] (m=3 and 5 when 1 wait and 2 wait, respectively) [ns] (n=1 and 3 when 1 wait and 2 wait, respectively) [ns] (l=1 and 2 when 1 wait and 2 wait, respectively) 10 9 X m - 55 f(BCLK) X 2 10 X n - 55 f(BCLK) X 2 10 X m f(BCLK) X 2 9 9 9 - 55 10 X n - 55 f(BCLK) X 2 10 X l f(BCLK) 9 - 55 Rev.1.00 Aug. 02, 2005 Page 251 REJ09B0187-0100 of 329 M16C/80 Group 28. Electrical characteristics VCC = 3V Timing requirements (referenced to VCC = 3V, VSS = 0V at Topr = 25oC unless otherwise specified) Table 28.26 Timer A input (counter input in event counter mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. Max. 150 60 60 Unit ns ns ns Table 28.27 Timer A input (gating input in timer mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. 600 300 300 Max. Unit ns ns ns Table 28.28 Timer A input (external trigger input in one-shot timer mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. Max. 300 150 150 Unit ns ns ns Table 28.29 Timer A input (external trigger input in pulse width modulation mode) Symbol tw(TAH) tw(TAL) TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. Max. 150 150 Unit ns ns Table 28.30 Timer A input (up/down input in event counter mode) Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) TAiOUT input cycle time TAiOUT input HIGH pulse width TAiOUT input LOW pulse width TAiOUT input setup time TAiOUT input hold time Parameter Standard Min. Max. 3000 1500 1500 600 600 Unit ns ns ns ns ns Rev.1.00 Aug. 02, 2005 Page 252 of 329 REJ09B0187-0100 M16C/80 Group 28. Electrical characteristics VCC = 3V Timing requirements (referenced to VCC = 3V, VSS = 0V at Topr = 25oC unless otherwise specified) Table 28.31 Timer B input (counter input in event counter mode) Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Parameter TBiIN input cycle time (counted on one edge) TBiIN input HIGH pulse width (counted on one edge) TBiIN input LOW pulse width (counted on one edge) TBiIN input cycle time (counted on both edges) TBiIN input HIGH pulse width (counted on both edges) TBiIN input LOW pulse width (counted on both edges) Standard Min. 150 60 60 300 160 160 Max. Unit ns ns ns ns ns ns Table 28.32 Timer B input (pulse period measurement mode) Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width Parameter Standard Min. 600 300 300 Max. Unit ns ns ns Table 28.33 Timer B input (pulse width measurement mode) Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width Parameter Standard Min. Max. 600 300 300 Unit ns ns ns Table 28.34 A/D trigger input Symbol tc(AD) tw(ADL) Parameter ADTRG input cycle time (trigger able minimum) ADTRG input LOW pulse width Standard Min. 1500 200 Max. Unit ns ns Table 28.35 Serial I/O Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) CLKi input cycle time CLKi input HIGH pulse width CLKi input LOW pulse width TxDi output delay time TxDi hold time RxDi input setup time RxDi input hold time _______ Parameter Standard Min. 300 150 150 160 0 50 90 Max. Unit ns ns ns ns ns ns ns Table 28.36 External interrupt INTi inputs Symbol tw(INH) tw(INL) INTi input HIGH pulse width INTi input LOW pulse width Parameter Standard Min. 380 380 Max. Unit ns ns Rev.1.00 Aug. 02, 2005 Page 253 REJ09B0187-0100 of 329 M16C/80 Group 28. Electrical characteristics VCC = 3V Switching characteristics (referenced to VCC = 3V, VSS = 0V at Topr = 25oC unless otherwise specified) Table 28.37 Memory expansion and microprocessor modes (with no wait) Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(DB-WR) th(WR-DB) tw(WR) Parameter Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard) Address output hold time (WR standard) Chip select output delay time Chip select output hold time (BCLK standard) Chip select output hold time (RD standard) Chip select output hold time (WR standard) ALE signal output delay time ALE signal output hold time RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (WR standard) Data output hold time (WR standard) WR signal width 10 9 f(BCLK) Measuring condition Figure 28.1 Standard Min. Max. 25 0 0 (Note 1) 25 0 0 (Note 1) 25 -2 10 -3 25 0 (Note 1) (Note 1) (Note 1) Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 1: Calculated according to the BCLK frequency as follows: td(DB - WR) = th(WR - DB) = th(WR - AD) = th(WR - CS) = - 40 [ns] [ns] [ns] [ns] 10 9 f(BCLK) X 2 10 f(BCLK) X 2 10 f(BCLK) X 2 10 9 f(BCLK) X 2 9 9 - 20 - 20 - 20 tw(WR) = - 20 [ns] Rev.1.00 Aug. 02, 2005 Page 254 of 329 REJ09B0187-0100 M16C/80 Group 28. Electrical characteristics VCC = 3V Switching characteristics (referenced to VCC = 3V, VSS = 0V at Topr = 25oC unless otherwise specified) Table 28.38 Memory expansion and microprocessor modes (with wait, accessing external memory) Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(DB-WR) th(WR-DB) tw(WR) Parameter Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard) Address output hold time (WR standard) Chip select output delay time Chip select output hold time (BCLK standard) Chip select output hold time (RD standard) Chip select output hold time (WR standard) ALE signal output delay time ALE signal output hold time RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (WR standard) Data output hold time (WR standard) WR signal width Measuring condition Figure 28.1 Standard Min. Max. 25 0 0 (Note 1) 25 0 0 (Note 1) 25 -2 10 -3 25 0 (Note 1) (Note 1) (Note 1) Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 1: Calculated according to the BCLK frequency as follows: td(DB - WR) = th(WR - DB) = th(WR - AD) = th(WR - CS) = 10 9 X n - 40 f(BCLK) 9 [ns] (n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively) [ns] [ns] [ns] 10 - 20 f(BCLK) X 2 10 - 20 f(BCLK) X 2 10 9 - 20 f(BCLK) X 2 - 20 9 tw( WR) = 10 9 X n f(BCLK) X 2 [ns] (n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively) Rev.1.00 Aug. 02, 2005 Page 255 REJ09B0187-0100 of 329 M16C/80 Group 28. Electrical characteristics VCC = 3V Switching characteristics (referenced to VCC = 3V, VSS = 0V at Topr = 25oC unless otherwise specified) Table 28.39 Memory expansion and microprocessor modes (with wait, accessing external memory, multiplex bus area selected) Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(DB-WR) th(WR-DB) td(BCLK-ALE) th(BCLK-ALE) td(AD-ALE) th(ALE-AD) tdz(RD-AD) th(BCLK-DB) Parameter Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard) Address output hold time (WR standard) Chip select output delay time Chip select output hold time (BCLK standard) Chip select output hold time (RD standard) Chip select output hold time (WR standard) RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (WR standard) Data output hold time (WR standard) ALE signal output delay time (BCLK standard) ALE signal output hold time (BCLK standard) ALE signal output delay time (address standard) ALE signal output hold time (address standard) Address output flowting start time DB signal output hold time (BCLK standard) Measuring condition Standard Min. Max. 25 0 (Note 1) (Note 1) 25 0 (Note 1) (Note 1) 25 -3 25 0 (Note 1) (Note 1) 25 -2 (Note 1) (Note 1) 8 0 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 28.1 Note 1: Calculated according to the BCLK frequency as follows: th(RD - AD) = th(WR - AD) = th(RD - CS) = th(WR - CS) = 10 9 f(BCLK) X 2 10 9 f(BCLK) X 2 10 9 f(BCLK) X 2 10 9 f(BCLK) X 2 9 - 20 - 20 - 20 - 20 [ns] [ns] [ns] [ns] td(DB - WR) = 10 X m - 40 f(BCLK) X 2 10 9 f(BCLK) X 2 10 9 f(BCLK) X 2 10 9 f(BCLK) X 2 - 20 [ns] (m=3 and 5 when 2 wait and 3 wait, respectively) th(WR - DB) = [ns] td(AD - ALE) = - 27 [ns] th(ALE - AD) = - 20 [ns] Rev.1.00 Aug. 02, 2005 Page 256 of 329 REJ09B0187-0100 M16C/80 Group 28. Electrical characteristics VCC = 3V Switching characteristics (referenced to VCC = 3V, VSS = 0V at Topr = 25oC unless otherwise specified) Table 28.40 Memory expansion and microprocessor modes (with wait, accessing external memory, DRAM area selected) Symbol td(BCLK-RAD) th(BCLK-RAD) td(BCLK-CAD) th(BCLK-CAD) th(RAS-RAD) td(BCLK-RAS) th(BCLK-RAS) tRP Parameter Row address output delay time Row address output hold time (BCLK standard) String address output delay time String address output hold time (BCLK standard) Row address output hold time after RAS output RAS output delay time (BCLK standard) RAS output hold time (BCLK standard) RAS "H" hold time Measuring condition Figure 28.1 Standard Min. Max. 25 0 25 0 (Note 1) 25 0 (Note 1) 25 0 25 -3 (Note 1) -7 (Note 1) Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns td(BCLK-CAS) CAS output delay time (BCLK standard) th(BCLK-CAS) CAS output hold time (BCLK standard) td(BCLK-DW) Data output delay time (BCLK standard) th(BCLK-DW) Data output hold time (BCLK standard) CAS after DB output setup time tsu(DB-CAS) th(BCLK-DB) DB signal output hold time (BCLK standard) tsu(CAS-RAS) CAS before RAS setup time (refresh) Note 1: Calculated according to the BCLK frequency as follows: th(RAS - RAD) = 10 9 f(BCLK) X 2 10 9 X 3 f(BCLK) X 2 10 f(BCLK) 9 9 - 25 [ns] tRP = tsu(DB - CAS) = - 40 [ns] - 40 [ns] tsu(CAS - RAS) = 10 f(BCLK) X 2 - 25 [ns] Rev.1.00 Aug. 02, 2005 Page 257 REJ09B0187-0100 of 329 M16C/80 Group 28. Electrical characteristics Vcc=3V Memory expansion Mode and Microprocessor Mode (without wait) Read Timing BCLK td(BCLK-ALE) 25ns.max th(BCLK-ALE) -2ns.min ALE td(BCLK-CS) 25ns.max*1 tcyc th(BCLK-CS) 0ns.min CSi th(RD-CS) 0ns.min td(BCLK-AD) ADi BHE 25ns.max*1 th(BCLK-AD) 0ns.min td(BCLK-RD) 10ns.max th(RD-AD) 0ns.min RD tac1(RD-DB)*2 tac1(AD-DB)*2 DB Hi-Z th(BCLK-RD) -3ns.min tsu(DB-BCLK) 40ns.min*1 th(RD-DB) 0ns.min *1:It is a guarantee value with being alone. 55ns.max garantees as td(BCLK-AD)+tsu(DB-BCLK). *2:It depends on operation frequency. tac1(RD-DB)=(tcyc/2-42)ns.max tac1(AD-DB)=(tcyc-55)ns.max Write Timing ( Written by 2 cycles in selecting no wait) BCLK td(BCLK-ALE) 25ns.max th(BCLK-ALE) -2ns.min ALE td(BCLK-CS) 25ns.max th(BCLK-CS) 0ns.min CSi tcyc th(WR-CS)*3 th(BCLK-AD) 0ns.min td(BCLK-AD) ADi BHE 25ns.max td(BCLK-WR) 25ns.max tw(WR)*3 th(WR-AD)*3 th(BCLK-WR) 0ns.min WR,WRL, WRH td(DB-WR)*3 DBi *3:It depends on operation frequency. td(DB-WR)=(tcyc-40)ns.min th(WR-DB)=(tcyc/2-20)ns.min th(WR-AD)=(tcyc/2-20)ns.min th(WR-CS)=(tcyc/2-20)ns.min tw(WR)=(tcyc/2-20)ns.min th(WR-DB)*3 Measuring conditions * VCC=3V10% * Input timing voltage :Determined with VIH=1.5V, VIL=0.5V * Output timing voltage :Determined with VOH=1.5V, VOL=1.5V Figure 28.15 VCC=3V timing diagram (1) Rev.1.00 Aug. 02, 2005 Page 258 of 329 REJ09B0187-0100 M16C/80 Group 28. Electrical characteristics Vcc=3V Memory expansion Mode and Microprocessor Mode (with 1 wait) Read Timing BCLK 25ns.max td(BCLK-ALE) th(BCLK-ALE) -2ns.min ALE td(BCLK-CS) CSi 25ns.max*1 tcyc th(BCLK-CS) 0ns.min th(RD-CS) 0ns.min td(BCLK-AD) ADi BHE 25ns.max*1 th(BCLK-AD) 0ns.min td(BCLK-RD) 10ns.max th(RD-AD) 0ns.min RD tac2(RD-DB)*2 tac2(AD-DB)*2 DB Hi-Z th(BCLK-RD) -3ns.min tsu(DB-BCLK) 40ns.min*1 th(RD-DB) 0ns.min *1:It is a guarantee value with being alone. 55ns.max garantees as td(BCLK-AD)+tsu(DB-BCLK). *2:It depends on operation frequency. tac2(RD-DB)=(tcyc/2 x m-42)ns.max (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively.) tac2(AD-DB)=(tcyc x n-55)ns.max (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively.) Write Timing BCLK 25ns.max td(BCLK-ALE) ALE th(BCLK-ALE) -2ns.min td(BCLK-CS) 25ns.max th(BCLK-CS) 0ns.min CSi tcyc th(WR-CS)*3 th(BCLK-AD) 0ns.min td(BCLK-AD) 25ns.max ADi BHE td(BCLK-WR) WR,WRL, WRH 25ns.max tw(WR)*3 th(WR-AD)*3 th(BCLK-WR) td(DB-WR)*3 DBi th(WR-DB)*3 0ns.min *3:It depends on operation frequency. td(DB-WR)=(tcyc x n-40)ns.min (n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively.) th(WR-DB)=(tcyc/2-20)ns.min th(WR-AD)=(tcyc/2-20)ns.min th(WR-CS)=(tcyc/2-20)ns.min tw(WR)=(tcyc/2 x n-20)ns.min (n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively.) Measuring conditions * VCC=3V10% * Input timing voltage :Determined with VIH=1.5V, VIL=0.5V * Output timing voltage :Determined with VOH=1.5V, VOL=1.5V Figure 28.16 VCC=3V timing diagram (2) Rev.1.00 Aug. 02, 2005 Page 259 REJ09B0187-0100 of 329 M16C/80 Group 28. Electrical characteristics Vcc=3V Memory expansion Mode and Microprocessor Mode (with 2 wait) Read Timing BCLK 25ns.max td(BCLK-ALE) th(BCLK-ALE) -2ns.min ALE td(BCLK-CS) CSi 25ns.max*1 tcyc th(BCLK-CS) 0ns.min th(RD-CS) 0ns.min td(BCLK-AD) ADi BHE 25ns.max*1 th(BCLK-AD) 0ns.min td(BCLK-RD) 10ns.max th(RD-AD) 0ns.min RD tac2(RD-DB)*2 tac2(AD-DB)*2 DB Hi-Z th(BCLK-RD) -3ns.min tsu(DB-BCLK) 40ns.min*1 th(RD-DB) 0ns.min *1:It is a guarantee value with being alone. 55ns.max garantees as td(BCLK-AD)+tsu(DB-BCLK). *2:It depends on operation frequency. tac2(RD-DB)=(tcyc/2 x m-42)ns.max (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively.) tac2(AD-DB)=(tcyc x n-55)ns.max (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively.) Write Timing BCLK 25ns.max td(BCLK-ALE) ALE th(BCLK-ALE) -2ns.min td(BCLK-CS) 25ns.max th(BCLK-CS) 0ns.min CSi tcyc th(WR-CS)*3 th(BCLK-AD) 0ns.min td(BCLK-AD) 25ns.max ADi BHE td(BCLK-WR) WR,WRL, WRH 25ns.max tw(WR)*3 th(WR-AD)*3 th(BCLK-WR) td(DB-WR)*3 DBi *3:It depends on operation frequency. td(DB-WR)=(tcyc x n-40)ns.min (n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively.) th(WR-DB)=(tcyc/2-20)ns.min th(WR-AD)=(tcyc/2-20)ns.min th(WR-CS)=(tcyc/2-20)ns.min tw(WR)=(tcyc/2 x n-20)ns.min (n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively.) th(WR-DB)*3 0ns.min Measuring conditions * VCC=3V10% * Input timing voltage :Determined with VIH=1.5V, VIL=0.5V * Output timing voltage :Determined with VOH=1.5V, VOL=1.5V Figure 28.17 VCC=3V timing diagram (3) Rev.1.00 Aug. 02, 2005 Page 260 of 329 REJ09B0187-0100 M16C/80 Group 28. Electrical characteristics Memory expansion Mode and Microprocessor Mode (with 3 wait) Read Timing BCLK 25ns.max Vcc=3V td(BCLK-ALE) th(BCLK-ALE) -2ns.min ALE td(BCLK-CS) CSi 25ns.max*1 tcyc th(BCLK-CS) 0ns.min th(RD-CS) 0ns.min td(BCLK-AD) ADi BHE 25ns.max*1 th(BCLK-AD) 0ns.min td(BCLK-RD) 10ns.max th(RD-AD) 0ns.min RD tac2(RD-DB)*2 tac2(AD-DB)*2 DB Hi-Z th(BCLK-RD) -3ns.min tsu(DB-BCLK) 40ns.min*1 th(RD-DB) 0ns.min *1:It is a guarantee value with being alone. 55ns.max garantees as td(BCLK-AD)+tsu(DB-BCLK). *2:It depends on operation frequency. tac2(RD-DB)=(tcyc/2 x m-42)ns.max (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively.) tac2(AD-DB)=(tcyc x n-55)ns.max (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively.) Write Timing BCLK 25ns.max td(BCLK-ALE) ALE th(BCLK-ALE) -2ns.min td(BCLK-CS) 25ns.max th(BCLK-CS) 0ns.min CSi tcyc th(WR-CS)*3 th(BCLK-AD) 0ns.min td(BCLK-AD) 25ns.max ADi BHE td(BCLK-WR) WR,WRL, WRH 25ns.max tw(WR)*3 th(WR-AD)*3 th(BCLK-WR) td(DB-WR) DBi *3 th(WR-DB)*3 0ns.min *3:It depends on operation frequency. td(DB-WR)=(tcyc x n-40)ns.min (n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively.) th(WR-DB)=(tcyc/2-20)ns.min th(WR-AD)=(tcyc/2-20)ns.min th(WR-CS)=(tcyc/2-20)ns.min tw(WR)=(tcyc/2 x n-20)ns.min (n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively.) Measuring conditions * VCC=3V10% * Input timing voltage :Determined with VIH=1.5V, VIL=0.5V * Output timing voltage :Determined with VOH=1.5V, VOL=1.5V Figure 28.18 VCC=3V timing diagram (4) Rev.1.00 Aug. 02, 2005 Page 261 REJ09B0187-0100 of 329 M16C/80 Group 28. Electrical characteristics Memory expansion Mode and Microprocessor Mode (When accessing external memory area with 2 wait, and select multiplexed bus) Vcc=3V Read Timing BCLK td(BCLK-ALE) 25ns.max th(BCLK-ALE) -2ns.min tcyc ALE td(BCLK-CS) 25ns.max th(BCLK-CS) 0ns.min CSi th(RD-CS)*1 td(AD-ALE)*1 th(ALE-AD)*1 ADi /DBi Address tdz(RD-AD) 8ns.max Data input Address th(RD-DB) tsu(DB-BCLK) *1 40ns.min 0ns.min td(BCLK-AD) ADi BHE 25ns.max th(BCLK-AD) 0ns.min tac3(RD-DB) tac3(AD-DB)*1 RD td(BCLK-RD) 25ns.max th(BCLK-RD) -3ns.min th(RD-AD)*1 *1:It depends on operation frequency. td(AD-ALE)=(tcyc/2-27)ns.min th(ALE-AD)=(tcyc/2-20)ns.min, th(RD-AD)=(tcyc/2-20)ns.min, th(RD-CS)=(tcyc/2-20)ns.min tac3(RD-DB)=(tcyc/2 x m-55)ns.max (m=3 and 5 when 2 wait and 3 wait, respectively.) tac3(AD-DB)=(tcyc/2 x n-55)ns.max (n=5 and 7 when 2 wait and 3 wait, respectively.) Write Timing BCLK td(BCLK-ALE) 25ns.max th(BCLK-ALE) -2ns.min ALE td(BCLK-CS) CSi 25ns.max tcyc th(BCLK-CS) th(WR-CS)*2 0ns.min td(AD-ALE)*2 th(ALE-AD)*2 ADi /DBi Address Data output th(BCLK-DB) 0ns.min Address td(BCLK-AD) ADi BHE 25ns.max td(DB-WR)*2 th(WR-DB)*2 th(BCLK-AD) 0ns.min td(BCLK-WR) WR,WRL, WRH 25ns.max th(BCLK-WR) 0ns.min th(WR-AD)*2 *2:It depends on operation frequency. td(AD-ALE)=(tcyc/2-27)ns.min th(ALE-AD)=(tcyc/2-20)ns.min, th(WR-AD)=(tcyc/2-20)ns.min th(WR-CS)=(tcyc/2-20)ns.min, th(WR-DB)=(tcyc/2-20)ns.min td(DB-WR)=(tcyc/2 x m-40)ns.min (m=3 and 5 when 2 wait and 3 wait, respectively.) Measuring conditions * VCC=3V10% * Input timing voltage :Determined with VIH=1.5V, VIL=0.5V * Output timing voltage :Determined with VOH=1.5V, VOL=1.5V Figure 28.19 VCC=3V timing diagram (5) Rev.1.00 Aug. 02, 2005 Page 262 of 329 REJ09B0187-0100 M16C/80 Group 28. Electrical characteristics Memory expansion Mode and Microprocessor Mode (When accessing external memory area with 3 wait, and select multiplexed bus) Vcc=3V Read Timing BCLK td(BCLK-ALE) 25ns.max th(BCLK-ALE) -2ns.min tcyc ALE td(BCLK-CS) 25ns.max th(BCLK-CS) 0ns.min CSi th(RD-CS)*1 td(AD-ALE)*1 th(ALE-AD)*1 ADi /DBi Address tdz(RD-AD) 8ns.max Data input Address th(RD-DB) tsu(DB-BCLK) 40ns.min 0ns.min td(BCLK-AD) ADi BHE 25ns.max th(BCLK-AD) 0ns.min tac3(RD-DB)*1 tac3(AD-DB)*1 RD td(BCLK-RD) 25ns.max th(BCLK-RD) -3ns.min th(RD-AD)*1 *1:It depends on operation frequency. td(AD-ALE)=(tcyc/2-27)ns.min th(ALE-AD)=(tcyc/2-20)ns.min, th(RD-AD)=(tcyc/2-20)ns.min, th(RD-CS)=(tcyc/2-20)ns.min tac3(RD-DB)=(tcyc/2 x m-55)ns.max (m=3 and 5 when 2 wait and 3 wait, respectively.) tac3(AD-DB)=(tcyc/2 x n-55)ns.max (n=5 and 7 when 2 wait and 3 wait, respectively.) Write Timing BCLK td(BCLK-ALE) 25ns.max th(BCLK-ALE) -2ns.min ALE td(BCLK-CS) CSi 25ns.max tcyc th(BCLK-CS) th(WR-CS)*2 0ns.min td(AD-ALE)*2 th(ALE-AD)*2 ADi /DBi Address Data output th(BCLK-DB) 0ns.min Address td(BCLK-AD) ADi BHE 25ns.max td(DB-WR)*2 th(WR-DB)*2 th(BCLK-AD) 0ns.min td(BCLK-WR) WR,WRL, WRH 25ns.max th(BCLK-WR) 0ns.min th(WR-AD)*2 *2:It depends on operation frequency. td(AD-ALE)=(tcyc/2-27)ns.min th(ALE-AD)=(tcyc/2-20)ns.min, th(WR-AD)=(tcyc/2-20)ns.min th(WR-CS)=(tcyc/2-20)ns.min, th(WR-DB)=(tcyc/2-20)ns.min td(DB-WR)=(tcyc/2 x m-40)ns.min (m=3 and 5 when 2 wait and 3 wait, respectively.) Measuring conditions * VCC=3V10% * Input timing voltage :Determined with VIH=1.5V, VIL=0.5V * Output timing voltage :Determined with VOH=1.5V, VOL=1.5V Figure 28.20 VCC=3V timing diagram (6) Rev.1.00 Aug. 02, 2005 Page 263 REJ09B0187-0100 of 329 M16C/80 Group 28. Electrical characteristics Memory expansion Mode and Microprocessor Mode (When accessing DRAM area with 1 wait) Vcc=3V Read Timing BCLK tcyc td(BCLK-RAD) MAi th(BCLK-RAD) 0ns.min td(BCLK-CAD) 25ns.max*1 th(BCLK-CAD) 0ns.min 25ns.max*1 Row address String address th(RAS-RAD)*2 RAS tRP*2 th(BCLK-RAS) td(BCLK-RAS) 25ns.max*1 td(BCLK-CAS) 25ns.max*1 0ns.min CASL CASH th(BCLK-CAS) 0ns.min DW tac4(CAS-DB)*2 tac4(CAD-DB)*2 tac4(RAS-DB)*2 DB Hi-Z tsu(DB-BCLK) 40ns.min*1 th(CAS-DB) 0ns.min *1:It is a guarantee value with being alone. 55ns.max garantees as follows: td(BCLK-RAS) + tsu(DB-BCLK) td(BCLK-CAS) + tsu(DB-BCLK) td(BCLK-CAD) + tsu(DB-BCLK) *2:It depends on operation frequency. tac4(RAS-DB)=(tcyc/2 x m-55)ns.max (m=3 and 5 when 1 wait and 2 wait, respectively.) tac4(CAS-DB)=(tcyc/2 x n-55)ns.max (n=1 and 3 when 1 wait and 2 wait, respectively.) tac4(CAD-DB)=(tcyc x l-55)ns.max (l=1 and 2 when 1 wait and 2 wait, respectively.) th(RAS-RAD)=(tcyc/2-25)ns.min tRP=(tcyc/2 x 3-40)ns.min Measuring conditions * VCC=3V10% * Input timing voltage :Determined with VIH=1.5V, VIL=0.5V * Output timing voltage :Determined with VOH=1.5V, VOL=1.5V Figure 28.21 VCC=3V timing diagram (7) Rev.1.00 Aug. 02, 2005 Page 264 of 329 REJ09B0187-0100 M16C/80 Group 28. Electrical characteristics Memory expansion Mode and Microprocessor Mode (When accessing DRAM area with 1 wait) Vcc=3V Write Timing BCLK tcyc td(BCLK-RAD) 25ns.max th(BCLK-RAD) 0ns.min td(BCLK-CAD) 25ns.max th(BCLK-CAD) 0ns.min MAi Row address String address th(RAS-RAD)*1 RAS tRP*1 td(BCLK-RAS) 25ns.max td(BCLK-CAS) 25ns.max th(BCLK-RAS) 0ns.min CASL CASH th(BCLK-CAS) td(BCLK-DW) 25ns.max 0ns.min DW th(BCLK-DW) tsu(DB-CAS)*1 Hi-Z -3ns.min DB th(BCLK-DB) -7ns.min *1:It depends on operation frequency. th(RAS-RAD)=(tcyc/2-25)ns.min tRP=(tcyc/2 x 3-40)ns.min tsu(DB-CAS)=(tcyc-40)ns.min Measuring conditions * VCC=3V10% * Input timing voltage :Determined with VIH=1.5V, VIL=0.5V * Output timing voltage :Determined with VOH=1.5V, VOL=1.5V Figure 28.22 VCC=3V timing diagram (8) Rev.1.00 Aug. 02, 2005 Page 265 REJ09B0187-0100 of 329 M16C/80 Group 28. Electrical characteristics Memory expansion Mode and Microprocessor Mode (When accessing DRAM area with 2 wait) Vcc=3V Read Timing BCLK tcyc td(BCLK-RAD) MAi th(BCLK-RAD) 0ns.min td(BCLK-CAD) 25ns.max*1 th(BCLK-CAD) 0ns.min 25ns.max*1 Row address String address th(RAS-RAD)*2 RAS tRP*2 th(BCLK-RAS) 0ns.min td(BCLK-RAS) 25ns.max*1 td(BCLK-CAS) 25ns.max*1 CASL CASH th(BCLK-CAS) 0ns.min DW tac4(CAS-DB)*2 tac4(CAD-DB)*2 tac4(RAS-DB)*2 Hi-Z DB tsu(DB-BCLK) 40ns.min*1 th(CAS-DB) 0ns.min *1:It is a guarantee value with being alone. 55ns.max garantees as follows: td(BCLK-RAS) + tsu(DB-BCLK) td(BCLK-CAS) + tsu(DB-BCLK) td(BCLK-CAD) + tsu(DB-BCLK) *2:It depends on operation frequency. tac4(RAS-DB)=(tcyc/2 x m-55)ns.max (m=3 and 5 when 1 wait and 2 wait, respectively.) tac4(CAS-DB)=(tcyc/2 x n-55)ns.max (n=1 and 3 when 1 wait and 2 wait, respectively.) tac4(CAD-DB)=(tcyc x l-55)ns.max (l=1 and 2 when 1 wait and 2 wait, respectively.) th(RAS-RAD)=(tcyc/2-25)ns.min tRP=(tcyc/2 x 3-40)ns.min Measuring conditions * VCC=3V10% * Input timing voltage :Determined with VIH=1.5V, VIL=0.5V * Output timing voltage :Determined with VOH=1.5V, VOL=1.5V Figure 28.23 VCC=3V timing diagram (9) Rev.1.00 Aug. 02, 2005 Page 266 of 329 REJ09B0187-0100 M16C/80 Group 28. Electrical characteristics Memory expansion Mode and Microprocessor Mode (When accessing DRAM area with 2 wait) Vcc=3V Write Timing BCLK tcyc td(BCLK-RAD) 25ns.max th(BCLK-RAD) 0ns.min td(BCLK-CAD) 25ns.max th(BCLK-CAD) 0ns.min MAi Row address String address th(RAS-RAD)*1 RAS tRP*1 td(BCLK-RAS) td(BCLK-CAS) 25ns.max 25ns.max th(BCLK-RAS) 0ns.min CASL CASH th(BCLK-CAS) td(BCLK-DW) 25ns.max 0ns.min DW th(BCLK-DW) tsu(DB-CAS)*1 Hi-Z -3ns.min DB th(BCLK-DB) -7ns.min *1:It depends on operation frequency. th(RAS-RAD)=(tcyc/2-25)ns.min tRP=(tcyc/2 x 3-40)ns.min tsu(DB-CAS)=(tcyc-40)ns.min Measuring conditions * VCC=3V10% * Input timing voltage :Determined with VIH=1.5V, VIL=0.5V * Output timing voltage :Determined with VOH=1.5V, VOL=1.5V Figure 28.24 VCC=3V timing diagram (10) Rev.1.00 Aug. 02, 2005 Page 267 REJ09B0187-0100 of 329 M16C/80 Group 28. Electrical characteristics Memory expansion Mode and Microprocessor Mode Refresh Timing (CAS before RAS refresh) BCLK Vcc=3V td(BCLK-RAS) 25ns.max tcyc RAS tsu(CAS-RAS)*1 CASL CASH th(BCLK-RAS) 0ns.min td(BCLK-CAS) 25ns.max th(BCLK-CAS) 0ns.min DW *1:It depends on operation frequency. tsu(CAS-RAS)=(tcyc/2-25)ns.min Refresh Timing (Self-refresh) BCLK td(BCLK-RAS) 25ns.max tcyc RAS tsu(CAS-RAS)*1 CASL CASH th(BCLK-RAS) 0ns.min td(BCLK-CAS) 25ns.max th(BCLK-CAS) 0ns.min DW *1:It depends on operation frequency. tsu(CAS-RAS)=(tcyc/2-25)ns.min Measuring conditions * VCC=3V10% * Input timing voltage :Determined with VIH=1.5V, VIL=0.5V * Output timing voltage :Determined with VOH=1.5V, VOL=1.5V Figure 28.25 VCC=3V timing diagram (11) Rev.1.00 Aug. 02, 2005 Page 268 of 329 REJ09B0187-0100 M16C/80 Group 28. Electrical characteristics tc(TA) tw(TAH) TAiIN input tw(TAL) tc(UP) tw(UPH) TAiOUT input tw(UPL) TAiOUT input (Up/down input) During event counter mode TAiIN input (When count on falling edge is selected) VCC = 3V th(TIN-UP) tsu(UP-TIN) TAiIN input (When count on rising edge is selected) tc(TB) tw(TBH) TBiIN input tw(TBL) tc(AD) tw(ADL) ADTRG input tc(CK) tw(CKH) CLKi tw(CKL) TxDi td(C-Q) RxDi tw(INL) INTi input tw(INH) tsu(D-C) th(C-D) th(C-Q) Figure 28.26 VCC=3V timing diagram (12) Rev.1.00 Aug. 02, 2005 Page 269 REJ09B0187-0100 of 329 M16C/80 Group 28. Electrical characteristics Memory Expansion Mode and Microprocessor Mode (Valid only with wait) VCC = 3V BCLK RD (Separate bus) WR, WRL, WRH (Separate bus) RD (Multiplexed bus) WR, WRL, WRH (Multiplexed bus) RDY input tsu(RDY-BCLK) (Valid with or without wait) th(BCLK-RDY) BCLK tsu(HOLD-BCLK) HOLD input th(BCLK-HOLD) HLDA output P0, P1, P2, P3, P4, P50 to P52 td(BCLK-HLDA) td(BCLK-HLDA) Hi-Z Measuring conditions : * VCC=3V10% * Input timing voltage : Determined with VIH=2.4V, VIL=0.6V * Output timing voltage : Determined with VOH=1.5V, VOL=1.5V Figure 28.27 VCC=3V timing diagram (13) Rev.1.00 Aug. 02, 2005 Page 270 of 329 REJ09B0187-0100 M16C/80 Group 29. Flash Memory Version 29. Flash Memory Version Outline Performance Table 29.1 shows the outline performance of the M16C/80 (flash memory version). Table 29.1 Outline Performance of the M16C/80 (flash memory version) Item Power supply voltage Performance 5V version: f(XIN)=20MHz, without wait, 4.2V to 5.5V f(XIN)=10MHz, without wait, 2.7V to 5.5V Program/erase voltage 5V version: 4.2V to 5.5 V f(BCLK)=12.5MHz, with one wait f(BCLK)=6.25MHz, without wait Flash memory operation mode Erase block division User ROM area Boot ROM area Program method Erase method Program/erase control method Protect method Number of commands Program/erase count Data holding ROM code protect Three modes (parallel I/O, standard serial I/O, CPU rewrite) See Figure 29.3 One division (8 Kbytes) (Note 1) In units of pages (in units of 256 bytes) Collective erase/block erase Program/erase control by software command Protected for each block by lock bit 8 commands 100 times 10 years Parallel I/O and standard serial modes are supported. Note: The boot ROM area contains a standard serial I/O mode control program which is stored in it when shipped from the factory. This area can be erased and programmed in only parallel I/O mode. Rev.1.00 Aug. 02, 2005 Page 271 REJ09B0187-0100 of 329 M16C/80 Group 29. Flash Memory Version The following shows Renesas plans to develop a line of M16C/80 products (flash memory version). (1) ROM capacity (2) Package 100P6S-A ... Plastic molded QFP 100P6Q-A ... Plastic molded QFP 144P6Q-A ... Plastic molded QFP ROM size (Bytes) External ROM 256K 128K 96K 64K Flash memory version M30805FGGP M30803FGFP/GP M30802FCGP M30800FCFP/GP Figure 29.1 ROM Expansion The following lists the M16C/80 products to be supported in the future. Table 29.2 Product List Type No M30800FCFP M30800FCGP M30803FGFP M30803FGGP M30802FCGP M30805FGGP ROM capacity 128 Kbytes 256 Kbytes 128 Kbytes 256 Kbytes RAM capacity 10 Kbytes 20 Kbytes 10 Kbytes 20 Kbytes Package type 100P6S-A 100P6Q-A 100P6S-A 100P6Q-A 144P6Q-A Remarks Type No. M30800 M C - XXX FP Package type: FP : Package GP : Package 100P6S-A 100P6Q-A, 144P6Q-A ROM No. Omitted for blank external ROM version and flash memory version ROM capacity: C : 128K bytes G : 256K bytes Memory type: M : Mask ROM version S : External ROM version F : Flash memory version Shows RAM capacity, pin count, etc (The value itself has no specific meaning) M16C/80 Group M16C Family Figure 29.2 Type No., memory size, and package Rev.1.00 Aug. 02, 2005 Page 272 of 329 REJ09B0187-0100 M16C/80 Group 29. Flash Memory Version Flash Memory The M16C/80 (flash memory version) contains the flash memory that can be rewritten with a single voltage of 5 V. For this flash memory, three flash memory modes are available in which to read, program, and erase: parallel I/O and standard serial I/O modes in which the flash memory can be manipulated using a programmer and a CPU rewrite mode in which the flash memory can be manipulated by the Central Processing Unit (CPU). Each mode is detailed in the pages to follow. The flash memory is divided into several blocks as shown in Figure 29.3, so that memory can be erased one block at a time. Each block has a lock bit to enable or disable execution of an erase or program operation, allowing for data in each block to be protected. In addition to the ordinary user ROM area to store a microcomputer operation control program, the flash memory has a boot ROM area that is used to store a program to control rewriting in CPU rewrite and standard serial I/O modes. This boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. However, the user can write a rewrite control program in this area that suits the user's application system. This boot ROM area can be rewritten in only parallel I/O mode. 0FC000016 Block 6 : 64K byte 0FD000016 Block 5 : 64K byte Flash memory size 128Kbytes 256Kbytes Flash memory start address 0FE000016 0FC000016 0FE000016 Block 4 : 64K byte Note 1: The boot ROM area can be rewritten in only parallel input/output mode. (Access to any other areas is inhibited.) Note 2: To specify a block, use the maximum address in the block that is an even address. 0FF000016 0FF800016 0FFA00016 0FFC00016 0FFFFFF16 Block 3 : 32K byte Block 2 : 8K byte Block 1 : 8K byte Block 0 : 16K byte User ROM area 0FFE00016 0FFFFFF16 8K byte Boot ROM area Figure 29.3 Block diagram of flash memory version Rev.1.00 Aug. 02, 2005 Page 273 REJ09B0187-0100 of 329 M16C/80 Group 30. CPU Rewrite Mode 30. CPU Rewrite Mode In CPU rewrite mode, the on-chip flash memory can be operated on (read, program, or erase) under control of the Central Processing Unit (CPU). In CPU rewrite mode, only the user ROM area shown in Figure 29.3 can be rewritten; the boot ROM area cannot be rewritten. Make sure the program and block erase commands are issued for only the user ROM area and each block area. The control program for CPU rewrite mode can be stored in either user ROM or boot ROM area. In the CPU rewrite mode, because the flash memory cannot be read from the CPU, the rewrite control program must be transferred to any area other than the internal flash memory before it can be executed. Microcomputer Mode and Boot Mode The control program for CPU rewrite mode must be written into the user ROM or boot ROM area in parallel I/O mode beforehand. (If the control program is written into the boot ROM area, the standard serial I/O mode becomes unusable.) See Figure 29.3 for details about the boot ROM area. Normal microcomputer mode is entered when the microcomputer is reset with pulling CNVSS pin low. In this case, the CPU starts operating using the control program in the user ROM area. When the microcomputer is reset by pulling the P55 pin low, the CNVSS pin high, and the P50 pin high, the CPU starts operating using the control program in the boot ROM area. This mode is called the "boot" mode. The control program in the boot ROM area can also be used to rewrite the user ROM area. Block Address Block addresses refer to the maximum even address of each block. These addresses are used in the block erase command, lock bit program command, and read lock status command. Rev.1.00 Aug. 02, 2005 Page 274 of 329 REJ09B0187-0100 M16C/80 Group 30. CPU Rewrite Mode Outline Performance (CPU Rewrite Mode) In the CPU rewrite mode, the CPU erases, programs and reads the internal flash memory as instructed by software commands. Operations must be executed from a memory other than the internal flash memory, such as the internal RAM. When the CPU rewrite mode select bit (bit 1 at address 037716) is set to "1", transition to CPU rewrite mode occurs and software commands can be accepted. In the CPU rewrite mode, write to and read from software commands and data into even-numbered address ("0" for byte address A0) in 16-bit units. Always write 8-bit software commands into even-numbered address. Commands are ignored with odd-numbered addresses. Use software commands to control program and erase operations. Whether a program or erase operation has terminated normally or in error can be verified by reading the status register. Read data from an even address in the user ROM area when reading the status register. Figure 30.1 shows the flash memory control register 0 and the flash memory control register 1. _____ Bit 0 of the flash memory control register 0 is the RY/BY status flag used exclusively to read the operating status of the flash memory. During programming and erase operations, it is "0". Otherwise, it is "1". Bit 1 of the flash memory control register 0 is the CPU rewrite mode select bit. The CPU rewrite mode is entered by setting this bit to "1", so that software commands become acceptable. In CPU rewrite mode, the CPU becomes unable to access the internal flash memory directly. Therefore, write bit 1 in an area other than the internal flash memory. To set this bit to "1", it is necessary to write "0" and then write "1" in succession when NMI pin is "H" level. The bit can be set to "0" by only writing a "0" . Bit 2 of the flash memory control register 0 is a lock bit disable bit. By setting this bit to "1", it is possible to disable erase and write protect (block lock) effectuated by the lock bit data. The lock bit disable select bit only disables the lock bit function; it does not change the lock data bit value. However, if an erase operation is performed when this bit ="1", the lock bit data that is "0" (locked) is set to "1" (unlocked) after erasure. To set this bit to "1", it is necessary to write "0" and then write "1" in succession. This bit can be manipulated only when the CPU rewrite mode select bit = "1". Bit 3 of the flash memory control register 0 is the flash memory reset bit used to reset the control circuit of the internal flash memory. This bit is used when exiting CPU rewrite mode and when flash memory access has failed. When the CPU rewrite mode select bit is "1", writing "1" for this bit resets the control circuit. To release the reset, it is necessary to set this bit to "0". Bit 5 of the flash memory control register 0 is a user ROM area select bit which is effective in only boot mode. If this bit is set to "1" in boot mode, the area to be accessed is switched from the boot ROM area to the user ROM area. When the CPU rewrite mode needs to be used in boot mode, set this bit to "1". Note that if the microcomputer is booted from the user ROM area, it is always the user ROM area that can be accessed and this bit has no effect. When in boot mode, the function of this bit is effective regardless of whether the CPU rewrite mode is on or off. Use the control program except in the internal flash memory to rewrite this bit. Bit 3 of the flash memory control register 1 turns power supply to the internal flash memory on/off. When this bit is set to "1", power is not supplied to the internal flash memory, thus power consumption can be reduced. However, in this state, the internal flash memory cannot be accessed. To set this bit to "1", it is necessary to write "0" and then write "1" in succession. Use this bit mainly in the low speed mode (when XCIN is the block count source of BCLK). When the CPU is shifted to the stop or wait modes, power to the internal flash memory is automatically shut off. It is reconnected automatically when CPU operation is restored. Therefore, it is not particularly necessary to set flash memory control register 1. Rev.1.00 Aug. 02, 2005 Page 275 REJ09B0187-0100 of 329 M16C/80 Group 30. CPU Rewrite Mode Figure 30.2 shows a flowchart for setting/releasing the CPU rewrite mode. Figure 30.3 shows a flowchart for shifting to the low speed mode. Always perform operation as indicated in these flowcharts. Flash memory control register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol FMR0 Bit symbol Address 037716 When reset XX0000012 0 Bit name RY/BY status flag CPU rewrite mode select bit (Note 1) Function 0: Busy (being written or erased) 1: Ready 0: Normal mode (Software commands invalid) 1: CPU rewrite mode (Software commands acceptable) 0: Block lock by lock bit data is enabled 1: Block lock by lock bit data is disabled 0: Normal operation 1: Reset Must always be set to "0" 0: Boot ROM area is accessed 1: User ROM area is accessed RW RW FMR00 FMR01 FMR02 Lock bit disable bit (Note 2) FMR03 Flash memory reset bit (Note 3) Reserved bit FMR05 User ROM area select bit ( Note 4) (Effective in only boot mode) Nothing is assigned. When write, set "0". When read, values are indeterminate. Note 1: For this bit to be set to "1", the user needs to write a "0" and then a "1" to it in succession. When it is not this procedure, it is not enacted in "1". This is necessary to ensure that no interrupt or DMA transfer will be executed during the interval. Use the control program except in the internal flash memory for write to this bit. Also write to this bit when NMI pin is "H" level. Note 2: For this bit to be set to "1", the user needs to write a "0" and then a "1" to it in succession when the CPU rewrite mode select bit = "1". When it is not this procedure, it is not enacted in "1". This is necessary to ensure that no interrupt or DMA transfer will be executed during the interval. Note 3: Effective only when the CPU rewrite mode select bit = 1. Set this bit to 0 subsequently after setting it to 1 (reset). Note 4: Use the control program except in the internal flash memory for write to this bit. Flash memory control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol FMR1 Bit symbol Address 037616 When reset XXXX0XXX2 0 0 0 0 0 0 0 Bit name Function Must always be set to "0" 0: Flash memory power supply is connected 1: Flash memory power supply-off Must always be set to "0" RW RW Reserved bit FMR13 Flash memory power supply-OFF bit (Note) Reserved bit Note : For this bit to be set to "1", the user needs to write a "0" and then a "1" to it in succession. When it is not this procedure, it is not enacted in "1". This is necessary to ensure that no interrupt or DMA transfer will be executed during the interval. Use the control program except in the internal flash memory for write to this bit. During parallel I/O mode,programming,erase or read of flash memory is not controlled by this bit,only by external pins. Figure 30.1 Flash memory control registers Rev.1.00 Aug. 02, 2005 Page 276 of 329 REJ09B0187-0100 M16C/80 Group 30. CPU Rewrite Mode Program in ROM Start Program in RAM *1 Single-chip mode, memory expansion mode, or boot mode (Boot mode only) Set user ROM area select bit to "1" Set processor mode register (Note 1) Set CPU rewrite mode select bit to "1" (by writing "0" and then "1" in succession)(Note 2) Transfer CPU rewrite mode control program to internal RAM Using software command execute erase, program, or other operation (Set lock bit disable bit as required) Jump to transferred control program in RAM (Subsequent operations are executed by control program in this RAM) Execute read array command or reset flash memory by setting flash memory reset bit (by writing "1" and then "0" in succession) (Note 3) *1 Write "0" to CPU rewrite mode select bit (Boot mode only) Write "0" to user ROM area select bit (Note 4) End Note 1: During CPU rewrite mode, set the main clock frequency as shown below using the main clock division register (address 000C16): 6.25 MHz or less when wait bit (bit 2 at address 000516) = "0" (without internal access wait state) 12.5 MHz or less when wait bit (bit 2 at address 000516) = "1" (with internal access wait state) Note 2: For CPU rewrite mode select bit to be set to "1", the user needs to write a "0" and then a "1" to it in succession. When it is not this procedure, it is not enacted in "1". This is necessary to ensure that no interrupt or DMA transfer will be executed during the interval. Use the program except in the internal flash memory for write to this bit. Also write to this bit when NMI pin is "H" level. Note 3: Before exiting the CPU rewrite mode after completing erase or program operation, always be sure to execute a read array command or reset the flash memory. Note 4: "1" can be set. However, when this bit is "1", user ROM area is accessed. Figure 30.2 CPU rewrite mode set/reset flowchart Rev.1.00 Aug. 02, 2005 Page 277 REJ09B0187-0100 of 329 M16C/80 Group 30. CPU Rewrite Mode Program in ROM Start Program in RAM *1 Transfer the program to be executed in the low speed mode, to the internal RAM. Set flash memory power supply-OFF bit to "1" (by writing "0" and then "1" in succession)(Note 1) Jump to transferred control program in RAM (Subsequent operations are executed by control program in this RAM) Switch the count source of BCLK. XIN stop. (Note 2) *1 Process of low speed mode XIN oscillating Wait until the XIN has stabilized Switch the count source of BCLK (Note 2) Set flash memory power supply-OFF bit to "0" Wait time until the internal circuit stabilizes (Set NOP instruction about twice) End Note 1: For flash memory power supply-OFF bit to be set to "1", the user needs to write a "0" and then a "1" to it in succession. When it is not this procedure, it is not enacted in "1". This is necessary to ensure that no interrupt or DMA transfer will be executed during the interval. Note 2: Before the count source for BCLK can be changed from XIN to XCIN or vice versa, the clock to which the count source is going to be switched must be oscillating stably. Figure 30.3 Shifting to the low speed mode flowchart Rev.1.00 Aug. 02, 2005 Page 278 of 329 REJ09B0187-0100 M16C/80 Group 30. CPU Rewrite Mode Precautions on CPU Rewrite Mode Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode. (1) Operation speed During CPU rewrite mode, set the BCLK as shown below using the main clock division register (address 000C16): 6.25 MHz or less when wait bit (bit 2 at address 000516) = 0 (without internal access wait state) 12.5 MHz or less when wait bit (bit 2 at address 000516) = 1 (with internal access wait state) (2) Instructions inhibited against use The instructions listed below cannot be used during CPU rewrite mode because they refer to the internal data of the flash memory: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction (3) Interrupts inhibited against use The address match interrupt cannot be used during CPU rewrite mode because they refer to the internal data of the flash memory. If interrupts have their vector in the variable vector table, they can be _______ used by transferring the vector into the RAM area. The NMI and watchdog timer interrupts each can be used to change the CPU rewrite mode select bit forcibly to normal mode (FMR01="0") upon occur_______ rence of the interrupt. Since the rewrite operation is halted when the NMI and watchdog timer interrupts occur, set the CPU rewite mode select bit to "1" and the erase/program operation needs to be performed over again. (4) Reset Reset input is always accepted. (5) Access disable Write CPU rewrite mode select bit, flash memory power supply-OFF bit and user ROM area select bit in an area other than the internal flash memory. (6) How to access For CPU rewrite mode select bit, lock bit disable bit, and flash memory power supply-OFF bit to be set to "1", the user needs to write a "0" and then a "1" to it in succession. When it is not this procedure, it is not enacted in "1". This is necessary to ensure that no interrupt or DMA transfer will be executed during the interval. Write to the CPU rewrite mode select bit when NMI pin is "H" level. (7)Writing in the user ROM area If power is lost while rewriting blocks that contain the flash rewrite program with the CPU rewrite mode, those blocks may not be correctly rewritten and it is possible that the flash memory can no longer be rewritten after that. Therefore, it is recommended to use the standard serial I/O mode or parallel I/O mode to rewrite these blocks. (8)Using the lock bit To use the CPU rewrite mode, use a boot program that can set and cancel the lock command. Rev.1.00 Aug. 02, 2005 Page 279 REJ09B0187-0100 of 329 M16C/80 Group 30. CPU Rewrite Mode Software Commands Table 30.1 lists the software commands available with the M16C/62A (flash memory version). After setting the CPU rewrite mode select bit to 1, write a software command to specify an erase or program operation. Note that when entering a software command, the upper byte (D8 to D15) is ignored. The content of each software command is explained below. Table 30.1 List of software commands (CPU rewrite mode) First bus cycle Command Read array Read status register Clear status register Page program Block erase Erase all unlock block Lock bit program Read lock bit status (Note 3) Second bus cycle Mode Address Data (D0 to D7) Third bus cycle Data Mode Address (D0 to D7) Mode Write Write Write Write Write Write Write Write Address X (Note 6) Data (D0 to D7) FF16 7016 5016 4116 2016 A716 7716 7116 X X X X X X X Read X (Note 6) SRD (Note 2) Write Write Write Write Read WA0 (Note 3) WD0 (Note 3) Write BA (Note 4) WA1 WD1 D016 D016 D016 D6 (Note 5) X BA BA Note 1: When a software command is input, the high-order byte of data (D8 to D15) is ignored. Note 2: SRD = Status Register Data Note 3: WA = Write Address, WD = Write Data WA and WD must be set sequentially from 0016 to FE16 (byte address; however, an even address). The page size is 256 bytes. Note 4: BA = Block Address (Enter the maximum address of each block that is an even address.) Note 5: D6 corresponds to the block lock status. Block not locked when D6 = 1, block locked when D6 = 0. Note 6: X denotes a given address in the user ROM area (that is an even address). Read Array Command (FF16) The read array mode is entered by writing the command code "FF16" in the first bus cycle. When an even address to be read is input in one of the bus cycles that follow, the content of the specified address is read out at the data bus (D0-D15), 16 bits at a time. The read array mode is retained intact until another command is written. Read Status Register Command (7016) When the command code "7016" is written in the first bus cycle, the content of the status register is read out at the data bus (D0-D7) by a read in the second bus cycle. (Set an address to even address in the user ROM area). The status register is explained in the next section. Clear Status Register Command (5016) This command is used to clear the bits SR3 to 5 of the status register after they have been set. These bits indicate that operation has ended in an error. To use this command, write the command code "5016" in the first bus cycle. Rev.1.00 Aug. 02, 2005 Page 280 of 329 REJ09B0187-0100 M16C/80 Group 30. CPU Rewrite Mode Page Program Command (4116) Page program allows for high-speed programming in units of 256 bytes. Page program operation starts when the command code "4116" is written in the first bus cycle. In the second bus cycle through the 129th bus cycle, the write data is sequentially written 16 bits at a time. At this time, the addresses A0-A7 need to be incremented by 2 from "0016" to "FE16." When the system finishes loading the data, it starts an auto write operation (data program and verify operation). Whether the auto write operation is completed can be confirmed by reading the status register or the flash memory control register 0. At the same time the auto write operation starts, the read status register mode is automatically entered, so the content of the status register can be read out. The status register bit 7 (SR7) is set to 0 at the same time the auto write operation starts and is returned to 1 upon completion of the auto write operation. In this case, the read status register mode remains active until the Read Array command (FF16) or Read Lock Bit Status command (7116) is written or the flash memory is reset using its reset bit. ____ The RY/BY status flag of the flash memory control register 0 is 0 during auto write operation and 1 when the auto write operation is completed as is the status register bit 7. After the auto write operation is completed, the status register can be read out to know the result of the auto write operation. For details, refer to the section where the status register is detailed. Figure 30.4 shows an example of a page program flowchart. Each block of the flash memory can be write protected by using a lock bit. For details, refer to the section where the data protect function is detailed. Additional writes to the already programmed pages are prohibited. Start Write 4116 n=0 Write address n and data n NO n=n+2 n = FE16 YES RY/BY status flag = 1? YES Check full status Page program completed NO Figure 30.4 Page program flowchart Rev.1.00 Aug. 02, 2005 Page 281 REJ09B0187-0100 of 329 M16C/80 Group 30. CPU Rewrite Mode Block Erase Command (2016/D016) By writing the command code "2016" in the first bus cycle and the confirmation command code "D016" in the second bus cycle that follows to the block address of a flash memory block, the system initiates an auto erase (erase and erase verify) operation. Whether the auto erase operation is completed can be confirmed by reading the status register or the flash memory control register 0. At the same time the auto erase operation starts, the read status register mode is automatically entered, so the content of the status register can be read out. The status register bit 7 (SR7) is set to 0 at the same time the auto erase operation starts and is returned to 1 upon completion of the auto erase operation. In this case, the read status register mode remains active until the Read Array command (FF16) or Read Lock Bit Status command (7116) is written or the flash memory is reset using its reset bit. ____ The RY/BY status flag of the flash memory control register 0 is 0 during auto erase operation and 1 when the auto erase operation is completed as is the status register bit 7. After the auto erase operation is completed, the status register can be read out to know the result of the auto erase operation. For details, refer to the section where the status register is detailed. Figure 30.5 shows an example of a block erase flowchart. Each block of the flash memory can be protected against erasure by using a lock bit. For details, refer to the section where the data protect function is detailed. Start Write 2016 Write D016 Block address RY/BY status flag = 1? YES Check full status check NO Block erase completed Figure 30.5 Block erase flowchart Rev.1.00 Aug. 02, 2005 Page 282 of 329 REJ09B0187-0100 M16C/80 Group 30. CPU Rewrite Mode Erase All Unlock Blocks Command (A716/D016) By writing the command code "A716" in the first bus cycle and the confirmation command code "D016" in the second bus cycle that follows, the system starts erasing blocks successively. Whether the erase all unlock blocks command is terminated can be confirmed by reading the status register or the flash memory control register 0, in the same way as for block erase. Also, the status register can be read out to know the result of the auto erase operation. When the lock bit disable bit of the flash memory control register 0 = 1, all blocks are erased no matter how the lock bit is set. On the other hand, when the lock bit disable bit = 0, the function of the lock bit is effective and only nonlocked blocks (where lock bit data = 1) are erased. Lock Bit Program Command (7716/D016) By writing the command code "7716" in the first bus cycle and the confirmation command code "D016" in the second bus cycle that follows to the block address of a flash memory block, the system sets the lock bit for the specified block to 0 (locked). Figure 30.6 shows an example of a lock bit program flowchart. The status of the lock bit (lock bit data) can be read out by a read lock bit status command. Whether the lock bit program command is terminated can be confirmed by reading the status register or the flash memory control register 0, in the same way as for page program. For details about the function of the lock bit and how to reset the lock bit, refer to the section where the data protect function is detailed. Start Write 7716 Write D016 block address RY/BY status flag = 1? YES SR4 = 0? NO NO Lock bit program in error YES Lock bit program completed Figure 30.6 Lock bit program flowchart Rev.1.00 Aug. 02, 2005 Page 283 REJ09B0187-0100 of 329 M16C/80 Group 30. CPU Rewrite Mode Read Lock Bit Status Command (7116) By writing the command code "7116" in the first bus cycle and then the block address of a flash memory block in the second bus cycle that follows, the system reads out the status of the lock bit of the specified block on to the data (D6). Figure 30.7 shows an example of a read lock bit program flowchart. Start Write 7116 Enter block address D6 = 0? YES Blocks locked NO Blocks not locked Figure 30.7 Read lock bit status flowchart Rev.1.00 Aug. 02, 2005 Page 284 of 329 REJ09B0187-0100 M16C/80 Group 30. CPU Rewrite Mode Data Protect Function (Block Lock) Each block in Figure 29.3 has a nonvolatile lock bit to specify that the block be protected (locked) against erase/write. The lock bit program command is used to set the lock bit to 0 (locked). The lock bit of each block can be read out using the read lock bit status command. Whether block lock is enabled or disabled is determined by the status of the lock bit and how the flash memory control register 0's lock bit disable bit is set. (1) When the lock bit disable bit = 0, a specified block can be locked or unlocked by the lock bit status (lock bit data). Blocks whose lock bit data = 0 are locked, so they are disabled against erase/write. On the other hand, the blocks whose lock bit data = 1 are not locked, so they are enabled for erase/ write. (2) When the lock bit disable bit = 1, all blocks are nonlocked regardless of the lock bit data, so they are enabled for erase/write. In this case, the lock bit data that is 0 (locked) is set to 1 (nonlocked) after erasure, so that the lock bit-actuated lock is removed. Status Register The status register indicates the operating status of the flash memory and whether an erase or program operation has terminated normally or in an error. The content of this register can be read out by only writing the read status register command (7016). Table 30.2 details the status register. The status register is cleared by writing the Clear Status Register command (5016). After a reset, the status register is set to "8016." Each bit in this register is explained below. Write state machine (WSM) status (SR7) After power-on, the write state machine (WSM) status is set to 1. The write state machine (WSM) status indicates the operating status of the device, as for output on the ____ RY/BY pin. This status bit is set to 0 during auto write or auto erase operation and is set to 1 upon completion of these operations. Erase status (SR5) The erase status informs the operating status of auto erase operation to the CPU. When an erase error occurs, it is set to 1. The erase status is reset to 0 when cleared. Rev.1.00 Aug. 02, 2005 Page 285 REJ09B0187-0100 of 329 M16C/80 Group 30. CPU Rewrite Mode Program status (SR4) The program status informs the operating status of auto write operation to the CPU. When a write error occurs, it is set to 1. The program status is reset to 0 when cleared. When an erase command is in error (which occurs if the command entered after the block erase command (2016) is not the confirmation command (D016), both the program status and erase status (SR5) are set to 1. When the program status or erase status = 1, the following commands entered by command write are not accepted. Also, in one of the following cases, both SR4 and SR5 are set to 1 (command sequence error): (1) When the valid command is not entered correctly (2) When the data entered in the second bus cycle of lock bit program (7716/D016), block erase (2016/D016), or erase all unlock blocks (A716/D016) is not the D016 or FF16. However, if FF16 is entered, read array is assumed and the command that has been set up in the first bus cycle is canceled. Block status after program (SR3) If excessive data is written (phenomenon whereby the memory cell becomes depressed which results in data not being read correctly), "1" is set for the program status after-program at the end of the page write operation. In other words, when writing ends successfully, "8016" is output; when writing fails, "9016" is output; and when excessive data is written, "8816" is output. Table 30.2 Definition of each bit in status register Each bit of SRD SR7 (bit7) SR6 (bit6) SR5 (bit5) SR4 (bit4) SR3 (bit3) SR2 (bit2) SR1 (bit1) SR0 (bit0) Definition Status name Write state machine (WSM) status Reserved Erase status Program status Block status after program Reserved Reserved Reserved "1" Ready Terminated in error Terminated in error Terminated in error "0" Busy Terminated normally Terminated normally Terminated normally - Rev.1.00 Aug. 02, 2005 Page 286 of 329 REJ09B0187-0100 M16C/80 Group 30. CPU Rewrite Mode Full Status Check By performing full status check, it is possible to know the execution results of erase and program operations. Figure 30.8 shows a full status check flowchart and the action to be taken when each error occurs. Read status register YES (When reading the status register, set an even number address in the user ROM area). Command sequence error Execute the clear status register command (5016) to clear the status register. Try performing the operation one more time after confirming that the command is entered correctly. Should a block erase error occur, the block in error cannot be used. SR4=1 and SR5 =1 ? NO SR5=0? YES SR4=0? YES NO Block erase error NO Program error (page or lock bit) Execute the read lock bit status command (7116) to see if the block is locked. After removing lock, execute write operation in the same way. If the error still occurs, the page in error cannot be used. After erasing the block in error, execute write operation one more time. If the same error still occurs, the block in error cannot be used. SR3=0? YES NO Program error (block) End (block erase, program) Note: When one of SR5 to SR3 is set to 1, none of the page program, block erase, erase all unlock blocks and lock bit program commands is accepted. Execute the clear status register command (5016) before executing these commands. Figure 30.8 Full status check flowchart and remedial procedure for errors Rev.1.00 Aug. 02, 2005 Page 287 REJ09B0187-0100 of 329 M16C/80 Group 30. CPU Rewrite Mode Functions To Prevent the Flash Memory from Rewriting To prevent the contents of the flash memory version from being read out or rewritten easily, the device incorporates a ROM code protect function for use in parallel I/O mode and an ID code verify function for use in standard serial I/O mode. ROM code protect function The ROM code protect function reading out or modifying the contents of the flash memory version by using the ROM code protect control address (0FFFFFF16) during parallel I/O mode. Figure 30.9 shows the ROM code protect control address (0FFFFFF16). (This address exists in the user ROM area.) If one of the pair of ROM code protect bits is set to 0, ROM code protect is turned on, so that the contents of the flash memory version are protected against readout and modification. If both of the two ROM code protect reset bits are set to "00," ROM code protect is turned off, so that the contents of the flash memory version can be read out or modified. Once ROM code protect is turned on, the contents of the ROM code protect reset bits cannot be modified in parallel I/O mode. Use the serial I/ O or some other mode to rewrite the contents of the ROM code protect reset bits. ROM Code Protect Control Address(5) b7 b6 b5 b4 b3 b2 b1 b0 111111 Symbol ROMCP Address FFFFFF16 Factory Setting FF16(4) Bit Symbol Bit Name Reserved Bit Set to "1" b7 b6 Function RW RW (b5 - b0) 0 0 : ROM code protection active 0 1 : ROM code protection active 1 0 : ROM code protection active 1 1 : ROM code protection inactive ROM Code Protect ROMCP1 Level 1 Set Bit(1, 2, 3, 4) RW NOTES: 1. When the ROM code protection is active by the ROMCP1 bit setting, the flash memory is protected against reading or rewriting in parallel I/O mode. 2. Set the bit 5 to bit 0 to "1111112" when the ROMCP1 bit is set to a value other than "112". If the bit 5 to bit 0 are set to values other than "1111112", the ROM code protection may not become active by setting the ROMCP1 bit to a value other than "112". 3. To make the ROM code protection inactive, erase a block including the ROMCP address in standard serial I/O mode or CPU rewrite mode. 4. The ROMCP address is set to "FF16" when a block, including the ROMCP address, is erased. 5. When a value of the ROMCP address is "0016" or "FF16", the ROM code protect function is disabled. Figure 30.9 ROM code protect control address Rev.1.00 Aug. 02, 2005 Page 288 of 329 REJ09B0187-0100 M16C/80 Group 30. CPU Rewrite Mode ID Code Verify Function Use this function in standard serial I/O mode. When the contents of the flash memory are not blank, the ID code sent from the peripheral unit is compared with the ID code written in the flash memory to see if they match. If the ID codes do not match, the commands sent from the peripheral unit are not accepted. The ID code consists of 8-bit data, the areas of which, beginning with the first byte, are 0FFFFDF16, 0FFFFE316, 0FFFFEB16, 0FFFFEF16, 0FFFFF316, 0FFFFF716, and 0FFFFFB16. Write a program which has had the ID code preset at these addresses to the flash memory. Address 0FFFFDC16 to 0FFFFDF16 0FFFFE016 to 0FFFFE316 0FFFFE416 to 0FFFFE716 0FFFFE816 to 0FFFFEB16 0FFFFEC16 to 0FFFFEF16 0FFFFF016 to 0FFFFF316 0FFFFF416 to 0FFFFF716 0FFFFF816 to 0FFFFFB16 0FFFFFC16 to 0FFFFFF16 ID1 Undefined instruction vector ID2 Overflow vector BRK instruction vector ID3 Address match vector ID4 ID5 Watchdog timer vector ID6 ID7 NMI vector Reset vector 4 bytes Figure 30.10 ID code store addresses Rev.1.00 Aug. 02, 2005 Page 289 REJ09B0187-0100 of 329 M16C/80 Group 31. Parallel I/O Mode 31. Parallel I/O Mode Use an exclusive programer supporting M16C/80 (flash memory version). Refer to the instruction manual of each programer maker for the details of use. User ROM and Boot ROM Areas In parallel I/O mode, the user ROM and boot ROM areas shown in Figure 29.3 can be rewritten. Both areas of flash memory can be operated on in the same way. Program and block erase operations can be performed in the user ROM area. The user ROM area and its blocks are shown in Figure 29.3. The boot ROM area is 8 Kbytes in size. In parallel I/O mode, it is located at addresses 0FFE00016 through 0FFFFFF16. Make sure program and block erase operations are always performed within this address range. (Access to any location outside this address range is prohibited.) In the boot ROM area, an erase block operation is applied to only one 8 Kbyte block. The boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. Therefore, using the device in standard serial input/output mode, you do not need to write to the boot ROM area. Rev.1.00 Aug. 02, 2005 Page 290 of 329 REJ09B0187-0100 M16C/80 Group 31. Parallel I/O Mode Pin functions (Flash memory standard serial I/O mode) Pin VCC,VSS CNVSS RESET XIN XOUT BYTE AVCC, AVSS VREF P00 to P07 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P51 to P54, P56, P57 P50 P55 P60 to P63 P64 P65 P66 P67 P70 to P77 P80 to P84, P86, P87 P85 P90 to P97 P100 to P107 P110 to P114 P120 to P127 P130 to P137 P140 to P146 P150 to P157 Name Power input CNVSS Reset input I I I/O Description Apply 4.2V to 5.5V to Vcc pin and 0 V to Vss pin. Connect to Vcc pin. Reset input pin. While reset is "L" level, a 20 cycle or longer clock must be input to XIN pin. Connect a ceramic resonator or crystal oscillator between XIN and XOUT pins. To input an externally generated clock, input it to XIN pin and open XOUT pin. Connect this pin to Vcc or Vss. Connect AVSS to Vss and AVcc to Vcc, respectively. Enter the reference voltage for A/D converter from this pin. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" level signal. Input "L" level signal. Input "H" or "L" level signal or open. Standard serial mode 1: BUSY signal output pin Standard serial mode 2: Monitors the program operation check Standard serial mode 1: Serial clock input pin Standard serial mode 2: Input "L" level signal. Serial data input pin Serial data output pin Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Connect this pin to Vcc. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. (Note) Input "H" or "L" level signal or open. (Note) Input "H" or "L" level signal or open. (Note) Input "H" or "L" level signal or open. (Note) Input "H" or "L" level signal or open. (Note) Clock input Clock output BYTE Analog power supply input Reference voltage input Input port P0 Input port P1 Input port P2 Input port P3 Input port P4 Input port P5 CE input EPM input Input port P6 BUSY output SCLK input RxD input TxD output Input port P7 Input port P8 NMI input Input port P9 Input port P10 Input port P11 Input port P12 Input port P13 Input port P14 Input port P15 I O I I I I I I I I I I I I O I I O I I I I I I I I I I Note: Port P11 to P15 exist in 144-pin version. Rev.1.00 Aug. 02, 2005 Page 291 REJ09B0187-0100 of 329 M16C/80 Group 31. Parallel I/O Mode P07/D7 P06/D6 P05/D5 P04/D4 P03/D3 P02/D2 P01/D1 P00/D0 P107/AN7/KI3 P106/AN6/KI2 P105/AN5/KI1 P104/AN4/KI0 P103/AN3 P102/AN2 P101/AN1 AVSS P100/AN0 VREF AVcc P97/ADTRG/RXD4/SCL4/STxD4 Mode setting Signal CNVss EPM RESET CE Value Vcc Vss Vss >> Vcc Vcc 97 98 99 100 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 CNVss RESET P96/ANEX1/TXD4/SDA4/SRxD4 P95/ANEX0/CLK4 P94/DA1/TB4IN/CTS4/RTS4/SS4 P93/DA0/TB3IN/CTS3/RTS3/SS3 P92/TB2IN/TXD3/SDA3/SRxD3 P91/TB1IN/RXD3/SCL3/STxD3 P90/TB0IN/CLK3 BYTE CNVss P87/XCIN P86/XCOUT RESET XOUT VSS XIN VCC P85/NMI P84/INT2 P83/INT1 P82/INT0 P81/TA4IN/U P80/TA4OUT/U P77/TA3IN P76/TA3OUT P75/TA2IN/W P74/TA2OUT/W P73/CTS2/RTS2/TA1IN/V P72/CLK2/TA1OUT/V P71/RxD2/SCL2/TA0IN/TB5IN P70/TXD2/SDA2/TA0OUT 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 M16C/80(100-pin) Group Flash Memory Version (100P6S) P10/D8 P11/D9 P12/D10 P13/D11 P14/D12 P15/D13/INT3 P16/D14/INT4 P17/D15/INT5 P20/A0(/D0) P21/A1(/D1) P22/A2(/D2) P23/A3(/D3) P24/A4(/D4) P25/A5(/D5) P26/A6(/D6) P27/A7(/D7) Vss P30/A8(MA0)(/D8) Vcc P31/A9(MA1)(/D9) P32/A10(MA2)(/D10) P33/A11(MA3)(/D11) P34/A12(MA4)(/D12) P35/A13(MA5)(/D13) P36/A14(MA6)(/D14) P37/A15(MA7)(/D15) P40/A16(MA8) P41/A17(MA9) P42/A18(MA10) P43/A19(MA11) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Figure 31.1 Pin connections for standard serial I/O mode (1) Rev.1.00 Aug. 02, 2005 Page 292 of 329 REJ09B0187-0100 Connect oscillation circuit 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 P44/CS3/A20(MA12) P45/CS2/A21 P46/CS1/A22 P47/CS0/A23 P50/WRL/WR/CASL P51/WRH/BHE/CASH P52/RD/DW P53/BCLK/ALE/CLKOUT P54/HLDA/ALE P55/HOLD P56/ALE/RAS P57/RDY P60/CTS0/RTS0 P61/CLK0 P62/RxD0 P63/TXD0 P64/CTS1/RTS1/CTS0/CLKS1 P65/CLK1 P66/RxD1 P67/TXD1 EPM BUSY RxD Vcc Vss TxD CE SCLK M16C/80 Group 31. Parallel I/O Mode P12/D10 P11/D9 P10/D8 P07/D7 P06/D6 P05/D5 P04/D4 P03/D3 P02/D2 P01/D1 P00/D0 P107/AN7/KI3 P106/AN6/KI2 P105/AN5/KI1 P104/AN4/KI0 P103/AN3 P102/AN2 P101/AN1 AVSS P100/AN0 VREF AVcc P97/ADTRG/RxD4/SCL4/STxD4 P96/ANEX1/TxD4/SDA4/SRxD4 P95/ANEX0/CLK4 Mode setting Signal CNVss EPM RESET CE Value Vcc Vss Vss >> Vcc Vcc 100 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 CNVSS RESET P94/DA1/TB4IN/CTS4/RTS4/SS4 P93/DA0/TB3IN/CTS3/RTS3/SS3 P92/TB2IN/TxD3/SDA3/SRxD3 P91/TB1IN/RxD3/SCL3/STxD3 P90/TB0IN/CLK3 BYTE CNVss P87/XCIN P86/XCOUT RESET XOUT VSS XIN VCC P85/NMI P84/INT2 P83/INT1 P82/INT0 P81/TA4IN/U P80/TA4OUT/U P77/TA3IN P76/TA3OUT P75/TA2IN/W P74/TA2OUT/W P73/CTS2/RTS2/TA1IN/V M16C/80(100-pin) Group Flash Memory Version (100P6Q) P13/D11 P14/D12 P15/D13/INT3 P16/D14/INT4 P17/D15/INT5 P20/A0(/D0) P21/A1(/D1) P22/A2(/D2) P23/A3(/D3) P24/A4(/D4) P25/A5(/D5) P26/A6(/D6) P27/A7(/D7) Vss P30/A8(MA0)(/D8) Vcc P31/A9(MA1)(/D9) P32/A10(MA2)(/D10) P33/A11(MA3)(/D11) P34/A12(MA4)(/D12) P35/A13(MA5)(/D13) P36/A14(MA6)(/D14) P37/A15(MA7)(/D15) P40/A16(MA8) P41/A17(MA9) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Figure 31.2 Pin connections for standard serial I/O mode (2) Rev.1.00 Aug. 02, 2005 Page 293 REJ09B0187-0100 Connect oscillation circuit 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 P42/A18/(MA10) P43/A19/(MA11) P44/CS3/A20(MA12) P45/CS2/A21 P46/CS1/A22 P47/CS0/A23 P50/WRL/WR/CASL P51/WRH/BHE/CASH P52/RD/DW P53/BCLK/ALE/CLKOUT P54/HLDA/ALE P55/HOLD P56/ALE/RAS P57/RDY P60/CTS0/RTS0 P61/CLK0 P62/RxD0 P63/TXD0 P64/CTS1/RTS1/CTS0/CLKS1 P65/CLK1 P66/RxD1 P67/TXD1 P70/TXD2/SDA2/TA0OUT P71/RxD2/SCL2/TA0IN/TB5IN P72/CLK2/TA1OUT/V BUSY VCC VSS TXD CE RXD SCLK EPM of 329 M16C/80 Group 31. Parallel I/O Mode Mode setting Signal CNVss EPM RESET CE Value Vcc Vss Vss >> Vcc Vcc P43/A19(MA11) VCC P42/A18(MA10) VSS P41/A17(MA9) P40/A16(MA8) P37/A15(MA7)(/D15) P36/A14(MA6)(/D14) P35/A13(MA5)(/D13) P34/A12(MA4)(/D12) P33/A11(MA3)(/D11) P32/A10(MA2)(/D10) P31/A9(MA1)(/D9) P124 P123 P122 P121 P120 VCC P30/A8(MA0)(/D8) VSS P27/A7(/D7) P26/A6(/D6) P25/A5(/D5) P24/A4(/D4) P23/A3(/D3) P22/A2(/D2) P21/A1(/D1) P20/A0(/D0) P17/D15/INT5 P16/D14/INT4 P15/D13/INT3 P14/D12 P13/D11 P12/D10 P11/D9 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 P10/D8 P07/D7 P06/D6 P05/D5 P04/D4 P114 P113 P112 P111 P110 P03/D3 P02/D2 P01/D1 P00/D0 P157 P156 P155 P154 P153 P152 P151 VSS P150 VCC P107/AN7/KI3 P106/AN6/KI2 P105/AN5/KI1 P104/AN4/KI0 P103/AN3 P102/AN2 P101/AN1 AVSS P100/AN0 VREF AVCC P97/ADTRG/RXD4/ SCL4/STxD4 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 1 2 3 45 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 M16C/80(144-pin) Group Flash Memory Version (144P6Q) 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 P44/CS3/A20(MA12) P45/CS2/A21 P46/CS1/A22 P47/CS0/A23 P125 P126 P127 P50/WRL/WR/CASL P51/WRH/BHE/CASH P52/RD/DW P53/BCLK/ALE/CLKOUT P130 P131 VCC P132 VSS P133 P54/HLDA/ALE P55/HOLD P56/ALE/RAS P57/RDY P134 P135 P136 P137 P60/CTS0/RTS0 P61/CLK0 P62/RXD0 P63/TXD0 P64/CTS1/RTS1/CTS0/CLKS1 P65/CLK1 VSS P66/RXD1 VCC P67/TXD1 P70/TXD2/SDA2/TA0OUT CE EPM BUSY SCLK RxD TxD VCC Figure 31.3 Pin connections for standard serial I/O mode (3) Rev.1.00 Aug. 02, 2005 Page 294 of 329 REJ09B0187-0100 P146 P90/TB0IN/CLK3 P91/TB1IN/RXD3/SCL3/STxD3 P92/TB2IN/TXD3/SDA3/SRxD3 P93/DA0/TB3IN/CTS3/RTS3/SS3 P94/DA1/TB4IN/CTS4/RTS4/SS4 P95/ANEX0/CLK4 P96/ANEX1/TXD4/SDA4/SRxD4 P71/RXD2/SCL2/TA0IN/TB5IN P72/CLK2/TA1OUT/V P73/CTS2/RTS2/TA1IN/V P74/TA2OUT/W P75/TA2IN/W P76/TA3OUT P77/TA3IN P80/TA4OUT/U P81/TA4IN/U P82/INT0 P83/INT1 P84/INT2 P85/NMI VCC XIN VSS XOUT RESET P86/XCOUT P87/XCIN CNVSS BYTE P140 P141 P142 P143 P144 P145 VSS Connect oscillation circuit RESET CNVSS M16C/80 Group 32. Standard serial I/O mode 32. Standard serial I/O mode The standard serial I/O mode inputs and outputs the software commands, addresses and data needed to operate (read, program, erase, etc.) the internal flash memory. This I/O is serial. There are actually two standard serial I/O modes: mode 1, which is clock synchronized, and mode 2, which is asynchronized. Both modes require a purpose-specific peripheral unit. The standard serial I/O mode is different from the parallel I/O mode in that the CPU controls flash memory rewrite (uses the CPU's rewrite mode), rewrite data input and so forth. It is started when the reset is re_____ ________ leased, which is done when the P50 (CE) pin is "H" level, the P55 (EPM) pin "L" level and the CNVss pin "H" level. (In the ordinary command mode, set CNVss pin to "L" level.) This control program is written in the boot ROM area when the product is shipped from the factory. Accordingly, make note of the fact that the standard serial I/O mode cannot be used if the boot ROM area is rewritten in the parallel I/O mode. Figures 31.1 and 31.3 show the pin connections for the standard serial I/ O mode. Serial data I/O uses UART1 and transfers the data serially in 8-bit units. Standard serial I/O switches between mode 1 (clock synchronized) and mode 2 (clock asynchronized) according to the level of CLK1 pin when the reset is released. To use standard serial I/O mode 1 (clock synchronized), set the CLK1 pin to "H" level and release the reset. The operation uses the four UART1 pins CLK1, RxD1, TxD1 and RTS1 (BUSY). The CLK1 pin is the transfer clock input pin through which an external transfer clock is input. The TxD1 pin is for CMOS output. The RTS1 (BUSY) pin outputs an "L" level when ready for reception and an "H" level when reception starts. To use standard serial I/O mode 2 (clock asynchronized), set the CLK1 pin to "L" level and release the reset. The operation uses the two UART1 pins RxD1 and TxD1. In the standard serial I/O mode, only the user ROM area indicated in Figure 32.17can be rewritten. The boot ROM cannot. In the standard serial I/O mode, a 7-byte ID code is used. When there is data in the flash memory, commands sent from the peripheral unit (programmer) are not accepted unless the ID code matches. Rev.1.00 Aug. 02, 2005 Page 295 REJ09B0187-0100 of 329 M16C/80 Group 32. Standard serial I/O mode 32.1 Overview of standard serial I/O mode 1 (clock synchronized) In standard serial I/O mode 1, software commands, addresses and data are input and output between the MCU and peripheral units (serial programer, etc.) using 4-wire clock-synchronized serial I/O (UART1). Standard serial I/O mode 1 is engaged by releasing the reset with the P65 (CLK1) pin "H" level. In reception, software commands, addresses and program data are synchronized with the rise of the transfer clock that is input to the CLK1 pin, and are then input to the MCU via the RxD1 pin. In transmission, the read data and status are synchronized with the fall of the transfer clock, and output from the TxD1 pin. The TxD1 pin is for CMOS output. Transfer is in 8-bit units with LSB first. When busy, such as during transmission, reception, erasing or program execution, the RTS1 (BUSY) pin is "H" level. Accordingly, always start the next transfer after the RST1 (BUSY) pin is "L" level. Also, data and status registers in memory can be read after inputting software commands. Status, such as the operating state of the flash memory or whether a program or erase operation ended successfully or not, can be checked by reading the status register. Here following are explained software commands, status registers, etc. Rev.1.00 Aug. 02, 2005 Page 296 of 329 REJ09B0187-0100 M16C/80 Group 32. Standard serial I/O mode Software Commands Table 31.1 lists software commands. In the standard serial I/O mode 1, erase operations, programs and reading are controlled by transferring software commands via the RxD1 pin. Software commands are explained here below. Table 32.1 Software commands (Standard serial I/O mode 1) Control command 1 Page read 1st byte transfer 2nd byte Address (middle) Address (middle) Address (middle) D016 SRD output Address (middle) Address (middle) 3rd byte Address (high) Address (high) Address (high) SRD1 output Address (high) Address (high) 4th byte 5th byte 6th byte Data output Data input D016 Data output Data input Data output Data input Data output to 259th byte Data input to 259th byte FF16 When ID is not verified Not acceptable Not acceptable Not acceptable Not acceptable Acceptable Not acceptable Not acceptable Not acceptable Not acceptable Not acceptable 2 Page program 4116 3 4 5 6 7 Block erase Erase all unlocked blocks Read status register Clear status register Read lock bit status 2016 A716 7016 5016 7116 Lock bit data output D016 8 9 Lock bit program Lock bit enable 7716 7A16 7516 10 Lock bit disable 11 Code processing function 12 Download function Address (middle) Size FA16 Size (low) (high) F516 Version data output Address (middle) Version data output Address (high) Check data (high) Address (low) Address (high) Checksum Version data output Data output 13 Version data output function FB16 ID1 To Data required input number of times Version Version data data output output Data output Data output ID size To ID7 Acceptable Not acceptable 14 Boot ROM area output function 15 Read check data FC16 Version data output to 9th byte Data output to 259th byte Acceptable Not acceptable Not acceptable Check FD16 data (low) Note 1: Shading indicates transfer from flash memory microcomputer to peripheral unit. All other data is transferred from the peripheral unit to the flash memory microcomputer. Note 2: SRD refers to status register data. SRD1 refers to status register data1 . Note 3: All commands can be accepted when the flash memory is totally blank. Rev.1.00 Aug. 02, 2005 Page 297 REJ09B0187-0100 of 329 M16C/80 Group 32. Standard serial I/O mode Page Read Command This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page read command as explained here following. (1) Transfer the "FF16" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, data (D0-D7) for the page (256 bytes) specified with addresses A8 to A23 will be output sequentially from the smallest address first in sync with the rise of the clock. CLK1 RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY) FF16 A8 to A15 A16 to A23 data0 data255 Figure 32.1 Timing for page read Read Status Register Command This command reads status information. When the "7016" command code is sent with the 1st byte, the contents of the status register (SRD) specified with the 2nd byte and the contents of status register 1 (SRD1) specified with the 3rd byte are read. CLK1 RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY) 7016 SRD output SRD1 output Figure 32.2 Timing for reading the status register Rev.1.00 Aug. 02, 2005 Page 298 of 329 REJ09B0187-0100 M16C/80 Group 32. Standard serial I/O mode Clear Status Register Command This command clears the bits (SR3-SR5) which are set when the status register operation ends in error. When the "5016" command code is sent with the 1st byte, the aforementioned bits are cleared. When the clear status register operation ends, the RTS1 (BUSY) signal changes from the "H" to the "L" level. CLK1 RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY) 5016 Figure 32.3 Timing for clearing the status register Page Program Command This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page program command as explained here following. (1) Transfer the "4116" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, as write data (D0-D7) for the page (256 bytes) specified with addresses A8 to A23 is input sequentially from the smallest address first, that page is automatically written. When reception setup for the next 256 bytes ends, the RTS1 (BUSY) signal changes from the "H" to the "L" level. The result of the page program can be known by reading the status register. For more information, see the section on the status register. Each block can be write-protected with the lock bit. For more information, see the section on the data protection function. Additional writing is not allowed with already programmed pages. CLK1 RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY) 4116 A8 to A15 A16 to A23 data0 data255 Figure 32.4 Timing for the page program Rev.1.00 Aug. 02, 2005 Page 299 REJ09B0187-0100 of 329 M16C/80 Group 32. Standard serial I/O mode Block Erase Command This command erases the data in the specified block. Execute the block erase command as explained here following. (1) Transfer the "2016" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) Transfer the verify command code "D016" with the 4th byte. With the verify command code, the erase operation will start for the specified block in the flash memory. Write the highest address of the specified block for addresses A16 to A23. When block erasing ends, the RTS1 (BUSY) signal changes from the "H" to the "L" level. After block erase ends, the result of the block erase operation can be known by reading the status register. For more information, see the section on the status register. Each block can be erase-protected with the lock bit. For more information, see the section on the data protection function. CLK1 RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY) 2016 A8 to A15 A16 to A23 D016 Figure 32.5 Timing for block erasing Rev.1.00 Aug. 02, 2005 Page 300 of 329 REJ09B0187-0100 M16C/80 Group 32. Standard serial I/O mode Erase All Unlocked Blocks Command This command erases the content of all blocks. Execute the erase all unlocked blocks command as explained here following. (1) Transfer the "A716" command code with the 1st byte. (2) Transfer the verify command code "D016" with the 2nd byte. With the verify command code, the erase operation will start and continue for all blocks in the flash memory. When block erasing ends, the RTS1 (BUSY) signal changes from the "H" to the "L" level. The result of the erase operation can be known by reading the status register. Each block can be erase-protected with the lock bit. For more information, see the section on the data protection function. CLK1 RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY) A716 D016 Figure 32.6 Timing for erasing all unlocked blocks Lock Bit Program Command This command writes "0" (lock) for the lock bit of the specified block. Execute the lock bit program command as explained here following. (1) Transfer the "7716" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) Transfer the verify command code "D016" with the 4th byte. With the verify command code, "0" is written for the lock bit of the specified block. Write the highest address of the specified block for addresses A8 to A23. When writing ends, the RTS1 (BUSY) signal changes from the "H" to the "L" level. Lock bit status can be read with the read lock bit status command. For information on the lock bit function, reset procedure and so on, see the section on the data protection function. CLK1 RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY) 7716 A8 to A15 A16 to A23 D016 Figure 32.7 Timing for the lock bit program Rev.1.00 Aug. 02, 2005 Page 301 REJ09B0187-0100 of 329 M16C/80 Group 32. Standard serial I/O mode Read Lock Bit Status Command This command reads the lock bit status of the specified block. Execute the read lock bit status command as explained here following. (1) Transfer the "7116" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) The lock bit data of the specified block is output with the 4th byte. The 6th bit (D6) of output data is the lock bit data. Write the highest address of the specified block for addresses A8 to A23. CLK1 RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY) 7116 A8 to A15 A16 to A23 DQ6 Figure 32.8 Timing for reading lock bit status Lock Bit Enable Command This command enables the lock bit in blocks whose bit was disabled with the lock bit disable command. The command code "7A16" is sent with the 1st byte of the serial transmission. This command only enables the lock bit function; it does not set the lock bit itself. CLK1 RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY) 7A16 Figure 32.9 Timing for enabling the lock bit Rev.1.00 Aug. 02, 2005 Page 302 of 329 REJ09B0187-0100 M16C/80 Group 32. Standard serial I/O mode Lock Bit Disable Command This command disables the lock bit. The command code "7516" is sent with the 1st byte of the serial transmission. This command only disables the lock bit function; it does not set the lock bit itself. However, if an erase command is executed after executing the lock bit disable command, "0" (locked) lock bit data is set to "1" (unlocked) after the erase operation ends. In any case, after the reset is cancelled, the lock bit is enabled. CLK1 RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY) 7516 Figure 32.10 Timing for disabling the lock bit Download Command This command downloads a program to the RAM for execution. Execute the download command as explained here following. (1) Transfer the "FA16" command code with the 1st byte. (2) Transfer the program size with the 2nd and 3rd bytes. (3) Transfer the check sum with the 4th byte. The check sum is added to all data sent with the 5th byte onward. (4) The program to execute is sent with the 5th byte onward. When all data has been transmitted, if the check sum matches, the downloaded program is executed. The size of the program will vary according to the internal RAM. CLK1 RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY) FA16 Data size (low) Check sum Program data Program data Data size (high) Figure 32.11 Timing for download Rev.1.00 Aug. 02, 2005 Page 303 REJ09B0187-0100 of 329 M16C/80 Group 32. Standard serial I/O mode Version Information Output Command This command outputs the version information of the control program stored in the boot area. Execute the version information output command as explained here following. (1) Transfer the "FB16" command code with the 1st byte. (2) The version information will be output from the 2nd byte onward. This data is composed of 8 ASCII code characters. CLK1 RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY) FB16 'V' 'E' 'R' 'X' Figure 32.12 Timing for version information output Boot ROM Area Output Command This command outputs the control program stored in the boot ROM area in one page blocks (256 bytes). Execute the boot ROM area output command as explained here following. (1) Transfer the "FC16" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, data (D0-D7) for the page (256 bytes) specified with addresses A8 to A23 will be output sequentially from the smallest address first, in sync with the rise of the clock. CLK1 RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY) FC16 A8 to A15 A16 to A23 data0 data255 Figure 32.13 Timing for boot ROM area output Rev.1.00 Aug. 02, 2005 Page 304 of 329 REJ09B0187-0100 M16C/80 Group 32. Standard serial I/O mode ID Check This command checks the ID code. Execute the boot ID check command as explained here following. (1) Transfer the "F516" command code with the 1st byte. (2) Transfer addresses A0 to A7, A8 to A15 and A16 to A23 of the 1st byte of the ID code with the 2nd, 3rd and 4th bytes respectively. (3) Transfer the number of data sets of the ID code with the 5th byte. (4) The ID code is sent with the 6th byte onward, starting with the 1st byte of the code. CLK1 RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY) F516 DF16 FF16 0F16 ID size ID1 ID7 Figure 32.14 Timing for the ID check ID Code When the flash memory is not blank, the ID code sent from the peripheral units and the ID code written in the flash memory are compared to see if they match. If the codes do not match, the command sent from the peripheral units is not accepted. An ID code contains 8 bits of data. Area is, from the 1st byte, addresses 0FFFFDF16, 0FFFFE316, 0FFFFEB16, 0FFFFEF16, 0FFFFF316, 0FFFFF716 and 0FFFFFB16. Write a program into the flash memory, which already has the ID code set for these addresses. Address 0FFFFDC16 to 0FFFFDF16 0FFFFE016 to 0FFFFE316 0FFFFE416 to 0FFFFE716 0FFFFE816 to 0FFFFEB16 0FFFFEC16 to 0FFFFEF16 0FFFFF016 to 0FFFFF316 0FFFFF416 to 0FFFFF716 0FFFFF816 to 0FFFFFB16 0FFFFFC16 to 0FFFFFF16 ID1 Undefined instruction vector ID2 Overflow vector BRK instruction vector ID3 Address match vector ID4 ID5 Watchdog timer vector ID6 ID7 NMI vector Reset vector 4 bytes Figure 32.15 ID code storage addresses Rev.1.00 Aug. 02, 2005 Page 305 REJ09B0187-0100 of 329 M16C/80 Group 32. Standard serial I/O mode Read Check Data This command reads the check data that confirms that the write data, which was sent with the page program command, was successfully received. (1) Transfer the "FD16" command code with the 1st byte. (2) The check data (low) is received with the 2nd byte and the check data (high) with the 3rd. To use this read check data command, first execute the command and then initialize the check data. Next, execute the page program command the required number of times. After that, when the read check command is executed again, the check data for all of the read data that was sent with the page program command during this time is read. The check data is the result of CRC operation of write data. CLK1 RxD1 (M16C reception data) TxD1 (M16C transmit data) FD16 Check data (low) RTS1(BUSY) Check data (high) Figure 32.16 Timing for the read check data Rev.1.00 Aug. 02, 2005 Page 306 of 329 REJ09B0187-0100 M16C/80 Group 32. Standard serial I/O mode Data Protection (Block Lock) Each of the blocks in Figure 32.17 have a nonvolatile lock bit that specifies protection (block lock) against erasing/writing. A block is locked (writing "0" for the lock bit) with the lock bit program command. Also, the lock bit of any block can be read with the read lock bit status command. Block lock disable/enable is determined by the status of the lock bit itself and execution status of the lock bit disable and lock enable bit commands. (1) After the reset has been cancelled and the lock bit enable command executed, the specified block can be locked/unlocked using the lock bit (lock bit data). Blocks with a "0" lock bit data are locked and cannot be erased or written in. On the other hand, blocks with a "1" lock bit data are unlocked and can be erased or written in. (2) After the lock bit enable command has been executed, all blocks are unlocked regardless of lock bit data status and can be erased or written in. In this case, lock bit data that was "0" before the block was erased is set to "1" (unlocked) after erasing, therefore the block is actually unlocked with the lock bit. 0FC000016 Block 6 : 64K byte 0FD000016 Block 5 : 64K byte 0FE000016 Block 4 : 64K byte Flash memory Flash memory size start address 128 Kbytes 256 Kbytes 0FE000016 0FC000016 0FF000016 0FF800016 0FFA00016 0FFC00016 0FFFFFF16 Block 3 : 32K byte Block 2 : 8K byte Block 1 : 8K byte Block 0 : 16K byte User ROM area Figure 32.17 Blocks in the user area Rev.1.00 Aug. 02, 2005 Page 307 REJ09B0187-0100 of 329 M16C/80 Group 32. Standard serial I/O mode Status Register (SRD) The status register indicates operating status of the flash memory and status such as whether an erase operation or a program ended successfully or in error. It can be read by writing the read status register command (7016). Also, the status register is cleared by writing the clear status register command (5016). Table 32.2 gives the definition of each status register bit. After clearing the reset, the status register outputs "8016". Table 32.2 Status register (SRD) SRD0 bits SR7 (bit7) SR6 (bit6) SR5 (bit5) SR4 (bit4) SR3 (bit3) SR2 (bit2) SR1 (bit1) SR0 (bit0) Status name Write state machine (WSM) status Reserved Erase status Program status Block status after program Reserved Reserved Reserved Definition "1" Ready Terminated in error Terminated in error Terminated in error "0" Busy Terminated normally Terminated normally Terminated normally - Write State Machine (WSM) Status (SR7) The write state machine (WSM) status indicates the operating status of the flash memory. When power is turned on, "1" (ready) is set for it. The bit is set to "0" (busy) during an auto write or auto erase operation, but it is set back to "1" when the operation ends. Erase Status (SR5) The erase status reports the operating status of the auto erase operation. If an erase error occurs, it is set to "1". When the erase status is cleared, it is set to "0". Program Status (SR4) The program status reports the operating status of the auto write operation. If a write error occurs, it is set to "1". When the program status is cleared, it is set to "0". Program Status After Program (SR3) If excessive data is written (phenomenon whereby the memory cell becomes depressed which results in data not being read correctly), "1" is set for the program status after-program at the end of the page write operation. In other words, when writing ends successfully, "8016" is output; when writing fails, "9016" is output; and when excessive data is written, "8816" is output. If "1" is written for any of the SR5, SR4 or SR3 bits, the page program, block erase, erase all unlocked blocks and lock bit program commands are not accepted. Before executing these commands, execute the clear status register command (5016) and clear the status register. Rev.1.00 Aug. 02, 2005 Page 308 of 329 REJ09B0187-0100 M16C/80 Group 32. Standard serial I/O mode Status Register 1 (SRD1) Status register 1 indicates the status of serial communications, results from ID checks and results from check sum comparisons. It can be read after the SRD by writing the read status register command (7016). Also, status register 1 is cleared by writing the clear status register command (5016). Table 31.3 gives the definition of each status register 1 bit. "0016" is output when power is turned ON and the flag status is maintained even after the reset. Table 32.3 Status register 1 (SRD1) SRD1 bits SR15 (bit7) SR14 (bit6) SR13 (bit5) SR12 (bit4) SR11 (bit3) SR10 (bit2) Status name Boot update completed bit Reserved Reserved Checksum match bit ID check completed bits Definition "1" Update completed "0" Not update Mismatch Not verified Verification mismatch Reserved Verified Normal operation - Match 00 01 10 11 Time out - SR9 (bit1) SR8 (bit0) Data receive time out Reserved Boot Update Completed Bit (SR15) This flag indicates whether the control program was downloaded to the RAM or not, using the download function. Check Sum Consistency Bit (SR12) This flag indicates whether the check sum matches or not when a program, is downloaded for execution using the download function. ID Check Completed Bits (SR11 and SR10) These flags indicate the result of ID checks. Some commands cannot be accepted without an ID check. Data Reception Time Out (SR9) This flag indicates when a time out error is generated during data reception. If this flag is attached during data reception, the received data is discarded and the microcomputer returns to the command wait state. Rev.1.00 Aug. 02, 2005 Page 309 REJ09B0187-0100 of 329 M16C/80 Group 32. Standard serial I/O mode Full Status Check Results from executed erase and program operations can be known by running a full status check. Figure 32.18 shows a flowchart of the full status check and explains how to remedy errors which occur. Read status register YES (When reading the status register, set an even number address in the user ROM area). Command sequence error Execute the clear status register command (5016) to clear the status register. Try performing the operation one more time after confirming that the command is entered correctly. Should a block erase error occur, the block in error cannot be used. SR4=1 and SR5 =1 ? NO SR5=0? YES SR4=0? YES NO Block erase error NO Program error (page or lock bit) Execute the read lock bit status command (7116) to see if the block is locked. After removing lock, execute write operation in the same way. If the error still occurs, the page in error cannot be used. After erasing the block in error, execute write operation one more time. If the same error still occurs, the block in error cannot be used. SR3=0? YES NO Program error (block) End (block erase, program) Note: When one of SR5 to SR3 is set to 1, none of the page program, block erase, erase all unlock blocks and lock bit program commands is accepted. Execute the clear status register command (5016) before executing these commands. Figure 32.18 Full status check flowchart and remedial procedure for errors Example Circuit Application for The Standard Serial I/O Mode 1 The below figure shows a circuit application for the standard serial I/O mode 1. Control pins will vary according to peripheral unit (programmer), therefore see the peripheral unit (programmer) manual for more information. Clock input BUSY output Data input Data output CLK1 RTS1(BUSY) RXD1 TXD1 M16C/80 Flash memory version CNVss NMI P50(CE) P55(EPM) (1) Control pins and external circuitry will vary according to peripheral unit (programmer). For more information, see the peripheral unit (programmer) manual. (2) In this example, the microprocessor mode and standard serial I/O mode are switched via a switch. Figure 32.19 Example circuit application for the standard serial I/O mode 1 Rev.1.00 Aug. 02, 2005 Page 310 of 329 REJ09B0187-0100 M16C/80 Group 32. Standard serial I/O mode 32.2 Overview of standard serial I/O mode 2 (clock asynchronized) In standard serial I/O mode 2, software commands, addresses and data are input and output between the MCU and peripheral units (serial programer, etc.) using 2-wire clock-asynchronized serial I/O (UART1). Standard serial I/O mode 2 is engaged by releasing the reset with the P65 (CLK1) pin "L" level. The TxD1 pin is for CMOS output. Data transfer is in 8-bit units with LSB first, 1 stop bit and parity OFF. After the reset is released, connections can be established at 9,600 bps when initial communications (Figure 32.20) are made with a peripheral unit. However, this requires a main clock with a minimum 2 MHz input oscillation frequency. Baud rate can also be changed from 9,600 bps to 19,200, 38,400, 57,600 or 115,200 bps by executing software commands. However, communication errors may occur because of the oscillation frequency of the main clock. If errors occur, change the main clock's oscillation frequency and the baud rate. After executing commands from a peripheral unit that requires time to erase and write data, as with erase and program commands, allow a sufficient time interval or execute the read status command and check how processing ended, before executing the next command. Data and status registers in memory can be read after transmitting software commands. Status, such as the operating state of the flash memory or whether a program or erase operation ended successfully or not, can be checked by reading the status register. Here following are explained initial communications with peripheral units, how frequency is identified and software commands. Initial communications with peripheral units After the reset is released, the bit rate generator is adjusted to 9,600 bps to match the oscillation frequency of the main clock, by sending the code as prescribed by the protocol for initial communications with peripheral units (Figure 32.20). (1) Transmit "0016" from a peripheral unit 16 times. (The MCU with internal flash memory sets the bit rate generator so that "0016" can be successfully received.) (2) The MCU with internal flash memory outputs the "B016" check code and initial communications end successfully *1. Initial communications must be transmitted at a speed of 9,600 bps and a transfer interval of a minimum 15 ms. Also, the baud rate at the end of initial communications is 9,600 bps. *1. If the peripheral unit cannot receive "B016" successfully, change the oscillation frequency of the main clock. Peripheral unit MCU with internal flash memory Reset (1) Transfer "0016" 16 times At least 15ms transfer interval 15 th 16th 1st 2nd "0016" "0016" "0016" "0016" "B016" (2) Transfer check code "B016" The bit rate generator setting completes (9600bps) Figure 32.20 Peripheral unit and initial communication Rev.1.00 Aug. 02, 2005 Page 311 REJ09B0187-0100 of 329 M16C/80 Group 32. Standard serial I/O mode How frequency is identified When "0016" data is received 16 times from a peripheral unit at a baud rate of 9,600 bps, the value of the bit rate generator is set to match the operating frequency (2 - 20 MHz). The highest speed is taken from the first 8 transmissions and the lowest from the last 8. These values are then used to calculate the bit rate generator value for a baud rate of 9,600 bps. Baud rate cannot be attained with some operating frequencies. Table 32.4 gives the operation frequency and the baud rate that can be attained for. Table 32.4 Operation frequency and the baud rate Operation frequency (MHZ) 20MHz 16MHZ 12MHZ 11MHZ 10MHZ 8MHZ 7.3728MHZ 6MHZ 5MHZ 4.5MHZ 4.194304MHZ 4MHZ 3.58MHZ 3MHZ 2MHZ Baud rate 9,600bps Baud rate 19,200bps Baud rate 38,400bps Baud rate 57,600bps Baud rate 115,200bps - - - - - - - - - - - - - - - - - - - - - - - : Communications possible - : Communications not possible Rev.1.00 Aug. 02, 2005 Page 312 of 329 REJ09B0187-0100 M16C/80 Group 32. Standard serial I/O mode Software Commands Table 32.5 lists software commands. In the standard serial I/O mode 2, erase operations, programs and reading are controlled by transferring software commands via the RxD1 pin. Standard serial I/O mode 2 adds five transmission speed commands - 9,600, 19,200, 38,400, 57,600 and 115,200 bps - to the software commands of standard serial I/O mode 1. Software commands are explained here below. Table 32.5 Software commands (Standard serial I/O mode 2) Control command 1 2 Page read Page program 1st byte transfer 2nd byte Address (middle) Address (middle) Address (middle) D016 SRD output Address (middle) Address (middle) 3rd byte Address (high) Address (high) Address (high) SRD1 output Address (high) Address (high) 4th byte 5th byte 6th byte Data output Data input D016 Data output Data input Data output Data input Data output to 259th byte Data input to 259th byte FF16 4116 When ID is not verified Not acceptable Not acceptable Not acceptable Not acceptable Acceptable Not acceptable Not acceptable Not acceptable Not acceptable Not acceptable 3 4 5 6 7 8 9 Block erase Erase all unlocked blocks Read status register Clear status register Read lock bit status Lock bit program Lock bit enable 2016 A716 7016 5016 7116 7716 7A16 7516 Lock bit data output D016 10 Lock bit disable 11 Code processing function 12 Download function Address (middle) Size FA16 Size (low) (high) F516 Address (low) Version data output Address (middle) Version data output Address (high) Check data (high) Address (high) Checksum Version data output Data output 13 Version data output function FB16 ID1 To Data required input number of times Version Version data data output output Data output Data output ID size To ID7 Acceptable Not acceptable 14 Boot ROM area output function 15 Read check data FC16 Version data output to 9th byte Data output to 259th byte Acceptable Not acceptable Not acceptable Check FD16 data (low) 16 Baud rate 9600 17 Baud rate 19200 18 Baud rate 38400 19 Baud rate 57600 20 Baud rate 115200 B016 B116 B216 B316 B416 B016 B116 B216 B316 B416 Acceptable Acceptable Acceptable Acceptable Acceptable Note 1: Shading indicates transfer from flash memory microcomputer to peripheral unit. All other data is transferred from the peripheral unit to the flash memory microcomputer. Note 2: SRD refers to status register data. SRD1 refers to status register data 1. Note 3: All commands can be accepted when the flash memory is totally blank. Rev.1.00 Aug. 02, 2005 Page 313 REJ09B0187-0100 of 329 M16C/80 Group 32. Standard serial I/O mode Page Read Command This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page read command as explained here following. (1) Transfer the "FF16" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, data (D0-D7) for the page (256 bytes) specified with addresses A8 to A23 will be output sequentially from the smallest address first in sync with the rise of the clock. RxD1 (M16C reception data) TxD1 (M16C transmit data) FF16 A8 to A15 A16 to A23 data0 data255 Figure 32.21 Timing for page read Read Status Register Command This command reads status information. When the "7016" command code is sent with the 1st byte, the contents of the status register (SRD) specified with the 2nd byte and the contents of status register 1 (SRD1) specified with the 3rd byte are read. RxD1 (M16C reception data) TxD1 (M16C transmit data) 7016 SRD output SRD1 output Figure 32.22 Timing for reading the status register Clear Status Register Command This command clears the bits (SR3-SR5) which are set when the status register operation ends in error. When the "5016" command code is sent with the 1st byte, the aforementioned bits are cleared. RxD1 (M16C reception data) TxD1 (M16C transmit data) 5016 Figure 32.23 Timing for clearing the status register Rev.1.00 Aug. 02, 2005 Page 314 of 329 REJ09B0187-0100 M16C/80 Group 32. Standard serial I/O mode Page Program Command This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page program command as explained here following. (1) Transfer the "4116" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, as write data (D0-D7) for the page (256 bytes) specified with addresses A8 to A23 is input sequentially from the smallest address first, that page is automatically written. The result of the page program can be known by reading the status register. For more information, see the section on the status register. Each block can be write-protected with the lock bit. For more information, see the section on the data protection function. Additional writing is not allowed with already programmed pages. RxD1 (M16C reception data) TxD1 (M16C transmit data) 4116 A8 to A15 A16 to A23 data0 data255 Figure 32.24 Timing for the page program Block Erase Command This command erases the data in the specified block. Execute the block erase command as explained here following. (1) Transfer the "2016" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) Transfer the verify command code "D016" with the 4th byte. With the verify command code, the erase operation will start for the specified block in the flash memory. Write the highest address of the specified block for addresses A16 to A23. After block erase ends, the result of the block erase operation can be known by reading the status register. For more information, see the section on the status register. Each block can be erase-protected with the lock bit. For more information, see the section on the data protection function. RxD1 (M16C reception data) TxD1 (M16C transmit data) Figure 32.25 Timing for block erasing 2016 A8 to A15 A16 to A23 D016 Rev.1.00 Aug. 02, 2005 Page 315 REJ09B0187-0100 of 329 M16C/80 Group 32. Standard serial I/O mode Erase All Unlocked Blocks Command This command erases the content of all blocks. Execute the erase all unlocked blocks command as explained here following. (1) Transfer the "A716" command code with the 1st byte. (2) Transfer the verify command code "D016" with the 2nd byte. With the verify command code, the erase operation will start and continue for all blocks in the flash memory. The result of the erase operation can be known by reading the status register. Each block can be eraseprotected with the lock bit. For more information, see the section on the data protection function. RxD1 (M16C reception data) TxD1 (M16C transmit data) A716 D016 Figure 32.26 Timing for erasing all unlocked blocks Lock Bit Program Command This command writes "0" (lock) for the lock bit of the specified block. Execute the lock bit program command as explained here following. (1) Transfer the "7716" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) Transfer the verify command code "D016" with the 4th byte. With the verify command code, "0" is written for the lock bit of the specified block. Write the highest address of the specified block for addresses A8 to A23. Lock bit status can be read with the read lock bit status command. For information on the lock bit function, reset procedure and so on, see the section on the data protection function. RxD1 (M16C reception data) TxD1 (M16C transmit data) 7716 A8 to A15 A16 to A23 D016 Figure 32.27 Timing for the lock bit program Rev.1.00 Aug. 02, 2005 Page 316 of 329 REJ09B0187-0100 M16C/80 Group 32. Standard serial I/O mode Read Lock Bit Status Command This command reads the lock bit status of the specified block. Execute the read lock bit status command as explained here following. (1) Transfer the "7116" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) The lock bit data of the specified block is output with the 4th byte. Write the highest address of the specified block for addresses A8 to A23. RxD1 (M16C reception data) TxD1 (M16C transmit data) 7116 A8 to A15 A16 to A23 DQ6 Figure 32.28 Timing for reading lock bit status Lock Bit Enable Command This command enables the lock bit in blocks whose bit was disabled with the lock bit disable command. The command code "7A16" is sent with the 1st byte of the serial transmission. This command only enables the lock bit function; it does not set the lock bit itself. RxD1 (M16C reception data) TxD1 (M16C transmit data) 7A16 Figure 32.29 Timing for enabling the lock bit Rev.1.00 Aug. 02, 2005 Page 317 REJ09B0187-0100 of 329 M16C/80 Group 32. Standard serial I/O mode Lock Bit Disable Command This command disables the lock bit. The command code "7516" is sent with the 1st byte of the serial transmission. This command only disables the lock bit function; it does not set the lock bit itself. However, if an erase command is executed after executing the lock bit disable command, "0" (locked) lock bit data is set to "1" (unlocked) after the erase operation ends. In any case, after the reset is cancelled, the lock bit is enabled. RxD1 (M16C reception data) TxD1 (M16C transmit data) 7516 Figure 32.30 Timing for disabling the lock bit Download Command This command downloads a program to the RAM for execution. Execute the download command as explained here following. (1) Transfer the "FA16" command code with the 1st byte. (2) Transfer the program size with the 2nd and 3rd bytes. (3) Transfer the check sum with the 4th byte. The check sum is added to all data sent with the 5th byte onward. (4) The program to execute is sent with the 5th byte onward. When all data has been transmitted, if the check sum matches, the downloaded program is executed. The size of the program will vary according to the internal RAM. RxD1 (M16C reception data) TxD1 (M16C transmit data) FA16 Data size (low) Check sum Program data Program data Data size (high) Figure 32.31 Timing for download Rev.1.00 Aug. 02, 2005 Page 318 of 329 REJ09B0187-0100 M16C/80 Group 32. Standard serial I/O mode Version Information Output Command This command outputs the version information of the control program stored in the boot area. Execute the version information output command as explained here following. (1) Transfer the "FB16" command code with the 1st byte. (2) The version information will be output from the 2nd byte onward. This data is composed of 8 ASCII code characters. RxD1 (M16C reception data) TxD1 (M16C transmit data) FB16 'V' 'E' 'R' 'X' Figure 32.34 Timing for version information output Boot ROM Area Output Command This command outputs the control program stored in the boot ROM area in one page blocks (256 bytes). Execute the boot ROM area output command as explained here following. (1) Transfer the "FC16" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, data (D0-D7) for the page (256 bytes) specified with addresses A8 to A23 will be output sequentially from the smallest address first, in sync with the rise of the clock. RxD1 (M16C reception data) TxD1 (M16C transmit data) FC16 A8 to A15 A16 to A23 data0 data255 Figure 32.33 Timing for boot ROM area output Rev.1.00 Aug. 02, 2005 Page 319 REJ09B0187-0100 of 329 M16C/80 Group 32. Standard serial I/O mode ID Check This command checks the ID code. Execute the boot ID check command as explained here following. (1) Transfer the "F516" command code with the 1st byte. (2) Transfer addresses A0 to A7, A8 to A15 and A16 to A23 of the 1st byte of the ID code with the 2nd, 3rd and 4th bytes respectively. (3) Transfer the number of data sets of the ID code with the 5th byte. (4) The ID code is sent with the 6th byte onward, starting with the 1st byte of the code. RxD1 (M16C reception data) TxD1 (M16C transmit data) F516 DF16 FF16 0F16 ID size ID1 ID7 Figure 32.34 Timing for the ID check ID Code When the flash memory is not blank, the ID code sent from the peripheral units and the ID code written in the flash memory are compared to see if they match. If the codes do not match, the command sent from the peripheral units is not accepted. An ID code contains 8 bits of data. Area is, from the 1st byte, addresses 0FFFFDF16, 0FFFFE316, 0FFFFEB16, 0FFFFEF16, 0FFFFF316, 0FFFFF716 and 0FFFFFB16. Write a program into the flash memory, which already has the ID code set for these addresses. Address 0FFFFDC16 to 0FFFFDF16 0FFFFE016 to 0FFFFE316 0FFFFE416 to 0FFFFE716 0FFFFE816 to 0FFFFEB16 0FFFFEC16 to 0FFFFEF16 0FFFFF016 to 0FFFFF316 0FFFFF416 to 0FFFFF716 0FFFFF816 to 0FFFFFB16 0FFFFFC16 to 0FFFFFF16 ID1 Undefined instruction vector ID2 Overflow vector BRK instruction vector ID3 Address match vector ID4 ID5 Watchdog timer vector ID6 ID7 NMI vector Reset vector 4 bytes Figure 32.35 ID code storage addresses Rev.1.00 Aug. 02, 2005 Page 320 of 329 REJ09B0187-0100 M16C/80 Group 32. Standard serial I/O mode Read Check Data This command reads the check data that confirms that the write data, which was sent with the page program command, was successfully received. (1) Transfer the "FD16" command code with the 1st byte. (2) The check data (low) is received with the 2nd byte and the check data (high) with the 3rd. To use this read check data command, first execute the command and then initialize the check data. Next, execute the page program command the required number of times. After that, when the read check command is executed again, the check data for all of the read data that was sent with the page program command during this time is read. The check data is the result of CRC operation of write data. RxD1 (M16C reception data) TxD1 (M16C transmit data) FD16 Check data (low) Check data (high) Figure 32.36 Timing for the read check data Baud Rate 9600 This command changes baud rate to 9,600 bps. Execute it as follows. (1) Transfer the "B016" command code with the 1st byte. (2) After the "B016" check code is output with the 2nd byte, change the baud rate to 9,600 bps. RxD1 (M16C reception data) TxD1 (M16C transmit data) B016 B016 Figure 32.37 Timing of baud rate 9600 Rev.1.00 Aug. 02, 2005 Page 321 REJ09B0187-0100 of 329 M16C/80 Group 32. Standard serial I/O mode Baud Rate 19200 This command changes baud rate to 19,200 bps. Execute it as follows. (1) Transfer the "B116" command code with the 1st byte. (2) After the "B116" check code is output with the 2nd byte, change the baud rate to 19,200 bps. RxD1 (M16C reception data) TxD1 (M16C transmit data) B116 B116 Figure 32.38 Timing of baud rate 19200 Baud Rate 38400 This command changes baud rate to 38,400 bps. Execute it as follows. (1) Transfer the "B216" command code with the 1st byte. (2) After the "B216" check code is output with the 2nd byte, change the baud rate to 38,400 bps. RxD1 (M16C reception data) TxD1 (M16C transmit data) B216 B216 Figure 32.39 Timing of baud rate 38400 Baud Rate 57600 This command changes baud rate to 57,600 bps. Execute it as follows. (1) Transfer the "B316" command code with the 1st byte. (2) After the "B316" check code is output with the 2nd byte, change the baud rate to 57,600 bps. RxD1 (M16C reception data) TxD1 (M16C transmit data) B316 B316 Figure 32.40 Timing of baud rate 57600 Rev.1.00 Aug. 02, 2005 Page 322 of 329 REJ09B0187-0100 M16C/80 Group 32. Standard serial I/O mode Baud Rate 115200 This command changes baud rate to 115,200 bps. Execute it as follows. (1) Transfer the "B416" command code with the 1st byte. (2) After the "B416" check code is output with the 2nd byte, change the baud rate to 19,200 bps. RxD1 (M16C reception data) TxD1 (M16C transmit data) B416 B416 Figure 32.41 Timing of baud rate 115200 Example Circuit Application for The Standard Serial I/O Mode 2 The below figure shows a circuit application for the standard serial I/O mode 2. CLK1 Monitor output Data input Data output RTS1(BUSY) RXD1 TXD1 M16C/80 Flash memory version CNVss NMI P50(CE) P55(EPM) (1) In this example, the microprocessor mode and standard serial I/O mode are switched via a switch. Figure 32.42 Example circuit application for the standard serial I/O mode 2 Rev.1.00 Aug. 02, 2005 Page 323 REJ09B0187-0100 of 329 M16C/80 Group 33. Appendix External ROM version with built-in boot loader 33. Appendix External ROM version with built-in boot loader External ROM version of M16C/80 is available with built-in boot loader (firmware). By using the boot loader, users can download their rewrite program of Flash memory to the internal RAM. When using the following Flash memory*, reprogramming of the external Flash memory can be done without downloading the rewrite program. For more detail, please refer to the "Volume Boot Loader" in the application note of M16C/80 external ROM version. *: M5M29GB/T160BVP, M5M29GB/T320BVP and the equivalent of these. The following shows Renesas plans to develop a line of M16C/80 products with built-in boot loader. (1) ROM capacity (2) Package 100P6S-A ... Plastic molded QFP 100P6Q-A ... Plastic molded QFP 144P6Q-A ... Plastic molded QFP ROM size (Bytes) M30805SGP-BL M30803SFP/GP-BL M30802SGP-BL M30800SFP/GP-BL External ROM 256K 128K External ROM version Figure 33.1 ROM Expansion The following lists the M16C/80 products to be supported in the future. Table 33.1 Product List Type No M30800SFP-BL M30800SGP-BL M30802SGP-BL M30803SFP-BL M30803SGP-BL M30805SGP-BL ROM capacity RAM capacity 10 Kbytes Package type 100P6S-A 100P6Q-A 144P6Q-A Remarks External ROM version with built-in boot loader 24 Kbytes 100P6S-A 100P6Q-A 144P6Q-A Rev.1.00 Aug. 02, 2005 Page 324 of 329 REJ09B0187-0100 M16C/80 Group 33. Appendix External ROM version with built-in boot loader Type No. M 3 0 8 0 2 M C - X X X G P - BL Boot loader Package type: FP : Package GP : Package 100P6S-A 100P6Q-A, 144P6Q-A ROM No. Omitted for blank external ROM version and flash memory version ROM capacity: C : 128K bytes G : 256K bytes Memory type: M : Mask ROM version S : External ROM version F : Flash memory version Shows RAM capacity, pin count, etc (The value itself has no specific meaning) M16C/80 Group M16C Family Figure 33.2 Type No., memory size, and package Rev.1.00 Aug. 02, 2005 Page 325 REJ09B0187-0100 of 329 M16C/80 Group Package Dimensions Package Dimension 100P6S-A Recommended JEDEC Code - HD D Weight(g) 1.58 Lead Material Alloy 42 Plastic 100pin 1420mm body QFP MD e EIAJ Package Code QFP100-P-1420-0.65 1 80 b2 100 81 I2 Recommended Mount Pad Symbol HE E 30 51 31 50 A L1 A A1 A2 b c D E e HD HE L L1 x y b2 I2 MD ME F b A1 e y x M L Detail F Dimension in Millimeters Min Nom Max - - 3.05 0.1 0.2 0 - - 2.8 0.25 0.3 0.4 0.13 0.15 0.2 13.8 14.0 14.2 19.8 20.0 20.2 - 0.65 - 16.5 16.8 17.1 22.5 22.8 23.1 0.4 0.6 0.8 1.4 - - - - 0.13 - - 0.1 - 0 10 - - 0.35 1.3 - - 14.6 - - - - 20.6 A2 100P6Q-A Recommended JEDEC Code - Weight(g) 0.63 Lead Material Cu Alloy c Plastic 100pin 1414mm body LQFP MD e EIAJ Package Code LQFP100-P-1414-0.50 D 100 76 1 75 b2 HD l2 Recommended Mount Pad Symbol A A1 A2 b c D E e HD HE L L1 Lp A3 25 51 26 50 A e F L1 x y b2 I2 MD ME M Detail F Lp Rev.1.00 Aug. 02, 2005 Page 326 of 329 REJ09B0187-0100 c b x y L Dimension in Millimeters Min Nom Max - - 1.7 0.1 0.2 0 - - 1.4 0.13 0.18 0.28 0.105 0.125 0.175 13.9 14.0 14.1 13.9 14.0 14.1 0.5 - - 15.8 16.0 16.2 15.8 16.0 16.2 0.3 0.5 0.7 1.0 - - 0.6 0.75 0.45 0.25 - - - - 0.08 0.1 - - 0 10 - 0.225 - - 0.9 - - 14.4 - - - - 14.4 HE E A2 A1 A3 ME ME M16C/80 Group Package Dimensions 144P6Q-A Recommended JEDEC Code - HD Weight(g) 1.23 Lead Material Cu Alloy Plastic 144pin 2020mm body LQFP MD e EIAJ Package Code LQFP144-P-2020-0.50 144 109 1 108 b2 D l2 Recommended Mount Pad Symbol A A1 A2 b c D E e HD HE L L1 Lp A3 36 73 37 72 A F L1 e A2 A3 x y b2 I2 MD ME y b x M L Detail F Lp Dimension in Millimeters Min Nom Max 1.7 - - 0.125 0.2 0.05 1.4 - - 0.17 0.22 0.27 0.105 0.125 0.175 19.9 20.0 20.1 19.9 20.0 20.1 0.5 - - 21.8 22.0 22.2 21.8 22.0 22.2 0.35 0.5 0.65 1.0 - - 0.45 0.6 0.75 - 0.25 - - - 0.08 0.1 - - 0 8 - 0.225 - - 0.95 - - 20.4 - - - - 20.4 HE E A1 Rev.1.00 Aug. 02, 2005 Page 327 REJ09B0187-0100 of 329 c ME M16C/80 Group Register Index Register Index A AD0 to AD7 169 ADCON0 168, 170, 171, 172, 173, 174 ADCON1 168, 170, 171, 172, 173, 174 ADCON2 169 ADIC 63 AIER 73 K KUPIC 63 M MCD 47 O ONSF 96 B BCN2IC to BCN4IC 63 P P0 to P10 197 P11 198 P12 to P13 197 P14 198 P15 197 PCR 206 PD0 to PD10 195 PD11 196 PD12 to P13 195 PD14 196 PD15 195 PM0 27 PM1 28 PRCR 55 PS0 to PS1 200 PS2 to PS3 201 PSC 203 PSL0 PSL2 202 PSL3 203 PUR0 to PUR2 204 PUR3 to PUR4 205 C CM0 46, 79 CM1 46 CPSRF 96, 107 CRCD 178 CRCIN 178 D DA0 to DA1 177 DACON 177 DCT0 to DCT3 84 DM0IC to DM3IC 63 DM0SL to DM3SL 82 DMA0 to DMA3 85 DMD0 to DMD1 83 DRA0 to DRA3 85 DRAMCONT 183 DRC0 to DRC3 84 DS 31 DSA0 to DSA3 85 DTT 113 F FMR0 to FMR1 276 R REFCNT 185 RLVL 49, 64 RMAD0 to RMAD3 ROMCP 288 I ICTB2 113 IDB0 to IDB1 113 IFSR 71 INT0IC to INT5IC 63 INVC0 to INVC1 112 73 S S0RIC to S4RIC 63 S0TIC to S4TIC 63 Rev.1.00 Aug. 02, 2005 Page 328 of 329 REJ09B0187-0100 M16C/80 Group Register Index T TA0,TA3 95 TA0IC to TA4IC 63 TA0MR to TA4MR 94, 97, 98, 103, 104 TA1,TA2,TA4 95, 114 TA11,TA21,TA41 114 TA1MR,TA2MR,TA4MR 115 TA2MR to TA4MR 100 TABSR 95, 107, 114 TB0,TB1,TB3,TB4,TB5 107 TB0IC to TB5IC 63 TB0MR to TB5MR 106, 108, 109, 110 TB2 107, 114 TB2MR 115 TBSR 107 TRGSR 96, 114 U U0BRG to U4BRG 129 U0C0 to U2C0 131 U0C1 to U4C1 133 U0MR to U4MR 130, 139, 146 U0RB to U4RB 129 U0TB to U4TB 129 U2SMR to U4SMR 134, 156 U2SMR2 to U4SMR2 135, 156 U2SMR3 136 U3C0 to U4C0 132 U3SMR3 to U4SMR3 136, 163 UCON 134 UDF 95 W WCR 40 WDC 79 WDTS 79 X X0R to X15R XYC 180 181 Y Y0R to Y15R 181 Rev.1.00 Aug. 02, 2005 Page 329 REJ09B0187-0100 of 329 M16C/80 Group Revision History Version REV.B * Page 1 line 5 * Page 1 line 15 * Page 1 line 16 Contents for change 1 M byte --> 16 M bytes 10 MHz with software one wait --> 10 MHz : under planning 35 mW (f(XIN)=20MHz, without software wait, Vcc=5V; M30800MC- Revision date '98. 10.19 XXXFP target value ) --> 45 mA (M30800MC-XXXFP) * Page 1 X-Y converter ---- 1 circuit Addition * Page 4 line 28 35 mA --> 45 mA * Page 6 figure 1.1.4 * Page 18 figure 1.5.4 and corresponding pages (106) Peripheral subfunction select register --> Function select register C (107) Port function select register 0 --> Function select register A0 (108) Port function select register 1 --> Function select register A1 (109) Peripheral function select register 0 --> Function select register B0 (110) Peripheral function select register 1 --> Function select register B1 (111) Port function select register 2 --> Function select register A2 (112) Port function select register 3 --> Function select register A3 (113) Peripheral function select register 2 --> Function select register B2 * Page 21 figure 1.6.3 Register name change same as figure 1.5.4 * Page 24 figure 1.8.1 Processor mode register 0 Note 6 --> Note 7, Note 6 Addition Processor mode register 1 Note 3 * Page 31 line 4 Addition: The ALE signal is occurred regardless of internal area and external area. __ _____ ______ * Page 31 table 1.10.4, Page 33 table 1.10.5 R/W --> RD/WR * Page 42 table 1.11.4 System clock control register 0 Note 2 * Page 51 line 7, table 1.15.1 port function select register 3 (address 03B516) --> port function select register 3 (address 03B516) and D/A control register (address 039C16) * Page 60 line 3 the interrupt occurs. --> the interrupt can be set to occur on input signal level and input signal edge. * Page 65 line 10 Set register --> When writing to DCT2, DCT3, DRC2, DRC3, DMA2 and DMA3, set register * Page 67 table 1.20.2 * Page 86 line 1 * Page 93 line 16 Addition: Note 5 successively when --> successively two times when Count source input --> Count source input (Set the corresponding func- tion select register A to I/O port.) * Page 114 table 1.25.6, page 122 table 1.26.1 UARTi transmit/receive mode register UARTi transmit/receive mode register Addition: Note 2 Addition: Note 3 * Page 115 table 1.25.7 UARTi transmit/receive mode register 0 Delate: Note 3 * Page 120 line 13 Addition: -Set the corresponding function select register A to I/O port * Page 123 table 1.26.3 * Page 130 table 1.27.3 * Page 139 figure 1.29.2 * Page 142 line 2 062316 --> 032616 * Page 144 table 1.29.5 * Page 156 table 1.31.2 D/A control register (Note) Addition: Note ____ * Page 164 figure 1.34.2 16-bit bus mode A9 --> A9 * Page 165 line 5 f32 --> BCLK(frequency x 32) C- 1 M16C/80 Group Revision History Version REV.B * Page 165 figure 1.34.3 Contents for change operation clock --> BCLK Revision date '98.10.19 * Page 169 they function as output regardless of the contents of the direction registers. When pins are to be used as the outputs for the D/A converter, do not set the direction registers to output mode. --> set the corresponding function select registers A, B and C. When pins are to be used as the outputs for the D/A converter, set the function select register of each pin to I/O port, and set the direction registers to input mode. Table 1.35.1 lists each port and peripheral function. REV.C All page M30800MC-XXXFP --> M16C/80 (100-pin version) group changed, GP package is added Note 1 and Note 2 is added '98.3.2 Page 2 Figure 1 Page 3 Figure 3 Page 5 Figure 4, Table 2 New type no. is added Page 6 Figure 5 GP is added Page 10 Line 2 18 registers --> 28 registers Page 11 (7) Set USP and ISP to an even number so that execution efficiency is increased. --> added Page 17 Figure 11 (54) UART4 special mode register 3 --> added Page 18 Figure 12 UART3 special mode register 3 --> added UART2 special mode register 3 --> added Function select register B3 --> added Page 20 Figure 14 UART4 special mode register 3 --> added UART3 special mode register 3 --> added UART2 special mode register 3 --> added Page 21 Figure 15 Function select register B3 --> added Page 24 Figure 23 PM1 Note 4 -->added Page 31 Figure 26 Page 45 Table 14, Page 46 Table 15 Page 50 Figure 32-4 Changed Page 51 Line 6 Page 52 Line 17 Note --> added port function select register 3 --> function select register A3 FFFFE416 to FFFFE716 are all --> FFFFE716 is Page 53 Table 17 BRK instruction If the vector is --> If the contents of FFFFE716 is Page 53 Table 18 Instruction fetch and DBC --> delated Page 58 Figure 36 IPL --> RLVL Page 61 Figure 38 004D16 --> 009316 Page 67 Figure 44-1Note 3 and 6 --> added Page 68 Figure 45 memory --> memory (forward direction) Page 70 Figure 46-2DMAi memory address reload register Note: vector register (SVP) --> save PC register (SVP) Page 84 Figure 56 Note 4 addresses 034216 and 034316 --> address 034316 Page 93 Table 30 Count source: TBj overflow --> added Page 96 Figure 69 Three-phase PWM control register 0 Note 4:both bit 0 and 1 --> bit 1 C-2 M16C/80 Group Revision History Version REV.C Contents for change Three-phase PWM control register 1 Page 100 Line 1 In three-phase --> In "L" active output polarity in three-phase Page 100 Line 26,31 the state of set by port direction register --> the high-impedance state Page 101 Figure 73 Right: INV14 --> added Page 103 Figure 74 Page 108 Table 32 UART4 LSB first/MSB first selection : Note 1 --> Note 2 Page 118 Figure 83 UART transmit/receive control register 2 Page 119 Figure UART 3,4 special mode register 3 --> added Page 126 Line 3 CLK and CLKS select bit (bits 4 and 5 at address 037016) --> port function select register (bits of related to-P64 and P65) Page 145 Page 176 Table 124 P91: STxD3 output --> added P97: STxD4 output --> added Page 178 Figure 125-2 Function select register A3 Page 179 Figure 125-3 Page 180 Figure 125-4 Page 187 A/D Converter Page 188 DMAC Function select register B0 Function select register B3 (5) Revision date '98.3.2 Page1 Supply voltage 4.0V-5.5V, Mask ROM version is added. Page 5 Table 1.1.1 DMAC 2 channels --> 4 channels Page 8 Page 9 P0 description is changed P6 description is changed '98.4.12 P7, 8, 9, 10 equivalent to P0 --> P6 Page 10 Figure 1.2.1 M30800FC, M30803FG are added. Page 18 Figure 1.4.3 Page 19 Figure 1.4.4 (15) DRAM control register 0XXX0000 --> ?XXX???? Delate Note, (143)-(147) 00 --> ?? Page 20 Figure 1.5.1 Add Note Page 25 Figure 1.6.1 Processor mode register 1 When reset 0016 --> C016 Page 30 Line 15 ... output to A9 to A20 --> A8 to A20 Page 32 Figure 1.7.2 Page 35 (8) BCLK output Page 38 Figure 1.7.6 Page 39 Figure 1.7.7 Page 40 Figure 1.8.1 and 1.8.2 Page 42 Page 43 Figure 1.8.4 Page 44 Figure 1.8.5 Page 45 Page 47 Line 15 ... as BCLK --> as BCLK from the interrupt routine Table 1.8.3 Page 48 Status Transition of BCLK Page 51 Figure 1.8.7 Page 52 Line 6, Figure 1.8.6 Page 56 Line 14 Delate D/A control register Note Note 2, Line 6 Pin outputs "L" is delated. C- 3 M16C/80 Group Revision History Version REV.C Contents for change Page 58 Table 1.9.3 Software interrupt number 40,41, Add fault error, Add Note 2 Page 59 Interrupt control register Line 4 delate Page 64 Interrupt sequence (1) Page 66 Saving registers Last line added Page 67 Interrupt Priority *1 delated, Last line added Page 72 (2) Setting the stack pointer Last line added Page 74 Watchdog timer Line 2 A watchdog timer interrupt is generated when --> Whether a watchdog timer interrupt is generated or reset is selected when Last part :Watchdog timer function select bit is initialized only at reset. After reset, watchdog timer interrupt is selected. added Page 75 Figure 75 System clock control register 0 added Page 97 Figure 1.13.9 Count value Page 181 Figure 1.25.4 Page 182 Figure 1.25.5 Page 131 Figure 1.16.12 Page 135 Table 1.17.3 Page 132 Table 1.18.3 Page 147 Figure 1.19.1 Both register Note2 added RxDi bit 1 and 6 at address 03C716 --> bit 1 and 7 ... RxDi bit 1 and 6 at address 03C716 --> bit 1 and 7 ... Upper figure changed, note added Revision date Page 153 Bit 4 overflow --> underflow Page 154 Figure 1.20.3 overflow --> underflow Page 159 Clock phase setting UARTi transmission-reception control register 0 ..., whereas UARTi special mode register 3 ... --> Bit 6 of UARTi transmission-reception control register 0 ..., whereas bit 1 of UARTi special mode register 3 ... Line 15 ... output is high impedance. --> ... output is indeterminate. Page 171 Line 3 Set the function select register A to I/O port and the direction register to input mode. added Page 171 Figure 1.22.2 Note delate Page 176 Figure 1.24.3 added Page 178 Figure 1.25.1 When reset --> indeterminate, Note 4 is added. Page 200 Table 1.26.2 and 1.26.3 and Figure 1.26.14 CNVss is added Page 204Electric characteristics added th(BCLK-DW) add th(BCLK-CAS) --> th(BCLK-DW) WR, WRL, WRH(sepalate bus) wave change 99.5.20 99.6.4 99.5.12 Rev.C1 Page 214 Table 1.28.22 Page 220 Figure 1.28.6 Page 223 Figure 1.28.9 Rev.C2 Page 24 Line 3 same ... A software reset has almost the same ... --> A software reset has the Page 161 Note 2: When f(XIN) is over 10 MHz, the fAD frequency must be under 10 MHz by dividing. --> addition Page 18 Figure 1.4.3 Page 19 Figure 1.4.4 Page 22 Figure 1.5.3 (60) Timer B3,4,5 count start flag value change Flash memory control register 0 and 1 added Flash memory control register 0 and 1 added 99.7.6 C-4 M16C/80 Group Revision History Version Page 43 Figure 1.8.4 Contents for change CM0 Note 5 delate Revision date Page 81 Figure 1.11.5 DMAi memory address reload register Address DRA2, DRA3 00000016 --> XXXXXX16 Page 181, 182 Figures 1.25.4-1.25.5 D0-D15 waveform changed Page 185 (6) Pull up control register changed Page 208 Table 1.28.3 VT+-VTTB0IN-TB2IN --> TB0IN-TB5IN, TA2OUT-TA4OUT --> TA0OUT-TA4OUT Page 211 Table 1.28.19 Page 212 Table 1.28.20 Page 213 Table 1.28.21 Page 214 Table 1.28.22 Page 216 Figure 1.28.2 Page 217 Figure 1.28.3 Page 218 Figure 1.28.4 Page 219 Figure 1.28.5 Page 220 Figure 1.28.6 Page 221 Figure 1.28.7 Page 223 Figure 1.28.9 Rev.C3 Flash memory ROM version added Page 2,3 Figure 1.1.1, 1.1.2 Rev.D Page 1 Japanese font change to English font 99.9.24 99.12.8 14/3/'00 * DMAC...4 channels (trigger: 24 sources) --> 31 sources * Supply voltage 4.2 to 5.5V (f(XIN)=20MHz) Flash memory version--> addition * Interrupt...4 software --> 5 software Page 1,5 Table 1.1.1 Feature * Memory capacity ROM 128 Kbytes --> (See ROM expansion figure.) RAM 10K --> 10/20 Kbytes Page 5 Table 1.1.1 Interrupt...4 software --> 5 software Page 2, 3 Figure 1.1.1, 1.1.2 Note 1 addition Page 6 Figure 1.1.4, Table 1.1.2 M30803MG-XXXFP/GP addition Page 7 Figure1.1.5 ROM capacity G:256 Kbytes addition Page 8 P00 to P07 However, it is possible to select pull-up resistance presence to the usable port as I/O port by setting. --> addition CNVss Connect it to the Vss pin when operating in single-chip or memory expansion mode. Connect it to the Vcc pin when in microprocessor mode. --> Connect it to the Vss pin when operating in single-chip or memory expansion mode after reset. Connect it to the Vcc pin when in microprocessor mode after reset. BYTE When operating in single-chip mode,connect this pin to VSS. --> When not using the external bus,connect this pin to VSS. Page 9 P50 to P57 In single chip mode, --> delate Page 10 Figure 1.2.1 Page 13 Figure 1.4.3 M30803FG --> M30803MG/FG (2) processor mode register C016 --> 0016 Page 20 to 23 Figure 1.5.1 to 1.5.4 Note addition Page 23 Figure 1.5.4 Note 2 addition C- 5 M16C/80 Group Revision History Version Contents for change Page 25 Figure 1.6.1, 1.6.2 Figure 1.6.1 is divided to Figure 1.6.1and 1.6.2 Page 30 Table 1.7.4 Page 34 Figure 1.7.3 Note addition Page 36 Line 3 the chip select control register --> the wait control registe Page 38, 39 Figure 1.7.6, 1.7.7 Page 42 Line 7 addition Note change Revision date When the main clock is stoped (bit 5 at address 000616 =1) or the mode is shifted to stop mode (bit 0 at address 000716 =1), the main clock division register (address 000C16) is set to the divided-8 mode. Page 42 (3)BCLK When shifting to stop mode, --> When main clock is stoped or shifting to stop mode, Page 43 Figure 1.8.4 CM0 Note 6 change, Note 7, 8 addition, CM1 Note 4 addition Page 44 Figure 1.8.5 Note 2 change Page 48 Line 5 When shifting to stop mode and reset, --> When shifting to stop mode, reset or stopping main clock, (12) Low power dissipation mode addition When the main clock is stoped, the main clock division register (address 000C16) is set to the division by 8 mode. Page 51 Figure 1.8.7. Clock transition Page 52 Line 9 addition Note 3, 4 addition Page 54 Software Interrupts (2) Overflow interrupt, "CMPX" addition Page 55 (2) Peripheral I/O interrupts * Bus collision detection/start, stop condition (UART2, UART3, UART4) interrupts --> change Page 57 * Variable vector tables addition Set an even address to the start address of vector table setting in INTB so that operating efficiency is increased. Page 58 Table 1.9.3 Bus collision detection/start, stop condition interrupts --> Bus collision detection, start/ stop condition detection interrupts Page 58 Table 1.9.3, page 68 Figure 1.9.8 Software interrupt number 40, 41 fault errir --> addition Page 71 Address match interrupt Line 7 addition _______ Page 72 (3) The NMI interrupt _______ * Do not reset the CPU with the input to the NMI pin being in the "L" state. --> * Signal of "L" level width more than 1 clock of CPU operation clock (BCLK) is necessary for _______ NMI pin. Page 72 (4) External interrupt Page 74 Figure 1.10.1 Page 76 Line 2 "DMAC is a function that to transmit 1 data of a source address (8 bits /16 bits) to a destination address when transmission request occurs. " addition. Page 76 Line 12 addition When writing to DSA2 and DSA3, set register bank select flag (B flag) to "1" and use LDC instruction to set SB and FB registers. Page 76 Figure 1.11.1 Page 77 Table 1.11.1 Transfer memory space (16 Mbyte space) --> addition C-6 M16C/80 Group Revision History Version Page 78 Figure 1.11.2 Page 80 Figure 1.11.4 Page 81 Figure 1.11.5 Contents for change Note :6 OR instruction --> OR instruction etc. DRCi * Transfer counter --> * Transfer count register Revision date DMAi, DSAi, DRAi Transfer count specification "(16 Mbytes area)" addition DRAi memory address counter --> memory address register Page 85 Line 9 addition Page 87 Fugure 1.12.1 Page 88 Fugure 1.12.2 Page 93 Table 1.13.2 (1) Internal factors, (2) External factors change "Timer B2 overflow" addition Timer A --> Timer B2 overflow (to timer A count source) Cout source * TB2 overflows, TAj overflows --> *TB2 overflows or underflows , TAj overflows or underflows Page 95 Figure 1.13.7 When using two-phase signal processing Note 3 --> addition Page 102 Figure 1.14.3 TBSR When reset 0016 --> 000XXXXXX16 b4-b0 When read, the value is "0" --> indeterminate Page 104 Table 1.14.2 Page 124 Figure 1.16.5 Cout source * TBj overflows --> *TBj overflows or underflows UiTB Note 1 delate Page 126-127 Figure 1.16.7 to 1.16.8 CRD change Page 130 Figure 1.16.11 SDHI Enabled <--> Disabled _______ _______ (a) Separate CTS/RTS pins function (UART0) Page 144 Page 146 Table 1.19.1 Addition in "Other things" Page 147 Figure 1.19.1 eFigure A "L" level returns from TxD due to the occurrence of a parity error. --> A "L" level returns from SIM card... Page 149 Figure 1.19.4 Note addition Page 150 Table 1.20.1 Note 1: LSB first --> MSB first, Note 3 Change Page 156 Figure 1.20.4 4 to 5 cycles --> 3 to 6 cycles Page 163, 165-169 Figure 1.21.2-Figure 1.21.8 ADCON1 Note 2-6 addition Page 170 Line 14,23 addition Page 171 Line 5 addition Page 172 Figure 1.22.3 Page 176 Figure 1.24.3 Note :3 D/A control register --> D/A register Page 178 Figure 1.25.1 Note 1 position change Page 178 Line 10 DRAM controler --> addition Page 179 Figure 1.25.2 Note 1 --> change Page 184 (1) Direction registers, (2) Port registers --> change Page 185 (4) Function select register B --> change Page 189 Figure 1.26.4 Port Pi direction register Note 2 addition Page 190 Figure 1.26.5 Page 191 Table 1.26.1 Page 192 Figure 1.26.6 Page 194 Figure 1.26.8 Port Pi register Note 1 and 2 addition Note addition Function select register A1 Note 1 addition Function select register B1 Note 2 addition Page 195 Figure 1.26.9 Function select register B3 Note 1 --> addition, PSL3_3-PSL3_6 change Page 196 Figure 1.26.13 Page 197 Figure 1.26.4 Port control register Note 2 addition Port Pi direction register Note 2 addition Page 200 Precaution on A/D converter (6) --> addition Page 203 Stop Mode and Wait Mode (2) all clock stop bits --> all clock stop control bits Page 203 Noise addition Page 203 Precaution on interrupt (1) line 7 --> addition C- 7 M16C/80 Group Revision History Version Contents for change Page 204 Making power consumption electricity small --> addition Page 207 Table 1.28.3 VT+ - VT- SCL2-SCL4, SDA2-SDA4 Addition Page 208 Table 1.28.5 Note Change Page 215 Table 1.28.22 tRP expression change Page 217-220 Figure 1.28.2-1.28.5 tw(WR) addition, th(BCLK-DB) delate Page 219, 220, 222, 223, 225 Figure 1.28.4, 1.28.5, 1.28.7, 1.28.8, 1.28.10 addition Page 225, 226 Figure 1.28.10, 1.28.11 th(BCLK-DB) -5 ns.min --> -7 ns.min Page 227 Figure 1.28.12 Refresh timing (self refresh) RAS timing Page 230 3V of electric characteristics addition Page 246 Table 1.29.1 Data hold --> addition Page 247 Figure 1.29.2 Package type 144P6Q --> 144P6Q-A Page 248 Flash memory line 5 change Page 250 Function outline Line 24 (Parallel ... function ) --> delate Page 269 Standard serial I/O mode Line 26 externl device --> external device ( programmer) Page 285 Figure1.31.21 programer --> peripheral unit ( programmer) Revision date Rev.D3 Page 43 Figure1.8.4 Note of the system clock control register 0-->addition Page 44 Line 4 Note-->addition Page 45 Table1.8.2 Note-->addition Page 71 Line 9 "Address match interrupt is not generated with a start instruction of interrupt routine."-->Delete Page 73 (6) Precaution of Address mach interrupt-->addition Page 79 Figure1.11.2 Note-->change Page 87 Precaution for DMAC-->addition Page 131 Figure1.16.11 Bit 7-->Must set to "1" in selecting IIC mode. Page 152 Figure1.20.1 Bit 7-->Must set to "1" in selecting IIC mode. Page 182 Addition Page 205 (3) Address match interrupt in Interrupt precautions-->addition Page 206 (2) DMAC-->addition Page 207 Precautions for using CLKOUT pin-->addition Page 210 Table1.28.3 Icc when clock stop Topr=25Co-->change Page 212 Table1.28.6 External clock input HIGH and LOW pulse waidth 22-->20 External clock rise and fall time 10-->5 Page 215, 216 Table1.28.19, 20 th(BCLK-DB)-->delete, tw(WR)-->addition Page 218 Table1.28.22 th(BCLK-DB) -5ns --> -7ns Page 233 Table1.28.23 Icc when clock stop Topr=25Co-->change Page 235 Table1.28.27 th(CAS-DB)-->addition Page 238, 239 Table1.28.39, 40 tw(WR) -->addition, th(BCLK-RD) 0ns-->-3ns Page 240 Table1.28.41 td(AD-ALE)=109/(f(BCLK)X2)-20 -->109/(f(BCLK)X2)-27 Page 241 Table1.28.42 th(BCLK-CAS) 0ns-->-3ns Page 242 Figure1.28.15 tac1(RD-DB) min-->max, tac1(AD-DB) min-->max Page 243 Figure1.28.16 tac2(RD-DB) min-->max, tac2(AD-DB) min-->max Page 244, 255 Figure1.28.17 2 wait, Figure1.28.18 3 wait-->addition Page 246 Figure1.28.19 tac3(AD-DB)-->addition, tsu(DB-RD)-->tsu(DB-BCLK), th(BCLK-RD) 0ns -->3ns, td(AD-ALE)=(tcyc/2-20)ns--> ... -27)ns Page 247 Figure1.28.20 Addition Page 248, 249 Figure1.28.21, 1.28.22 -->addition 19/6/'00 C-8 M16C/80 Group Revision History Version Contents for change Page 250 Figure1.28.23 th(BCLK-DB)-->th(CAS-DB) Page 251 Figure 1.28.24 td(DB-CAS)-->tsu(DB-CAS), th(BCLK-CAS)-->th(BCLK-DB) Page 252 Figure1.28.25 td(CAS-RAS)-->tsu(CAS-RAS) Page 255 Table1.29.1 Power supply (under planning)-->delete, Program/erase voltage f(XIN)-->f(BCLK), 2.7V-5.5V-->delete Revision date Rev.E 144-pin version description addition Pages 1, 6 *Supply voltage --> external ROM version addition Page 7 (3) Package 144P6Q --> 144P6Q-A Page 21 Figure 1.4.4 (111) Function select register C 0016 --> 0XXXXXX0 (119) Function select register B3 ?0000??? --> 00000X0X Similarly, page 202 Figures 1.26.11 When reset ?0000??? --> 00000X0X Figures 1.26.12 When reset 0016 --> 0XXXXXX0 Page 28 Figure 1.6.2 ROMless version addition Page 29 Figure 1.6.3 External area 0 to 3 addition Page 34 Addition _______ _______ 09/02/'01 Page 37 Figure 1.7.4 Input RDY signal at i + 1 cycles for i wait --> RDY signal received timing for i wait: i +1 Page 46 Figure 1.8.4 System clock control register 0 CM0 --> contents of the Function changed, Notes 10, 11 addition Page 48 On the second line from the bottom, 'Although stop mode ... must be set to "1".' -->addition _______ _______ _______ _______ _______ _______ _______ ___ _________ Page 49 Table 1.8.4 CS0 to CS3 --> CS0 to CS3, BHE WR, BHE, WRL, WRH, W, CASL _______ _______ _______ ______ _________ --> WR, WRL, WRH, DW, CASL Page 52 Table 1.8.6 CM0i: Clock control register 0 (address 000616) bit i, MCDi: Main clock division register (address 000C16) bit i --> addition Page 60 * Vector table dedicated for emulator Interrupt vector address (address 00002016 to 00002316)-->... (address 00002016 to 00002216) Page 69 Interrupt priority 'the interrupt that a request came to most in the first place is accepted at first, and then,' --> delete Page 75 (6) Explanation of No.1 and No. 2 are partly revised. Page 76, 77 From "* To return from an interrupt..." to the end of page 77 --> addition Page 78 "In the stop...released." on the third line from the bottom --> addition Page 79 Figure 1.10.2 Notes 10, 11 --> addition Page 87 Figure 1.11.6 is partly revised. Page 88 Table for "Coefficient j, k" is partly revised. Page 89 Figure 1.11.7 is partly revised. Page 90 Explanation of (3) is partly revised. Page 94 Figure 1.13.3 Timer Ai register -->Notes 2 to 4 addition, *Pulse width modulation mode (8-bit PWM) --> Values that can be set is changed, Up/down flag --> Note addition Page 97 Figure 1.13.6 --> change Page 98 Table 1.13.3 --> Note 2 addition, *Normal processing operation --> *Normal processing operation (Timer A2 and timer A3), *Multiply-by-4 processing operation --> *Multiply-by-4 processing operation (Timer A3 and timer A4) Page 99 Figure 1.13.7 Timer Ai mode register (When using two-phase pulse signal process- C- 9 M16C/80 Group Revision History Version Contents for change ing) --> "Note 2 Timer A2 is fixed to ... multiply-by-4 processing operation." is added, note 3 change Page 109 Figure 1.14.6 Note 1 It is indeterminate when reset --> addition Page 112 Figure 1.15.2 Dead time timer-->Note 1 addition, Timer B2 interrupt occurrence frequency set counter-->Note 3 addition Page 113 Notes 2, 3 --> addition Page 114 three-phase waveform mode --> three phase PWM output mode Page 128 Figure 1.16.5 UARTi bit rate generator --> Note 2 addition Page 128 Figure 1.16.5 UARTi transmit buffer register, UARTi bit rate generator-->Note 1 addition Page 129 Figure 1.16.6 UARTi transmit/receive mode register-->Note 2 addition in CKDIR of UART mode Page 133 Figure 1.16.10 UART transmit/receive control register 2-->Note delete Page 136 Note 2, Page 143 Note 3 ... the UARTi receive interrupt request bit is not set to "1" --> ... the UARTi receive interrupt request bit will not change Page 145 Figure 1.18.1 UARTi transmit/receive mode register (i=0,1) --> Note 1 addition, UARTi transmit/receive mode register (i=2 to 4) --> Note 2 addition Page 157 On the 12th line, ... allocated to bit 3 in UART2 transmission buffer register 1 (address 033F16) ... --> ... allocated to bit 11 in UART2 transmission buffer register (address 033E16) ... Page 161 < Master Mode (TxDi and RxDi are selected, DINC = 0) > ..., and the STxDi, SRxDi and CLKi pins ...--> ..., and the TxDi, RxDi and CLKi pins ... Page 165 Table 1.21.1 Absolute precision --> change Page 170 Table 1.21.3 Reading of result of A/D converter --> (at any time) addition Page 173 Table 1.21.6 Input pin --> change to AN0 to AN7, With emphasis on the pin --> addition Page 182 On the second line from the bottom, ..., and dummy cycle for refresh ... --> ..., and processing necessary for dummy cycle to refresh DRAM ... Page 183 Figure 1.25.2 is partly revised. Page 189 On the 18th and 27th lines, page 194 Port Pi direction register Note 2, page 196 Port Pi register Note 1 ... for setting of bus control such as address bus and data bus is _____ _______ _______ _______ _____ _________ Revision date ... --> of pins A0 to A22, A23, D0 to D15, MA0 to MA12, CS0 to CS 3, WRL/WR/CASL, _______ _______ _______ _____ _____ _________ _________ _______ WRH/BHE/CASH, RD/DW, BCLK/ALE/CLKOUT, HLDA/ALE, HOLD, ALE/RAS, and _______ RDY are ... Page 203 Figure 1.26.13 is partly revised. Page 207, 208 Timer A (event counter mode) --> (3) addition, Timer A (one-shot timer mode) --> (2) changes to (3), (2) and (4) addition Page 209 Timer B (pulse period/pulse width measurement mode) --> (3) addition ________ ________ Page 212 to 214 (2) NMI interrupt *The NMI pin also serves as P85, ... *Signal of "L" level ... --> addition (3) Address match interrupt From "* To return from an interrupt..." to "; Interrupt completed" on page 77 --> addition (4) External interrupt, (5) Rewrite the interrupt control register --> addition Page 215 Explanation of (3) is partly revised. __________ Page 215 HOLD signal --> addition Page 216 DRAM controller --> addition C - 10 M16C/80 Group Revision History Version Contents for change Page 217 Setting the registers, Notes on the microprocessor mode ... single-chip mode ->addition Page 217 Explanation of note on Flash memroy version is added. Page 219 Note 2 80mA --> -80mA Page 220 Table 1.28.3 Ta --> Topr, Note2 --> addition Pages 220, 243 Tables 1.28.3, 1.28.23 Icc Power supply current ROMless version --> addition, Ta --> Topr, Note 2 --> addition Page 227 Calculation for td(AD-ALE) is partly revised. Page 234, 235 Figures 1.28.6 and 1.28.7 Timing for td(AD-ALE) is partly revised. Page 243 Table 1.28.23 Topr=25C, when clock is stopped: 2.0A --> 1.0A, Notes 1, 2 --> addition Page 250 Table 1.28.41 th(BCLK-RD) Min. 0 ns --> -3 ns Pages 251, 258 to 262 Table 1.28.42, figures 1.28.21 to 1.28.25 th(BCLK-CAS): -3 ns --> 0 ns Pages 251, 259, 261 Table 1.28,42, figures 1.28.22, 1.28.24 th(BCLK-DW): 0 ns --> -3 ns Page 266 Table 1.29.2 M30805FGGP RAM capacity 24 Kbytes --> 20 Kbytes Page 270 Figure 1.30.1 Flash memory control register 0 Note 1 Also write to this bit ... "H" level. --> addition Page 273 (3) Disabling erase or ... serial I/O mode --> delete, (7), (8) --> addition Page 285 Note --> addition Page 288 --> addition Pages 291, 307 Tables 1.31.1, 1.31.5 Note 2 ... status register 1 data --> ... status register data 1 Page 319 144P6Q-A version --> addition - Revision date Rev.E1 Page 32 Table 1.7.3 --> change 16/03/'01 10/05/'01 Rev.E2 Page 28 Figure 1.6.1 Note 8 --> addition Page 88 Table for "Coefficient j, k" is partly revised. Rev.E3 Page 7 Figure 1.1.5 and Table 1.1.2, product names --> added Page 8 Figure 1.1.6, Boot loader (BL) -->addition Page 85 Figure 1.11.5, DMAi SFR address register, Note 2, destination fixed address --> source fixed address, source fixed address --> destination fixed address Page 218 Precaution of boot loader --> addition Page 319 Appendix boot loader --> addition Rev.1.0 Page 4 Figure 1.3 XOUT --> revised Page 18 Figure 4.1 and 4.2 --> revised Page 20 Figure 4.3, Timer B3 mode register value 00?x0000 --> 00??0000 Three-phase output buffer register 0, 1 value 0016 --> 3F16 Page 21 Figure 4.4, Timer B0 mode register value 00?x0000 --> 00??0000 UART transmit/receive control register 2 value x0000000 --> x0xx0000 Flash memory control register1 value ?????0?? --> ????0??? Page 22 (address006A16) DM1IC --> DM2IC revised Page 24 (address037016) UCON2 --> UCON revised Page 26 "Carry out a software reset after oscillation of main clock is fully stable"--> added, (1), (2) --> revised Page 27 Figure 6.1 10:Inhibited --> 10:Must not be set 20/08/'01 02/08/'05 C- 11 M16C/80 Group Revision History Version Contents for change Revision date 02/08/'05 Rev.1.0 Page 46, 79 Note 9 'Do not set CM04 and CM07 simultaneously.' --> deleted Note 9 'In addition,do not rewrite CM04 and CM05 simultaneously' --> added Page 48 'The priority level of the interrupt which is not used to cancel stop mode,must have been changed to 0.' , 'If only a hardware reset or an NMI interrupt is used to cancel stop mode,change the priority level of all interrupt to 0,then shift to stop mode.' --> added Page 50 'The priority level of the interrupt which is not used to cancel wait mode,must have been changed to 0.', 'If only a hardware reset or an NMI interrupt is used to cancel stop mode,change the priority level of all interrupt to 0,then shift to wait mode.' --> added Page 54 Figure 8.7 The arrow of CM07="1" and CM05="1" deleted. Page 70 Interrupt request accepted. To CLK --> Interrupt request priority detection results output(to clock generation circuit) Page 74 'Signal of "L" level width...for NMI pin.' --> 'Signals input to the NMI ...from the operation clock of CPU.' Page 75 (5) Rewrite the interrupt control register 'When attempting to clear the interrupt...Instructions :MOV' --> added Page 78 'Therefore,we recom-mend using the watchdog timer to improve reliability of a system.' --> added Page 90 '2 instructions' --> '26 cycles', Program example revised, (4) --> added Page 91 (5) Recommended procedure for starting DMA transfer--> added Page 92 'Count source for each timer becomes an operation clock for timer operation as counting and reloading,etc.' --> added, Figure 12.1 One-shot mode --> One-shot timer mode Page 95 Figure 13.1 Up/Down flag Note2 --> added Figure13.3 Timer Ai register (FFFF --> FFFE revised) Page 99 'TAiIN pin function', 'TAiOUT pin function' specification revised Two-phase pulse input (Set the corresponding function select registers A to I/O port,and port direction register to "0") Page 103, 104 Selected by event/trigger select register --> Selected by event/trigger select bit Page 106 Figure 14.2, 11: Inhibited --> 11: Must not be set Page 109 TBiIN Pin function Programable I/O port or --> added, Figure 14.5 11: Inhibited --> 11: Must not be set Page 110 Interrupt request generation timing, Figure 14.6 'When an overflow occurs.(Simultaneously,the timer Bi overflow flag... the timer Bi mode register.)' --> 'Timer overflow.When an overflow occurs... the timer start flag is set to "1". Page 112 Figure 15.1 Note 5 Rewrite the INV00 to INV02 and INV06 bits when the timers A1,A2,A4 and B stop. -->added Page 113 Figure 15.2 Note 1--> added Note 4 --> added Three-phase output buffer register 0, 1 0016 --> 3F16 Page 114 Figure 15.3, Timer Ai register value Note 2 --> added Page 130 to 132 Inhibited --> Must not be set Page 134 Figure 16.10 UART transmit/receive control register 2 x0000000 --> x0xx0000 C - 12 M16C/80 Group Revision History Version Contents for change Revision date 02/08/'05 Rev.1.0 Page 136 Figure 16.12 Special mode register 3 'SDAi digital delay time set bit' --> revised 001: 1 to 2 cycles of 1/f(XIN) 010: 1 to 2 cycles of 1/f(XIN) 011: 1 to 2 cycles of 1/f(XIN) 100: 1 to 2 cycles of 1/f(XIN) 101: 1 to 2 cycles of 1/f(XIN) 110: 1 to 2 cycles of 1/f(XIN) 111: 1 to 2 cycles of 1/f(XIN) Page 150 Figure18.5 /P --> P revised Page 152 Typical transmit/receive timing in UART mode (compliant with the SIM interface) Diagram revised Page 153 (a) Function for outputting a parity error signal With the error signal output enable bit ... TxDi pin when a parity error is detected. --> During reception,with the error signal output enable bit ... TxDi pin when a parity error is detected. In step with this function, ... of a parity error signal. --> deleted Therefore parity error signals ... interrupt program. --> added And during transmission, ... of the transfer clock. --> added Page 160 the baud rate generator --> the UARTi bit rate generator baud rate generator stops counting. -->the count stops Page 160 UART2 Special Mode Register 2 (Address 033616) --> UARTi Special Mode Register 2(i=2 to 4) (Address 033616,032616,02F616), SCL2 --> SCLi, SDA2 --> SDAi, UART2 --> UARTi revised Page 161 UART2 Special Mode Register 3(Address 033516) --> UARTi Special Mode Register 3(i=2 to 4 )(Address 033516,032516,02F516) SDA2 --> SDSi revised Page 163 Figure 20.6 Special mode register 3 'SDAi digital delay time set bit' --> revised 001: 1 to 2 cycles of 1/f(XIN) 010: 1 to 2 cycles of 1/f(XIN) 011: 1 to 2 cycles of 1/f(XIN) 100: 1 to 2 cycles of 1/f(XIN) 101: 1 to 2 cycles of 1/f(XIN) 110: 1 to 2 cycles of 1/f(XIN) 111: 1 to 2 cycles of 1/f(XIN) Page 176 Set the function select register A... --> Set the function select register A3... Page 193 Figure 26.2, P74, P75, P80 move to (inside dotted-line included) Page 208 Timer --> added Page 209 (5) If an exernal triger input is used to start counting, the next external triger input must be avoided within 300ns before the timer A reaches "0000h". --> added Page 210 Timer B (pulse period/pulse width measurement mode) (4) --> added C- 13 M16C/80 Group Revision History Version Rev.1.0 Contents for change Page 210 Stop Mode and Wait Mode (4),(5) --> added (4) Follow the procedure below to enter stop mode. * Initial Setting Set each interrupt priority level after setting the minimum interrupt priority level required to exit stop mode and wait mode, controlled by the RLVL2 to RLVL0 bits in the RLVL register, to "7". * Before Execution of WAIT Instruction [1] Set the interrupt priority level of the interrupt being used to exit stop mode [2] Set the interrupt priority levels of the interrupts not being used to exit stop mode [3] Set the IPL in the FLG register. Then set the minimum interrupt priority level required to exit stop mode and wait mode to the same level as the IPL. (Interrupt priority level of the interrupt used to exit stop mode > mimimum inter rupt priority level to exit stop mode interrupt priority level of the interrupts not used to exit stop mode) [4] Set the I flag to "1" [5] Set the CM10 bit in the CM1 register to "1" (all clocks stop) after setting the PRC0 bit in the PRCR register to "1" (write enabled) * After Exiting Stop Mode Set the interrupt priority level required to exit stop mode to "7" immediately after exiting stop mode. (5) When microcomputer enters stop mode again after exiting from stop mode us ing the NMI interrupt, use the following procedure to set the CM10 bit to "1". [1] Exit stop mode using the /NMI interrupt [2] Generate a dummy interrupt [3] Set the CM10 bit to "1" example: INT BSET #63 CM1 ; Dummy interrupt ; All clocks stopped (in stop mode) Revision date 02/08/'05 ; /*for dummy interrupt* / DUMMY: REIT C - 14 M16C/80 Group Revision History Version Rev.1.0 Contents for change Page 210 (2) --> (2)Wait and (3)Stop divided (2) When entering wait mode, the instruction queue reads ahead to instructions following the WAIT instruction, and the program stops. The next instruction may be executed before entering wait mode, depending on the combination of instructions and their execution timing. Therefore, write at least 4 NOP instructions following the WAIT instruction. (3) When entering stop mode, the instruction queue reads ahead to instructions to set the CM10 bit to "1", and the program stops. The next instruction may be executed, before entering stop mode or executing the interrupt routine to exit stop mode, depending on the combination of instructions and their execution timing. Therefore, write a jmp.b instruction and at least 4 NOP instructions following the instruction to enter stop mode as shown below. bset 0,prcr ; Removing protection bset 0,cm1 jmp.b LABEL_001 LABEL_001: nop nop nop nop mov.b #0,prcr ; Stopping all clocks(Entering stop mode) ; Executing jmp.b instruction(Jump to the next instruction soon ; with adding no instruction between jmp.b and LABEL.) ; nop(1) ; nop(2) ; nop(3) ; nop(4) ; Setting protection Revision date 02/08/'05 * * * Page 211 (4) (6) --> Description revised Page 211 A/D Converter (6) --> added Page 214 (2)The NMI interrupt 'Signal of "L" level width...for NMI pin.' --> 'Signals input to the NMI ...from the operation clock of CPU.' Page 217 (5) Rewrite the interrupt control register 'When attempting to clear the interrupt...Instructions :MOV' --> added Page 217 DMAC '2 instructions' --> '26 cycles', Program example revised Page 218 (4), (5) --> added _________ Page 219 HOLD signal When P40 to P47 and P50 to P52 are set to... will not become high-impedance ports. --> added Memory expansion mode added Page 221 Notes on the microprocessor mode and transition after shifting from the microprocessor mode to the memory expansion mode / sigle-chip mode --> deleted C- 15 M16C/80 Group Revision History Version Contents for change Revision date 02/08/'05 Rev.1.0 Page 221 Notes on CNVSS pin reset at "H" level --> added Page 222 Microprocesser mode or Memory expansion mode --> added Page 222 Microprocessor(Usage Precaution) --> added If the software reset is executed when the CNVss pin is connected to Vcc to start up in microprocessor mode, write at least three NOP instructions following the writing instruction to the PM0 Register. example: mov.b #02H,PRCR bset 3,PM0 nop nop nop nop Page 227 Table 28.3 , Table 28.4 --> added Page 249 (Note 4) contained in the title of Table 28.23 --> deleted Page 274 Read data from an even address in the user ROM area when reading the status register. --> added Page 278 main clock frequency --> BCLK Page 279 Table 30.1 Read status register command's second bus cycle 'X' --> 'X(Note 6) Note 6 (that is an even address) --> added Page 286 Figure 30.8 (When reading the status register,set an even number address in the user ROM area). --> added Page 287 Figure 30.9 ROM code protect level 2 set bit --> deleted, Notes 3 to 5 --> added Page 289 In this mode, the M16C/80 (flash memory version) operates in a manner similar to the flash memory M5M29FB/T800 from Mitsubishi. Since there are some differences with regard to the functions not available with the microcomputer and matters related to memory capacity, the M16C/80 cannot be programed by a pro gramer for the flash memory. --> deleted Page 7,271,323 Mitsubishi-->Renesas Page 289 Mitsubishi -->deleted revised ; or "mov.b #8BH,PM0" (instruction to execute software reset) ; write at least three NOP instructions Page 294 from Mitsubisi --> from the factory revised Page 323 Mitsubisi --> the following revised All Pages Words standardized: A/D converter, D/A converter and XY converter All Pages Figure number and Table number change C - 16 RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER HARDWARE MANUAL M16C/80 Group Publication Data : Rev.B Oct. 19, 1998 Rev.1.00 Aug. 02, 2005 Published by : Sales Strategic Planning Div. Renesas Technology Corp. (c) 2005. Renesas Technology Corp., All rights reserved. Printed in Japan. M16C/80 Group Hardware Manual 2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan |
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